[turbofan] Add backend support for load/store float32 values.

src/compiler/x64/instruction-codes-x64.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
 #define V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 42 matching lines @@
   V(SSEFloat64Cmp)                 \
   V(SSEFloat64Add)                 \
   V(SSEFloat64Sub)                 \
   V(SSEFloat64Mul)                 \
   V(SSEFloat64Div)                 \
   V(SSEFloat64Mod)                 \
   V(SSEFloat64ToInt32)             \
   V(SSEFloat64ToUint32)            \
   V(SSEInt32ToFloat64)             \
   V(SSEUint32ToFloat64)            \
-  V(X64Movsd)                      \
   V(X64Movsxbl)                    \
   V(X64Movzxbl)                    \
   V(X64Movb)                       \
   V(X64Movsxwl)                    \
   V(X64Movzxwl)                    \
   V(X64Movw)                       \
   V(X64Movl)                       \
   V(X64Movsxlq)                    \
   V(X64Movq)                       \
+  V(X64Movsd)                      \
+  V(X64Movss)                      \
   V(X64StoreWriteBarrier)
 
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the
 // code generator after register allocation which assembler method to call.
 //
 // We use the following local notation for addressing modes:
 //
@@ skipping 12 matching lines @@
   V(MR1I) /* [%r1 + %r2 + K] */        \
   V(MR2I) /* [%r1 + %r2*2 + K] */      \
   V(MR4I) /* [%r1 + %r2*4 + K] */      \
   V(MR8I) /* [%r1 + %r2*8 + K] */
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_X64_INSTRUCTION_CODES_X64_H_