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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 500343002: [turbofan] Add backend support for load/store float32 values. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: REBASE Created 6 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after
43 V(ArmVmulF64) \ 43 V(ArmVmulF64) \
44 V(ArmVmlaF64) \ 44 V(ArmVmlaF64) \
45 V(ArmVmlsF64) \ 45 V(ArmVmlsF64) \
46 V(ArmVdivF64) \ 46 V(ArmVdivF64) \
47 V(ArmVmodF64) \ 47 V(ArmVmodF64) \
48 V(ArmVnegF64) \ 48 V(ArmVnegF64) \
49 V(ArmVcvtF64S32) \ 49 V(ArmVcvtF64S32) \
50 V(ArmVcvtF64U32) \ 50 V(ArmVcvtF64U32) \
51 V(ArmVcvtS32F64) \ 51 V(ArmVcvtS32F64) \
52 V(ArmVcvtU32F64) \ 52 V(ArmVcvtU32F64) \
53 V(ArmVldr32) \
54 V(ArmVstr32) \
53 V(ArmVldr64) \ 55 V(ArmVldr64) \
54 V(ArmVstr64) \ 56 V(ArmVstr64) \
55 V(ArmLdrb) \ 57 V(ArmLdrb) \
56 V(ArmLdrsb) \ 58 V(ArmLdrsb) \
57 V(ArmStrb) \ 59 V(ArmStrb) \
58 V(ArmLdrh) \ 60 V(ArmLdrh) \
59 V(ArmLdrsh) \ 61 V(ArmLdrsh) \
60 V(ArmStrh) \ 62 V(ArmStrh) \
61 V(ArmLdr) \ 63 V(ArmLdr) \
62 V(ArmStr) \ 64 V(ArmStr) \
(...skipping 16 matching lines...) Expand all
79 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 81 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
80 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 82 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
81 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 83 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
82 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 84 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
83 85
84 } // namespace compiler 86 } // namespace compiler
85 } // namespace internal 87 } // namespace internal
86 } // namespace v8 88 } // namespace v8
87 89
88 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 90 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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