As a first step towards implementing thumb2, add code for...

src/arm/assembler-thumb2-inl.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 204 matching lines @@
   if (buffer_space() <= kGap) {
     GrowBuffer();
   }
   if (pc_offset() >= next_buffer_check_) {
     CheckConstPool(false, true);
   }
 }
 
 
 void Assembler::emit(Instr x) {
+  forceArmMode();
   CheckBuffer();
   *reinterpret_cast<Instr*>(pc_) = x;
   pc_ += kInstrSize;
 }
 
+void Assembler::emitThumb(ThumbInstr x) {
+  forceThumbMode();
+  CheckBuffer();
+  *reinterpret_cast<ThumbInstr*>(pc_) = x;
+  pc_ += kThumbSize;
+}
+
 
 Address Assembler::target_address_address_at(Address pc) {
   Instr instr = Memory::int32_at(pc);
   // Verify that the instruction at pc is a ldr<cond> <Rd>, [pc +/- offset_12].
   ASSERT((instr & 0x0f7f0000) == 0x051f0000);
   int offset = instr & 0xfff;  // offset_12 is unsigned
   if ((instr & (1 << 23)) == 0) offset = -offset;  // U bit defines offset sign
   // Verify that the constant pool comes after the instruction referencing it.
   ASSERT(offset >= -4);
   return pc + offset + 8;
@@ skipping 18 matching lines @@
   //   CPU::FlushICache(pc, sizeof(target));
   // However, on ARM, no instruction was actually patched by the assignment
   // above; the target address is not part of an instruction, it is patched in
   // the constant pool and is read via a data access; the instruction accessing
   // this address in the constant pool remains unchanged.
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM_ASSEMBLER_THUMB2_INL_H_