Index: src/arm64/lithium-codegen-arm64.cc |
diff --git a/src/arm64/lithium-codegen-arm64.cc b/src/arm64/lithium-codegen-arm64.cc |
index 02cfbb8155104c58a64a18f86967d358fac722c6..1962c98bdf5f68a7b004a241f0846c69150f1295 100644 |
--- a/src/arm64/lithium-codegen-arm64.cc |
+++ b/src/arm64/lithium-codegen-arm64.cc |
@@ -4926,32 +4926,33 @@ void LCodeGen::DoShiftS(LShiftS* instr) { |
Register left = ToRegister(instr->left()); |
Register result = ToRegister(instr->result()); |
- // Only ROR by register needs a temp. |
- DCHECK(((instr->op() == Token::ROR) && right_op->IsRegister()) || |
- (instr->temp() == NULL)); |
- |
if (right_op->IsRegister()) { |
Register right = ToRegister(instr->right()); |
+ |
+ // JavaScript shifts only look at the bottom 5 bits of the 'right' operand. |
+ // Since we're handling smis in X registers, we have to extract these bits |
+ // explicitly. |
+ __ Ubfx(result, right, kSmiShift, 5); |
+ |
switch (instr->op()) { |
case Token::ROR: { |
- Register temp = ToRegister(instr->temp()); |
- __ Ubfx(temp, right, kSmiShift, 5); |
- __ SmiUntag(result, left); |
- __ Ror(result.W(), result.W(), temp.W()); |
+ // This is the only case that needs a scratch register. To keep things |
+ // simple for the other cases, borrow a MacroAssembler scratch register. |
+ UseScratchRegisterScope temps(masm()); |
ulan
2014/08/21 11:13:04
Didn't we want to reduce usage of scratch register
|
+ Register temp = temps.AcquireW(); |
+ __ SmiUntag(temp, left); |
+ __ Ror(result.W(), temp.W(), result.W()); |
__ SmiTag(result); |
break; |
} |
case Token::SAR: |
- __ Ubfx(result, right, kSmiShift, 5); |
__ Asr(result, left, result); |
__ Bic(result, result, kSmiShiftMask); |
break; |
case Token::SHL: |
- __ Ubfx(result, right, kSmiShift, 5); |
__ Lsl(result, left, result); |
break; |
case Token::SHR: |
- __ Ubfx(result, right, kSmiShift, 5); |
__ Lsr(result, left, result); |
__ Bic(result, result, kSmiShiftMask); |
if (instr->can_deopt()) { |