| Index: src/ic/arm/ic-conventions-arm.cc
|
| diff --git a/src/ic/arm/ic-conventions-arm.cc b/src/ic/arm/ic-conventions-arm.cc
|
| new file mode 100644
|
| index 0000000000000000000000000000000000000000..5e22858b8077e74cfc44339cc41e6a31dd3b47a6
|
| --- /dev/null
|
| +++ b/src/ic/arm/ic-conventions-arm.cc
|
| @@ -0,0 +1,41 @@
|
| +// Copyright 2012 the V8 project authors. All rights reserved.
|
| +// Use of this source code is governed by a BSD-style license that can be
|
| +// found in the LICENSE file.
|
| +
|
| +#include "src/v8.h"
|
| +
|
| +#if V8_TARGET_ARCH_ARM
|
| +
|
| +#include "src/codegen.h"
|
| +#include "src/ic/ic-conventions.h"
|
| +
|
| +namespace v8 {
|
| +namespace internal {
|
| +
|
| +// IC register specifications
|
| +const Register LoadConvention::ReceiverRegister() { return r1; }
|
| +const Register LoadConvention::NameRegister() { return r2; }
|
| +
|
| +
|
| +const Register VectorLoadConvention::SlotRegister() {
|
| + DCHECK(FLAG_vector_ics);
|
| + return r0;
|
| +}
|
| +
|
| +
|
| +const Register FullVectorLoadConvention::VectorRegister() {
|
| + DCHECK(FLAG_vector_ics);
|
| + return r3;
|
| +}
|
| +
|
| +
|
| +const Register StoreConvention::ReceiverRegister() { return r1; }
|
| +const Register StoreConvention::NameRegister() { return r2; }
|
| +const Register StoreConvention::ValueRegister() { return r0; }
|
| +
|
| +
|
| +const Register StoreConvention::MapRegister() { return r3; }
|
| +}
|
| +} // namespace v8::internal
|
| +
|
| +#endif // V8_TARGET_ARCH_ARM
|
|
|