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Side by Side Diff: include/configs/chromeos/tegra2/seaboard/recovery.h

Issue 4841001: Tegra2: implement Warmboot code and lp0_vec (Closed) Base URL: http://git.chromium.org/git/u-boot-next.git@chromeos-v2010.09
Patch Set: Add GPL headers & fix some 80-column issues Created 10 years ago
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1 /* 1 /*
2 * (C) Copyright 2010 2 * (C) Copyright 2010
3 * NVIDIA Corporation <www.nvidia.com> 3 * NVIDIA Corporation <www.nvidia.com>
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
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34 34
35 #define CONFIG_CONSOLE_MUX 1 35 #define CONFIG_CONSOLE_MUX 1
36 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 36 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
37 37
38 /* UARTD: keyboard satellite board uart, default */ 38 /* UARTD: keyboard satellite board uart, default */
39 #define CONFIG_SYS_NS16550_COM1 NV_ADDRESS_MAP_APB_UARTD_BASE 39 #define CONFIG_SYS_NS16550_COM1 NV_ADDRESS_MAP_APB_UARTD_BASE
40 40
41 /* UARTA: debug board uart */ 41 /* UARTA: debug board uart */
42 #define CONFIG_SYS_NS16550_COM2 NV_ADDRESS_MAP_APB_UARTA_BASE 42 #define CONFIG_SYS_NS16550_COM2 NV_ADDRESS_MAP_APB_UARTA_BASE
43 43
44 #ifdef CONFIG_TEGRA2_LP0
45 #define CONFIG_EXTRA_ENV_SETTINGS \
46 CONFIG_TEGRA_ENV_SETTINGS \
47 "platform_extras=mem=384M@0M nvmem=128M@384M mem=512M@512M "\
48 "lp0_vec="TEGRA_LP0_SIZE_STR"@"TEGRA_LP0_DEFAULT_ADDR_STR "\0" \
49 "stdin=serial,tegra-kbc\0" \
50 "stdout=serial\0" \
51 "stderr=serial\0"
52 #else
44 #define CONFIG_EXTRA_ENV_SETTINGS \ 53 #define CONFIG_EXTRA_ENV_SETTINGS \
45 CONFIG_TEGRA_ENV_SETTINGS \ 54 CONFIG_TEGRA_ENV_SETTINGS \
46 "platform_extras=mem=384M@0M nvmem=128M@384M mem=512M@512M\0" \ 55 "platform_extras=mem=384M@0M nvmem=128M@384M mem=512M@512M\0" \
47 "stdin=serial,tegra-kbc\0" \ 56 "stdin=serial,tegra-kbc\0" \
48 "stdout=serial\0" \ 57 "stdout=serial\0" \
49 » "stderr=serial\0" \ 58 » "stderr=serial\0"
59 #endif
50 60
51 #define LINUX_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD 61 #define LINUX_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD
52 #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 //lp1, 1GB 62 #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 //lp1, 1GB
53 63
54 #define CONFIG_I2CP_PIN_MUX 1 64 #define CONFIG_I2CP_PIN_MUX 1
55 #define CONFIG_I2C1_PIN_MUX 1 65 #define CONFIG_I2C1_PIN_MUX 1
56 #define CONFIG_I2C2_PIN_MUX 2 66 #define CONFIG_I2C2_PIN_MUX 2
57 #define CONFIG_I2C3_PIN_MUX 1 67 #define CONFIG_I2C3_PIN_MUX 1
58 68
59 #define CONFIG_SYS_MEMTEST_START 0x0000 69 #define CONFIG_SYS_MEMTEST_START 0x0000
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75 * and undef or delete the CONFIG_ENV_IS_NOWHERE (if present). 85 * and undef or delete the CONFIG_ENV_IS_NOWHERE (if present).
76 * Note that you MUST change the ENV_OFFSET to be beyond the BCT/BL area! 86 * Note that you MUST change the ENV_OFFSET to be beyond the BCT/BL area!
77 */ 87 */
78 #if 0 88 #if 0
79 #define CONFIG_ENV_IS_IN_SPI_FLASH 89 #define CONFIG_ENV_IS_IN_SPI_FLASH
80 #define CONFIG_ENV_SECT_SIZE 0x1000 /* 4K sectors */ 90 #define CONFIG_ENV_SECT_SIZE 0x1000 /* 4K sectors */
81 #define CONFIG_ENV_OFFSET 0x0 /* DANGER! for test, use offset != 0 */ 91 #define CONFIG_ENV_OFFSET 0x0 /* DANGER! for test, use offset != 0 */
82 #endif 92 #endif
83 93
84 #endif //__configs_chromeos_tegra2_seaboard_recovery_h__ 94 #endif //__configs_chromeos_tegra2_seaboard_recovery_h__
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