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1 /* | 1 /* |
2 * (C) Copyright 2010 | 2 * (C) Copyright 2010 |
3 * NVIDIA Corporation <www.nvidia.com> | 3 * NVIDIA Corporation <www.nvidia.com> |
4 * | 4 * |
5 * See file CREDITS for list of people who contributed to this | 5 * See file CREDITS for list of people who contributed to this |
6 * project. | 6 * project. |
7 * | 7 * |
8 * This program is free software; you can redistribute it and/or | 8 * This program is free software; you can redistribute it and/or |
9 * modify it under the terms of the GNU General Public License as | 9 * modify it under the terms of the GNU General Public License as |
10 * published by the Free Software Foundation; either version 2 of | 10 * published by the Free Software Foundation; either version 2 of |
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113 */ | 113 */ |
114 #define CONFIG_TEGRA2_I2C | 114 #define CONFIG_TEGRA2_I2C |
115 | 115 |
116 #ifdef CONFIG_TEGRA2_I2C | 116 #ifdef CONFIG_TEGRA2_I2C |
117 #define CONFIG_CMD_I2C | 117 #define CONFIG_CMD_I2C |
118 #define CONFIG_I2C_MULTI_BUS 1 | 118 #define CONFIG_I2C_MULTI_BUS 1 |
119 #define CONFIG_SYS_MAX_I2C_BUS 4 | 119 #define CONFIG_SYS_MAX_I2C_BUS 4 |
120 #define CONFIG_SYS_I2C_SPEED 100000 | 120 #define CONFIG_SYS_I2C_SPEED 100000 |
121 #endif | 121 #endif |
122 | 122 |
| 123 /* make sure the following 2 defines have the same values (_STR is the string of
TEGRA_LP0_DEFAULT_ADDR) */ |
| 124 #define TEGRA_LP0_DEFAULT_ADDR 0x1C406000 /* inside carveo
ut memory region */ |
| 125 #define TEGRA_LP0_DEFAULT_ADDR_STR "0x1C406000" /* inside carveo
ut memory region */ |
| 126 |
| 127 /* make sure the following 2 defines have the same values (_STR is the string of
TEGRA_LP0_SIZE) */ |
| 128 #define TEGRA_LP0_SIZE 0x2000 /* 8KB */ |
| 129 #define TEGRA_LP0_SIZE_STR "0x2000" /* 8KB */ |
| 130 |
123 #define CONFIG_LOADADDR 0x40C000 | 131 #define CONFIG_LOADADDR 0x40C000 |
124 #define CONFIG_BOOTDELAY 2 /* 2s to break to prompt */ | 132 #define CONFIG_BOOTDELAY 2 /* 2s to break to prompt */ |
125 #define CONFIG_TEGRA_ENV_SETTINGS \ | 133 #define CONFIG_TEGRA_ENV_SETTINGS \ |
126 "scriptaddr=0x408000\0" \ | 134 "scriptaddr=0x408000\0" \ |
127 "script_img=/u-boot/boot.scr.uimg\0" \ | 135 "script_img=/u-boot/boot.scr.uimg\0" \ |
128 "scriptboot=fatload ${devtype} 0:c ${scriptaddr} ${script_img};" \ | 136 "scriptboot=fatload ${devtype} 0:c ${scriptaddr} ${script_img};" \ |
129 "source ${scriptaddr};" \ | 137 "source ${scriptaddr};" \ |
130 "read ${devtype} 0:${kernelpart} ${scriptaddr} 0 10;" \ | 138 "read ${devtype} 0:${kernelpart} ${scriptaddr} 0 10;" \ |
131 "source ${scriptaddr};\0" \ | 139 "source ${scriptaddr};\0" \ |
132 "mmcboot=mmc init;" \ | 140 "mmcboot=mmc init;" \ |
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159 #endif | 167 #endif |
160 | 168 |
161 /*----------------------------------------------------------------------- | 169 /*----------------------------------------------------------------------- |
162 * Physical Memory Map | 170 * Physical Memory Map |
163 */ | 171 */ |
164 #define CONFIG_NR_DRAM_BANKS 1 | 172 #define CONFIG_NR_DRAM_BANKS 1 |
165 #define PHYS_SDRAM_1 TEGRA2_SDRC_CS0 | 173 #define PHYS_SDRAM_1 TEGRA2_SDRC_CS0 |
166 #define PHYS_SDRAM_1_SIZE SZ_512M | 174 #define PHYS_SDRAM_1_SIZE SZ_512M |
167 | 175 |
168 #endif //__configs_chromeos_tegra2_common_h__ | 176 #endif //__configs_chromeos_tegra2_common_h__ |
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