tests_lit/llvm2ice_tests/test_i1.ll - Issue 476323004: Start adding an integrated assembler.

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Issue 476323004: Start adding an integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: make fixups part of address Created 6 years, 3 months ago

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1 ; Tests various aspects of i1 related lowering.	1 ; Tests various aspects of i1 related lowering.

2	2

3 ; RUN: %llvm2ice -O2 --verbose none %s \	3 ; RUN: %llvm2ice -O2 --verbose none %s \

4 ; RUN: \| llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \	4 ; RUN: \| llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \

5 ; RUN: \| llvm-objdump -d --symbolize -x86-asm-syntax=intel - \| FileCheck %s	5 ; RUN: \| llvm-objdump -d --symbolize -x86-asm-syntax=intel - \| FileCheck %s

6 ; RUN: %llvm2ice -Om1 --verbose none %s \	6 ; RUN: %llvm2ice -Om1 --verbose none %s \

7 ; RUN: \| llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \	7 ; RUN: \| llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \

8 ; RUN: \| llvm-objdump -d --symbolize -x86-asm-syntax=intel - \| FileCheck %s	8 ; RUN: \| llvm-objdump -d --symbolize -x86-asm-syntax=intel - \| FileCheck %s

9 ; RUN: %llvm2ice --verbose none %s \| FileCheck --check-prefix=ERRORS %s	9 ; RUN: %llvm2ice --verbose none %s \| FileCheck --check-prefix=ERRORS %s

10 ; RUN: %llvm2iceinsts %s \| %szdiff %s \| FileCheck --check-prefix=DUMP %s	10 ; RUN: %llvm2iceinsts %s \| %szdiff %s \| FileCheck --check-prefix=DUMP %s

(...skipping 100 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
111 entry:	111 entry:

112 %arg_i1 = trunc i32 %arg to i1	112 %arg_i1 = trunc i32 %arg to i1

113 %result_i16 = sext i1 %arg_i1 to i16	113 %result_i16 = sext i1 %arg_i1 to i16

114 %result = sext i16 %result_i16 to i32	114 %result = sext i16 %result_i16 to i32

115 ret i32 %result	115 ret i32 %result

116 }	116 }

117 ; CHECK-LABEL: testSextI16	117 ; CHECK-LABEL: testSextI16

118 ; match the trunc instruction	118 ; match the trunc instruction

119 ; CHECK: and {{.*}}, 1	119 ; CHECK: and {{.*}}, 1

120 ; match the sext i1 instruction	120 ; match the sext i1 instruction

121 ; CHECK: movzx [[REG:.*]],	121 ; CHECK: movzx e[[REG:.*]],

122 ; CHECK-NEXT: shl [[REG]], 15	122 ; CHECK-NEXT: shl [[REG]], 15

123 ; CHECK-NEXT: sar [[REG]], 15	123 ; CHECK-NEXT: sar [[REG]], 15

124	124

125 ; Test sext to i32.	125 ; Test sext to i32.

126 define internal i32 @testSextI32(i32 %arg) {	126 define internal i32 @testSextI32(i32 %arg) {

127 entry:	127 entry:

128 %arg_i1 = trunc i32 %arg to i1	128 %arg_i1 = trunc i32 %arg to i1

129 %result_i32 = sext i1 %arg_i1 to i32	129 %result_i32 = sext i1 %arg_i1 to i32

130 ret i32 %result_i32	130 ret i32 %result_i32

131 }	131 }

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175 }	175 }

176 ; CHECK-LABEL: testFptosiDouble	176 ; CHECK-LABEL: testFptosiDouble

177 ; CHECK: cvttsd2si	177 ; CHECK: cvttsd2si

178 ; CHECK: and {{.*}}, 1	178 ; CHECK: and {{.*}}, 1

179 ; CHECK: movzx [[REG:.*]],	179 ; CHECK: movzx [[REG:.*]],

180 ; CHECK-NEXT: shl [[REG]], 31	180 ; CHECK-NEXT: shl [[REG]], 31

181 ; CHECK-NEXT: sar [[REG]], 31	181 ; CHECK-NEXT: sar [[REG]], 31

182	182

183 ; ERRORS-NOT: ICE translation error	183 ; ERRORS-NOT: ICE translation error

184 ; DUMP-NOT: SZ	184 ; DUMP-NOT: SZ

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