Unify MachineType and RepType.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler-intrinsics.h"
 
 namespace v8 {
 namespace internal {
@@ skipping 267 matching lines @@
 
 
 static void VisitBinop(InstructionSelector* selector, Node* node,
                        InstructionCode opcode, InstructionCode reverse_opcode) {
   FlagsContinuation cont;
   VisitBinop(selector, node, opcode, reverse_opcode, &cont);
 }
 
 
 void InstructionSelector::VisitLoad(Node* node) {
-  MachineType rep = OpParameter<MachineType>(node);
+  MachineType rep = RepresentationOf(OpParameter<MachineType>(node));
   ArmOperandGenerator g(this);
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
 
-  InstructionOperand* result = rep == kMachineFloat64
+  InstructionOperand* result = rep == kRepFloat64
                                    ? g.DefineAsDoubleRegister(node)
                                    : g.DefineAsRegister(node);
 
   ArchOpcode opcode;
+  // TODO(titzer): signed/unsigned small loads
   switch (rep) {
-    case kMachineFloat64:
+    case kRepFloat64:
       opcode = kArmFloat64Load;
       break;
-    case kMachineWord8:
+    case kRepBit:  // Fall through.
+    case kRepWord8:
       opcode = kArmLoadWord8;
       break;
-    case kMachineWord16:
+    case kRepWord16:
       opcode = kArmLoadWord16;
       break;
-    case kMachineTagged:  // Fall through.
-    case kMachineWord32:
+    case kRepTagged:  // Fall through.
+    case kRepWord32:
       opcode = kArmLoadWord32;
       break;
     default:
       UNREACHABLE();
       return;
   }
 
   if (g.CanBeImmediate(index, opcode)) {
     Emit(opcode | AddressingModeField::encode(kMode_Offset_RI), result,
          g.UseRegister(base), g.UseImmediate(index));
   } else if (g.CanBeImmediate(base, opcode)) {
     Emit(opcode | AddressingModeField::encode(kMode_Offset_RI), result,
          g.UseRegister(index), g.UseImmediate(base));
   } else {
     Emit(opcode | AddressingModeField::encode(kMode_Offset_RR), result,
          g.UseRegister(base), g.UseRegister(index));
   }
 }
 
 
 void InstructionSelector::VisitStore(Node* node) {
   ArmOperandGenerator g(this);
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
   Node* value = node->InputAt(2);
 
   StoreRepresentation store_rep = OpParameter<StoreRepresentation>(node);
-  MachineType rep = store_rep.rep;
+  MachineType rep = RepresentationOf(store_rep.machine_type);
   if (store_rep.write_barrier_kind == kFullWriteBarrier) {
-    DCHECK(rep == kMachineTagged);
+    DCHECK(rep == kRepTagged);
     // TODO(dcarney): refactor RecordWrite function to take temp registers
     //                and pass them here instead of using fixed regs
     // TODO(dcarney): handle immediate indices.
     InstructionOperand* temps[] = {g.TempRegister(r5), g.TempRegister(r6)};
     Emit(kArmStoreWriteBarrier, NULL, g.UseFixed(base, r4),
          g.UseFixed(index, r5), g.UseFixed(value, r6), ARRAY_SIZE(temps),
          temps);
     return;
   }
   DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
-  InstructionOperand* val = rep == kMachineFloat64 ? g.UseDoubleRegister(value)
-                                                   : g.UseRegister(value);
+  InstructionOperand* val =
+      rep == kRepFloat64 ? g.UseDoubleRegister(value) : g.UseRegister(value);
 
   ArchOpcode opcode;
   switch (rep) {
-    case kMachineFloat64:
+    case kRepFloat64:
       opcode = kArmFloat64Store;
       break;
-    case kMachineWord8:
+    case kRepBit:  // Fall through.
+    case kRepWord8:
       opcode = kArmStoreWord8;
       break;
-    case kMachineWord16:
+    case kRepWord16:
       opcode = kArmStoreWord16;
       break;
-    case kMachineTagged:  // Fall through.
-    case kMachineWord32:
+    case kRepTagged:  // Fall through.
+    case kRepWord32:
       opcode = kArmStoreWord32;
       break;
     default:
       UNREACHABLE();
       return;
   }
 
   if (g.CanBeImmediate(index, opcode)) {
     Emit(opcode | AddressingModeField::encode(kMode_Offset_RI), NULL,
          g.UseRegister(base), g.UseImmediate(index), val);
@@ skipping 535 matching lines @@
     DCHECK(cont->IsSet());
     Emit(cont->Encode(kArmVcmpF64), g.DefineAsRegister(cont->result()),
          g.UseDoubleRegister(m.left().node()),
          g.UseDoubleRegister(m.right().node()));
   }
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8