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Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 469213002: [turbofan] Introduce WordRor machine operator. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Fix BUILD.gn Created 6 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 28 matching lines...) Expand all
39 V(Arm64Not) \ 39 V(Arm64Not) \
40 V(Arm64Not32) \ 40 V(Arm64Not32) \
41 V(Arm64Neg) \ 41 V(Arm64Neg) \
42 V(Arm64Neg32) \ 42 V(Arm64Neg32) \
43 V(Arm64Shl) \ 43 V(Arm64Shl) \
44 V(Arm64Shl32) \ 44 V(Arm64Shl32) \
45 V(Arm64Shr) \ 45 V(Arm64Shr) \
46 V(Arm64Shr32) \ 46 V(Arm64Shr32) \
47 V(Arm64Sar) \ 47 V(Arm64Sar) \
48 V(Arm64Sar32) \ 48 V(Arm64Sar32) \
49 V(Arm64Ror) \
50 V(Arm64Ror32) \
49 V(Arm64CallCodeObject) \ 51 V(Arm64CallCodeObject) \
50 V(Arm64CallJSFunction) \ 52 V(Arm64CallJSFunction) \
51 V(Arm64CallAddress) \ 53 V(Arm64CallAddress) \
52 V(Arm64Claim) \ 54 V(Arm64Claim) \
53 V(Arm64Poke) \ 55 V(Arm64Poke) \
54 V(Arm64PokePairZero) \ 56 V(Arm64PokePairZero) \
55 V(Arm64PokePair) \ 57 V(Arm64PokePair) \
56 V(Arm64Drop) \ 58 V(Arm64Drop) \
57 V(Arm64Float64Cmp) \ 59 V(Arm64Float64Cmp) \
58 V(Arm64Float64Add) \ 60 V(Arm64Float64Add) \
(...skipping 35 matching lines...) Expand 10 before | Expand all | Expand 10 after
94 // MRR = [register + register] 96 // MRR = [register + register]
95 #define TARGET_ADDRESSING_MODE_LIST(V) \ 97 #define TARGET_ADDRESSING_MODE_LIST(V) \
96 V(MRI) /* [%r0 + K] */ \ 98 V(MRI) /* [%r0 + K] */ \
97 V(MRR) /* [%r0 + %r1] */ 99 V(MRR) /* [%r0 + %r1] */
98 100
99 } // namespace internal 101 } // namespace internal
100 } // namespace compiler 102 } // namespace compiler
101 } // namespace v8 103 } // namespace v8
102 104
103 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 105 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
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