OLD | NEW |
1 # Copyright 2013 the V8 project authors. All rights reserved. | 1 # Copyright 2013 the V8 project authors. All rights reserved. |
2 # Redistribution and use in source and binary forms, with or without | 2 # Redistribution and use in source and binary forms, with or without |
3 # modification, are permitted provided that the following conditions are | 3 # modification, are permitted provided that the following conditions are |
4 # met: | 4 # met: |
5 # | 5 # |
6 # * Redistributions of source code must retain the above copyright | 6 # * Redistributions of source code must retain the above copyright |
7 # notice, this list of conditions and the following disclaimer. | 7 # notice, this list of conditions and the following disclaimer. |
8 # * Redistributions in binary form must reproduce the above | 8 # * Redistributions in binary form must reproduce the above |
9 # copyright notice, this list of conditions and the following | 9 # copyright notice, this list of conditions and the following |
10 # disclaimer in the documentation and/or other materials provided | 10 # disclaimer in the documentation and/or other materials provided |
(...skipping 40 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
51 | 51 |
52 # Similar to vfp but on MIPS. | 52 # Similar to vfp but on MIPS. |
53 'v8_can_use_fpu_instructions%': 'true', | 53 'v8_can_use_fpu_instructions%': 'true', |
54 | 54 |
55 # Similar to the ARM hard float ABI but on MIPS. | 55 # Similar to the ARM hard float ABI but on MIPS. |
56 'v8_use_mips_abi_hardfloat%': 'true', | 56 'v8_use_mips_abi_hardfloat%': 'true', |
57 | 57 |
58 # Default arch variant for MIPS. | 58 # Default arch variant for MIPS. |
59 'mips_arch_variant%': 'r2', | 59 'mips_arch_variant%': 'r2', |
60 | 60 |
| 61 # Possible values fp32, fp64, fpxx. |
| 62 # fp32 - 32 32-bit FPU registers are available, doubles are placed in |
| 63 # register pairs. |
| 64 # fp64 - 32 64-bit FPU registers are available. |
| 65 # fpxx - compatibility mode, it chooses fp32 or fp64 depending on runtime |
| 66 # detection |
| 67 'mips_fpu_mode%': 'fp32', |
| 68 |
61 'v8_enable_backtrace%': 0, | 69 'v8_enable_backtrace%': 0, |
62 | 70 |
63 # Enable profiling support. Only required on Windows. | 71 # Enable profiling support. Only required on Windows. |
64 'v8_enable_prof%': 0, | 72 'v8_enable_prof%': 0, |
65 | 73 |
66 # Some versions of GCC 4.5 seem to need -fno-strict-aliasing. | 74 # Some versions of GCC 4.5 seem to need -fno-strict-aliasing. |
67 'v8_no_strict_aliasing%': 0, | 75 'v8_no_strict_aliasing%': 0, |
68 | 76 |
69 # Chrome needs this definition unconditionally. For standalone V8 builds, | 77 # Chrome needs this definition unconditionally. For standalone V8 builds, |
70 # it's handled in build/standalone.gypi. | 78 # it's handled in build/standalone.gypi. |
(...skipping 194 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
265 'cflags': ['-EB'], | 273 'cflags': ['-EB'], |
266 'ldflags': ['-EB'], | 274 'ldflags': ['-EB'], |
267 'conditions': [ | 275 'conditions': [ |
268 [ 'v8_use_mips_abi_hardfloat=="true"', { | 276 [ 'v8_use_mips_abi_hardfloat=="true"', { |
269 'cflags': ['-mhard-float'], | 277 'cflags': ['-mhard-float'], |
270 'ldflags': ['-mhard-float'], | 278 'ldflags': ['-mhard-float'], |
271 }, { | 279 }, { |
272 'cflags': ['-msoft-float'], | 280 'cflags': ['-msoft-float'], |
273 'ldflags': ['-msoft-float'], | 281 'ldflags': ['-msoft-float'], |
274 }], | 282 }], |
| 283 ['mips_fpu_mode=="fp64"', { |
| 284 'cflags': ['-mfp64'], |
| 285 }], |
| 286 ['mips_fpu_mode=="fpxx"', { |
| 287 'cflags': ['-mfpxx'], |
| 288 }], |
| 289 ['mips_fpu_mode=="fp32"', { |
| 290 'cflags': ['-mfp32'], |
| 291 }], |
| 292 ['mips_arch_variant=="r6"', { |
| 293 'cflags!': ['-mfp32'], |
| 294 'cflags': ['-mips32r6', '-Wa,-mips32r6'], |
| 295 'ldflags': [ |
| 296 '-mips32r6', |
| 297 '-Wl,--dynamic-linker=$(LDSO_PATH)', |
| 298 '-Wl,--rpath=$(LD_R_PATH)', |
| 299 ], |
| 300 }], |
275 ['mips_arch_variant=="r2"', { | 301 ['mips_arch_variant=="r2"', { |
276 'cflags': ['-mips32r2', '-Wa,-mips32r2'], | 302 'cflags': ['-mips32r2', '-Wa,-mips32r2'], |
277 }], | 303 }], |
278 ['mips_arch_variant=="r1"', { | 304 ['mips_arch_variant=="r1"', { |
| 305 'cflags!': ['-mfp64'], |
| 306 'cflags': ['-mips32', '-Wa,-mips32'], |
| 307 }], |
| 308 ['mips_arch_variant=="rx"', { |
| 309 'cflags!': ['-mfp64'], |
279 'cflags': ['-mips32', '-Wa,-mips32'], | 310 'cflags': ['-mips32', '-Wa,-mips32'], |
280 }], | 311 }], |
281 ], | 312 ], |
282 }], | 313 }], |
283 ], | 314 ], |
284 }], | 315 }], |
285 [ 'v8_can_use_fpu_instructions=="true"', { | 316 [ 'v8_can_use_fpu_instructions=="true"', { |
286 'defines': [ | 317 'defines': [ |
287 'CAN_USE_FPU_INSTRUCTIONS', | 318 'CAN_USE_FPU_INSTRUCTIONS', |
288 ], | 319 ], |
289 }], | 320 }], |
290 [ 'v8_use_mips_abi_hardfloat=="true"', { | 321 [ 'v8_use_mips_abi_hardfloat=="true"', { |
291 'defines': [ | 322 'defines': [ |
292 '__mips_hard_float=1', | 323 '__mips_hard_float=1', |
293 'CAN_USE_FPU_INSTRUCTIONS', | 324 'CAN_USE_FPU_INSTRUCTIONS', |
294 ], | 325 ], |
295 }, { | 326 }, { |
296 'defines': [ | 327 'defines': [ |
297 '__mips_soft_float=1' | 328 '__mips_soft_float=1' |
298 ], | 329 ], |
299 }], | 330 }], |
| 331 ['mips_arch_variant=="rx"', { |
| 332 'defines': [ |
| 333 '_MIPS_ARCH_MIPS32RX', |
| 334 'FPU_MODE_FPXX', |
| 335 ], |
| 336 }], |
| 337 ['mips_arch_variant=="r6"', { |
| 338 'defines': [ |
| 339 '_MIPS_ARCH_MIPS32R6', |
| 340 'FPU_MODE_FP64', |
| 341 ], |
| 342 }], |
300 ['mips_arch_variant=="r2"', { | 343 ['mips_arch_variant=="r2"', { |
301 'defines': ['_MIPS_ARCH_MIPS32R2',], | 344 'defines': ['_MIPS_ARCH_MIPS32R2',], |
| 345 'conditions': [ |
| 346 ['mips_fpu_mode=="fp64"', { |
| 347 'defines': ['FPU_MODE_FP64',], |
| 348 }], |
| 349 ['mips_fpu_mode=="fpxx"', { |
| 350 'defines': ['FPU_MODE_FPXX',], |
| 351 }], |
| 352 ['mips_fpu_mode=="fp32"', { |
| 353 'defines': ['FPU_MODE_FP32',], |
| 354 }], |
| 355 ], |
| 356 }], |
| 357 ['mips_arch_variant=="r1"', { |
| 358 'defines': ['FPU_MODE_FP32',], |
302 }], | 359 }], |
303 ], | 360 ], |
304 }], # v8_target_arch=="mips" | 361 }], # v8_target_arch=="mips" |
305 ['v8_target_arch=="mipsel"', { | 362 ['v8_target_arch=="mipsel"', { |
306 'defines': [ | 363 'defines': [ |
307 'V8_TARGET_ARCH_MIPS', | 364 'V8_TARGET_ARCH_MIPS', |
308 ], | 365 ], |
309 'conditions': [ | 366 'conditions': [ |
310 ['v8_target_arch==target_arch and android_webview_build==0', { | 367 ['v8_target_arch==target_arch and android_webview_build==0', { |
311 # Target built with a Mips CXX compiler. | 368 # Target built with a Mips CXX compiler. |
312 'target_conditions': [ | 369 'target_conditions': [ |
313 ['_toolset=="target"', { | 370 ['_toolset=="target"', { |
314 'cflags': ['-EL'], | 371 'cflags': ['-EL'], |
315 'ldflags': ['-EL'], | 372 'ldflags': ['-EL'], |
316 'conditions': [ | 373 'conditions': [ |
317 [ 'v8_use_mips_abi_hardfloat=="true"', { | 374 [ 'v8_use_mips_abi_hardfloat=="true"', { |
318 'cflags': ['-mhard-float'], | 375 'cflags': ['-mhard-float'], |
319 'ldflags': ['-mhard-float'], | 376 'ldflags': ['-mhard-float'], |
320 }, { | 377 }, { |
321 'cflags': ['-msoft-float'], | 378 'cflags': ['-msoft-float'], |
322 'ldflags': ['-msoft-float'], | 379 'ldflags': ['-msoft-float'], |
323 }], | 380 }], |
| 381 ['mips_fpu_mode=="fp64"', { |
| 382 'cflags': ['-mfp64'], |
| 383 }], |
| 384 ['mips_fpu_mode=="fpxx"', { |
| 385 'cflags': ['-mfpxx'], |
| 386 }], |
| 387 ['mips_fpu_mode=="fp32"', { |
| 388 'cflags': ['-mfp32'], |
| 389 }], |
| 390 ['mips_arch_variant=="r6"', { |
| 391 'cflags!': ['-mfp32'], |
| 392 'cflags': ['-mips32r6', '-Wa,-mips32r6'], |
| 393 'ldflags': [ |
| 394 '-mips32r6', |
| 395 '-Wl,--dynamic-linker=$(LDSO_PATH)', |
| 396 '-Wl,--rpath=$(LD_R_PATH)', |
| 397 ], |
| 398 }], |
324 ['mips_arch_variant=="r2"', { | 399 ['mips_arch_variant=="r2"', { |
325 'cflags': ['-mips32r2', '-Wa,-mips32r2'], | 400 'cflags': ['-mips32r2', '-Wa,-mips32r2'], |
326 }], | 401 }], |
327 ['mips_arch_variant=="r1"', { | 402 ['mips_arch_variant=="r1"', { |
| 403 'cflags!': ['-mfp64'], |
328 'cflags': ['-mips32', '-Wa,-mips32'], | 404 'cflags': ['-mips32', '-Wa,-mips32'], |
329 }], | 405 }], |
| 406 ['mips_arch_variant=="rx"', { |
| 407 'cflags!': ['-mfp64'], |
| 408 'cflags': ['-mips32', '-Wa,-mips32'], |
| 409 }], |
330 ['mips_arch_variant=="loongson"', { | 410 ['mips_arch_variant=="loongson"', { |
| 411 'cflags!': ['-mfp64'], |
331 'cflags': ['-mips3', '-Wa,-mips3'], | 412 'cflags': ['-mips3', '-Wa,-mips3'], |
332 }], | 413 }], |
333 ], | 414 ], |
334 }], | 415 }], |
335 ], | 416 ], |
336 }], | 417 }], |
337 [ 'v8_can_use_fpu_instructions=="true"', { | 418 [ 'v8_can_use_fpu_instructions=="true"', { |
338 'defines': [ | 419 'defines': [ |
339 'CAN_USE_FPU_INSTRUCTIONS', | 420 'CAN_USE_FPU_INSTRUCTIONS', |
340 ], | 421 ], |
341 }], | 422 }], |
342 [ 'v8_use_mips_abi_hardfloat=="true"', { | 423 [ 'v8_use_mips_abi_hardfloat=="true"', { |
343 'defines': [ | 424 'defines': [ |
344 '__mips_hard_float=1', | 425 '__mips_hard_float=1', |
345 'CAN_USE_FPU_INSTRUCTIONS', | 426 'CAN_USE_FPU_INSTRUCTIONS', |
346 ], | 427 ], |
347 }, { | 428 }, { |
348 'defines': [ | 429 'defines': [ |
349 '__mips_soft_float=1' | 430 '__mips_soft_float=1' |
350 ], | 431 ], |
351 }], | 432 }], |
| 433 ['mips_arch_variant=="rx"', { |
| 434 'defines': [ |
| 435 '_MIPS_ARCH_MIPS32RX', |
| 436 'FPU_MODE_FPXX', |
| 437 ], |
| 438 }], |
| 439 ['mips_arch_variant=="r6"', { |
| 440 'defines': [ |
| 441 '_MIPS_ARCH_MIPS32R6', |
| 442 'FPU_MODE_FP64', |
| 443 ], |
| 444 }], |
352 ['mips_arch_variant=="r2"', { | 445 ['mips_arch_variant=="r2"', { |
353 'defines': ['_MIPS_ARCH_MIPS32R2',], | 446 'defines': ['_MIPS_ARCH_MIPS32R2',], |
| 447 'conditions': [ |
| 448 ['mips_fpu_mode=="fp64"', { |
| 449 'defines': ['FPU_MODE_FP64',], |
| 450 }], |
| 451 ['mips_fpu_mode=="fpxx"', { |
| 452 'defines': ['FPU_MODE_FPXX',], |
| 453 }], |
| 454 ['mips_fpu_mode=="fp32"', { |
| 455 'defines': ['FPU_MODE_FP32',], |
| 456 }], |
| 457 ], |
| 458 }], |
| 459 ['mips_arch_variant=="r1"', { |
| 460 'defines': ['FPU_MODE_FP32',], |
354 }], | 461 }], |
355 ['mips_arch_variant=="loongson"', { | 462 ['mips_arch_variant=="loongson"', { |
356 'defines': ['_MIPS_ARCH_LOONGSON',], | 463 'defines': [ |
| 464 '_MIPS_ARCH_LOONGSON', |
| 465 'FPU_MODE_FP32', |
| 466 ], |
357 }], | 467 }], |
358 ], | 468 ], |
359 }], # v8_target_arch=="mipsel" | 469 }], # v8_target_arch=="mipsel" |
360 ['v8_target_arch=="mips64el"', { | 470 ['v8_target_arch=="mips64el"', { |
361 'defines': [ | 471 'defines': [ |
362 'V8_TARGET_ARCH_MIPS64', | 472 'V8_TARGET_ARCH_MIPS64', |
363 ], | 473 ], |
364 'conditions': [ | 474 'conditions': [ |
365 ['v8_target_arch==target_arch and android_webview_build==0', { | 475 ['v8_target_arch==target_arch and android_webview_build==0', { |
366 # Target built with a Mips CXX compiler. | 476 # Target built with a Mips CXX compiler. |
(...skipping 474 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
841 'OptimizeReferences': '2', | 951 'OptimizeReferences': '2', |
842 'EnableCOMDATFolding': '2', | 952 'EnableCOMDATFolding': '2', |
843 }, | 953 }, |
844 }, | 954 }, |
845 }], # OS=="win" | 955 }], # OS=="win" |
846 ], # conditions | 956 ], # conditions |
847 }, # Release | 957 }, # Release |
848 }, # configurations | 958 }, # configurations |
849 }, # target_defaults | 959 }, # target_defaults |
850 } | 960 } |
OLD | NEW |