Subzero: Align spill locations to natural alignment.

src/IceTargetLoweringX8632.h

 //===- subzero/src/IceTargetLoweringX8632.h - x86-32 lowering ---*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the TargetLoweringX8632 class, which
@@ skipping 22 matching lines @@
   virtual IceString getRegName(SizeT RegNum, Type Ty) const;
   virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include,
                                               RegSetMask Exclude) const;
   virtual const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const {
     return TypeToRegisterSet[Ty];
   }
   virtual bool hasFramePointer() const { return IsEbpBasedFrame; }
   virtual SizeT getFrameOrStackReg() const {
     return IsEbpBasedFrame ? Reg_ebp : Reg_esp;
   }
-  virtual size_t typeWidthInBytesOnStack(Type Ty) {
+  virtual size_t typeWidthInBytesOnStack(Type Ty) const {
     // Round up to the next multiple of 4 bytes.  In particular, i1,
     // i8, and i16 are rounded up to 4 bytes.
     return (typeWidthInBytes(Ty) + 3) & ~3;
   }
   virtual void emitVariable(const Variable *Var, const Cfg *Func) const;
   virtual void lowerArguments();
   virtual void addProlog(CfgNode *Node);
   virtual void addEpilog(CfgNode *Node);
   virtual void emitConstants() const;
   SizeT makeNextLabelNumber() { return NextLabelNumber++; }
@@ skipping 64 matching lines @@
 
   typedef void (TargetX8632::*LowerBinOp)(Variable *, Operand *);
   void expandAtomicRMWAsCmpxchg(LowerBinOp op_lo, LowerBinOp op_hi,
                                 Variable *Dest, Operand *Ptr, Operand *Val);
 
   void eliminateNextVectorSextInstruction(Variable *SignExtendedResult);
 
   void scalarizeArithmetic(InstArithmetic::OpKind K, Variable *Dest,
                            Operand *Src0, Operand *Src1);
 
+  void sortByAlignment(VarList &Dest, const VarList &Source) const;
+
   // Operand legalization helpers.  To deal with address mode
   // constraints, the helpers will create a new Operand and emit
   // instructions that guarantee that the Operand kind is one of those
   // indicated by the LegalMask (a bitmask of allowed kinds).  If the
   // input Operand is known to already meet the constraints, it may be
   // simply returned as the result, without creating any new
   // instructions or operands.
   enum OperandLegalization {
     Legal_None = 0,
     Legal_Reg = 1 << 0, // physical register, not stack location
@@ skipping 313 matching lines @@
         InstFakeDef::create(Func, Src, llvm::dyn_cast<Variable>(Dest)));
   }
   void _xor(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Xor::create(Func, Dest, Src0));
   }
 
   const X86InstructionSet InstructionSet;
   bool IsEbpBasedFrame;
   bool NeedsStackAlignment;
   size_t FrameSizeLocals;
-  size_t LocalsSizeBytes;
+  size_t SpillAreaSizeBytes;
   llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
   llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   SizeT NextLabelNumber;
   bool ComputedLiveRanges;
   VarList PhysicalRegisters;
   static IceString RegNames[];
 
 private:
   TargetX8632(const TargetX8632 &) LLVM_DELETED_FUNCTION;
@@ skipping 21 matching lines @@
   virtual ~TargetGlobalInitX8632() {}
 };
 
 template <> void ConstantInteger::emit(GlobalContext *Ctx) const;
 template <> void ConstantFloat::emit(GlobalContext *Ctx) const;
 template <> void ConstantDouble::emit(GlobalContext *Ctx) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632_H