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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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96 extern Register r7; | 96 extern Register r7; |
97 extern Register r8; | 97 extern Register r8; |
98 extern Register r9; | 98 extern Register r9; |
99 extern Register r10; | 99 extern Register r10; |
100 extern Register fp; | 100 extern Register fp; |
101 extern Register ip; | 101 extern Register ip; |
102 extern Register sp; | 102 extern Register sp; |
103 extern Register lr; | 103 extern Register lr; |
104 extern Register pc; | 104 extern Register pc; |
105 | 105 |
106 // Support for VFP registers s0 to s32 (d0 to d16). | |
107 // Note that "sN:sM" is the same as "dN/2". | |
108 extern Register s0; | |
109 extern Register s1; | |
110 extern Register s2; | |
111 extern Register s3; | |
112 extern Register s4; | |
113 extern Register s5; | |
114 extern Register s6; | |
115 extern Register s7; | |
116 extern Register s8; | |
117 extern Register s9; | |
118 extern Register s10; | |
119 extern Register s11; | |
120 extern Register s12; | |
121 extern Register s13; | |
122 extern Register s14; | |
123 extern Register s15; | |
124 extern Register s16; | |
125 extern Register s17; | |
126 extern Register s18; | |
127 extern Register s19; | |
128 extern Register s20; | |
129 extern Register s21; | |
130 extern Register s22; | |
131 extern Register s23; | |
132 extern Register s24; | |
133 extern Register s25; | |
134 extern Register s26; | |
135 extern Register s27; | |
136 extern Register s28; | |
137 extern Register s29; | |
138 extern Register s30; | |
139 extern Register s31; | |
140 | 106 |
141 extern Register d0; | 107 // Single word VFP register. |
142 extern Register d1; | 108 struct SwVfpRegister { |
143 extern Register d2; | 109 bool is_valid() const { return 0 <= code_ && code_ < 32; } |
144 extern Register d3; | 110 bool is(SwVfpRegister reg) const { return code_ == reg.code_; } |
145 extern Register d4; | 111 int code() const { |
146 extern Register d5; | 112 ASSERT(is_valid()); |
147 extern Register d6; | 113 return code_; |
148 extern Register d7; | 114 } |
149 extern Register d8; | 115 int bit() const { |
150 extern Register d9; | 116 ASSERT(is_valid()); |
151 extern Register d10; | 117 return 1 << code_; |
152 extern Register d11; | 118 } |
153 extern Register d12; | 119 |
154 extern Register d13; | 120 int code_; |
155 extern Register d14; | 121 }; |
156 extern Register d15; | 122 |
| 123 |
| 124 // Double word VFP register. |
| 125 struct DwVfpRegister { |
| 126 // Supporting d0 to d15, can be later extended to d31. |
| 127 bool is_valid() const { return 0 <= code_ && code_ < 16; } |
| 128 bool is(DwVfpRegister reg) const { return code_ == reg.code_; } |
| 129 int code() const { |
| 130 ASSERT(is_valid()); |
| 131 return code_; |
| 132 } |
| 133 int bit() const { |
| 134 ASSERT(is_valid()); |
| 135 return 1 << code_; |
| 136 } |
| 137 |
| 138 int code_; |
| 139 }; |
| 140 |
| 141 |
| 142 // Support for VFP registers s0 to s31 (d0 to d15). |
| 143 // Note that "s(N):s(N+1)" is the same as "d(N/2)". |
| 144 extern SwVfpRegister s0; |
| 145 extern SwVfpRegister s1; |
| 146 extern SwVfpRegister s2; |
| 147 extern SwVfpRegister s3; |
| 148 extern SwVfpRegister s4; |
| 149 extern SwVfpRegister s5; |
| 150 extern SwVfpRegister s6; |
| 151 extern SwVfpRegister s7; |
| 152 extern SwVfpRegister s8; |
| 153 extern SwVfpRegister s9; |
| 154 extern SwVfpRegister s10; |
| 155 extern SwVfpRegister s11; |
| 156 extern SwVfpRegister s12; |
| 157 extern SwVfpRegister s13; |
| 158 extern SwVfpRegister s14; |
| 159 extern SwVfpRegister s15; |
| 160 extern SwVfpRegister s16; |
| 161 extern SwVfpRegister s17; |
| 162 extern SwVfpRegister s18; |
| 163 extern SwVfpRegister s19; |
| 164 extern SwVfpRegister s20; |
| 165 extern SwVfpRegister s21; |
| 166 extern SwVfpRegister s22; |
| 167 extern SwVfpRegister s23; |
| 168 extern SwVfpRegister s24; |
| 169 extern SwVfpRegister s25; |
| 170 extern SwVfpRegister s26; |
| 171 extern SwVfpRegister s27; |
| 172 extern SwVfpRegister s28; |
| 173 extern SwVfpRegister s29; |
| 174 extern SwVfpRegister s30; |
| 175 extern SwVfpRegister s31; |
| 176 |
| 177 extern DwVfpRegister d0; |
| 178 extern DwVfpRegister d1; |
| 179 extern DwVfpRegister d2; |
| 180 extern DwVfpRegister d3; |
| 181 extern DwVfpRegister d4; |
| 182 extern DwVfpRegister d5; |
| 183 extern DwVfpRegister d6; |
| 184 extern DwVfpRegister d7; |
| 185 extern DwVfpRegister d8; |
| 186 extern DwVfpRegister d9; |
| 187 extern DwVfpRegister d10; |
| 188 extern DwVfpRegister d11; |
| 189 extern DwVfpRegister d12; |
| 190 extern DwVfpRegister d13; |
| 191 extern DwVfpRegister d14; |
| 192 extern DwVfpRegister d15; |
| 193 |
157 | 194 |
158 // Coprocessor register | 195 // Coprocessor register |
159 struct CRegister { | 196 struct CRegister { |
160 bool is_valid() const { return 0 <= code_ && code_ < 16; } | 197 bool is_valid() const { return 0 <= code_ && code_ < 16; } |
161 bool is(CRegister creg) const { return code_ == creg.code_; } | 198 bool is(CRegister creg) const { return code_ == creg.code_; } |
162 int code() const { | 199 int code() const { |
163 ASSERT(is_valid()); | 200 ASSERT(is_valid()); |
164 return code_; | 201 return code_; |
165 } | 202 } |
166 int bit() const { | 203 int bit() const { |
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752 LFlag l = Short); // v5 and above | 789 LFlag l = Short); // v5 and above |
753 void stc2(Coprocessor coproc, CRegister crd, Register base, int option, | 790 void stc2(Coprocessor coproc, CRegister crd, Register base, int option, |
754 LFlag l = Short); // v5 and above | 791 LFlag l = Short); // v5 and above |
755 | 792 |
756 // Support for VFP. | 793 // Support for VFP. |
757 // All these APIs support S0 to S31 and D0 to D15. | 794 // All these APIs support S0 to S31 and D0 to D15. |
758 // Currently these APIs do not support extended D registers, i.e, D16 to D31. | 795 // Currently these APIs do not support extended D registers, i.e, D16 to D31. |
759 // However, some simple modifications can allow | 796 // However, some simple modifications can allow |
760 // these APIs to support D16 to D31. | 797 // these APIs to support D16 to D31. |
761 | 798 |
762 void fmdrr(const Register dst, | 799 void vmov(const DwVfpRegister dst, |
763 const Register src1, | 800 const Register src1, |
764 const Register src2, | 801 const Register src2, |
765 const SBit s = LeaveCC, | 802 const Condition cond = al); |
766 const Condition cond = al); | 803 void vmov(const Register dst1, |
767 void fmrrd(const Register dst1, | 804 const Register dst2, |
768 const Register dst2, | 805 const DwVfpRegister src, |
769 const Register src, | 806 const Condition cond = al); |
770 const SBit s = LeaveCC, | 807 void vmov(const SwVfpRegister dst, |
771 const Condition cond = al); | |
772 void fmsr(const Register dst, | |
773 const Register src, | 808 const Register src, |
774 const SBit s = LeaveCC, | |
775 const Condition cond = al); | 809 const Condition cond = al); |
776 void fmrs(const Register dst, | 810 void vmov(const Register dst, |
777 const Register src, | 811 const SwVfpRegister src, |
778 const SBit s = LeaveCC, | |
779 const Condition cond = al); | 812 const Condition cond = al); |
780 void fsitod(const Register dst, | 813 void vcvt(const DwVfpRegister dst, |
781 const Register src, | 814 const SwVfpRegister src, |
782 const SBit s = LeaveCC, | 815 const Condition cond = al); |
783 const Condition cond = al); | 816 void vcvt(const SwVfpRegister dst, |
784 void ftosid(const Register dst, | 817 const DwVfpRegister src, |
785 const Register src, | 818 const Condition cond = al); |
786 const SBit s = LeaveCC, | |
787 const Condition cond = al); | |
788 | 819 |
789 void faddd(const Register dst, | 820 void vadd(const DwVfpRegister dst, |
790 const Register src1, | 821 const DwVfpRegister src1, |
791 const Register src2, | 822 const DwVfpRegister src2, |
792 const SBit s = LeaveCC, | 823 const Condition cond = al); |
793 const Condition cond = al); | 824 void vsub(const DwVfpRegister dst, |
794 void fsubd(const Register dst, | 825 const DwVfpRegister src1, |
795 const Register src1, | 826 const DwVfpRegister src2, |
796 const Register src2, | 827 const Condition cond = al); |
797 const SBit s = LeaveCC, | 828 void vmul(const DwVfpRegister dst, |
798 const Condition cond = al); | 829 const DwVfpRegister src1, |
799 void fmuld(const Register dst, | 830 const DwVfpRegister src2, |
800 const Register src1, | 831 const Condition cond = al); |
801 const Register src2, | 832 void vdiv(const DwVfpRegister dst, |
802 const SBit s = LeaveCC, | 833 const DwVfpRegister src1, |
803 const Condition cond = al); | 834 const DwVfpRegister src2, |
804 void fdivd(const Register dst, | 835 const Condition cond = al); |
805 const Register src1, | 836 void vcmp(const DwVfpRegister src1, |
806 const Register src2, | 837 const DwVfpRegister src2, |
807 const SBit s = LeaveCC, | |
808 const Condition cond = al); | |
809 void fcmp(const Register src1, | |
810 const Register src2, | |
811 const SBit s = LeaveCC, | 838 const SBit s = LeaveCC, |
812 const Condition cond = al); | 839 const Condition cond = al); |
813 void vmrs(const Register dst, | 840 void vmrs(const Register dst, |
814 const Condition cond = al); | 841 const Condition cond = al); |
815 | 842 |
816 // Pseudo instructions | 843 // Pseudo instructions |
817 void nop() { mov(r0, Operand(r0)); } | 844 void nop() { mov(r0, Operand(r0)); } |
818 | 845 |
819 void push(Register src, Condition cond = al) { | 846 void push(Register src, Condition cond = al) { |
820 str(src, MemOperand(sp, 4, NegPreIndex), cond); | 847 str(src, MemOperand(sp, 4, NegPreIndex), cond); |
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991 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); | 1018 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); |
992 | 1019 |
993 friend class RegExpMacroAssemblerARM; | 1020 friend class RegExpMacroAssemblerARM; |
994 friend class RelocInfo; | 1021 friend class RelocInfo; |
995 friend class CodePatcher; | 1022 friend class CodePatcher; |
996 }; | 1023 }; |
997 | 1024 |
998 } } // namespace v8::internal | 1025 } } // namespace v8::internal |
999 | 1026 |
1000 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1027 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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