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Issue 458983003: Revert "Reland "MIPS: Add support for arch. revision 6 to mips32 port."" (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 4 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 152 matching lines...) Expand 10 before | Expand all | Expand 10 after
163 __ or_(v0, v0, t1); // 0x00001234 163 __ or_(v0, v0, t1); // 0x00001234
164 __ xor_(v0, v0, t2); // 0x1234444c 164 __ xor_(v0, v0, t2); // 0x1234444c
165 __ nor(v0, v0, t2); // 0xedcba987 165 __ nor(v0, v0, t2); // 0xedcba987
166 __ Branch(&error, ne, v0, Operand(0xedcba983)); 166 __ Branch(&error, ne, v0, Operand(0xedcba983));
167 __ nop(); 167 __ nop();
168 168
169 __ slt(v0, t7, t3); 169 __ slt(v0, t7, t3);
170 __ Branch(&error, ne, v0, Operand(0x1)); 170 __ Branch(&error, ne, v0, Operand(0x1));
171 __ nop(); 171 __ nop();
172 __ sltu(v0, t7, t3); 172 __ sltu(v0, t7, t3);
173 __ Branch(&error, ne, v0, Operand(zero_reg)); 173 __ Branch(&error, ne, v0, Operand(0x0));
174 __ nop(); 174 __ nop();
175 // End of SPECIAL class. 175 // End of SPECIAL class.
176 176
177 __ addiu(v0, zero_reg, 0x7421); // 0x00007421 177 __ addiu(v0, zero_reg, 0x7421); // 0x00007421
178 __ addiu(v0, v0, -0x1); // 0x00007420 178 __ addiu(v0, v0, -0x1); // 0x00007420
179 __ addiu(v0, v0, -0x20); // 0x00007400 179 __ addiu(v0, v0, -0x20); // 0x00007400
180 __ Branch(&error, ne, v0, Operand(0x00007400)); 180 __ Branch(&error, ne, v0, Operand(0x00007400));
181 __ nop(); 181 __ nop();
182 __ addiu(v1, t3, 0x1); // 0x80000000 182 __ addiu(v1, t3, 0x1); // 0x80000000
183 __ Branch(&error, ne, v1, Operand(0x80000000)); 183 __ Branch(&error, ne, v1, Operand(0x80000000));
184 __ nop(); 184 __ nop();
185 185
186 __ slti(v0, t1, 0x00002000); // 0x1 186 __ slti(v0, t1, 0x00002000); // 0x1
187 __ slti(v0, v0, 0xffff8000); // 0x0 187 __ slti(v0, v0, 0xffff8000); // 0x0
188 __ Branch(&error, ne, v0, Operand(zero_reg)); 188 __ Branch(&error, ne, v0, Operand(0x0));
189 __ nop(); 189 __ nop();
190 __ sltiu(v0, t1, 0x00002000); // 0x1 190 __ sltiu(v0, t1, 0x00002000); // 0x1
191 __ sltiu(v0, v0, 0x00008000); // 0x1 191 __ sltiu(v0, v0, 0x00008000); // 0x1
192 __ Branch(&error, ne, v0, Operand(0x1)); 192 __ Branch(&error, ne, v0, Operand(0x1));
193 __ nop(); 193 __ nop();
194 194
195 __ andi(v0, t1, 0xf0f0); // 0x00001030 195 __ andi(v0, t1, 0xf0f0); // 0x00001030
196 __ ori(v0, v0, 0x8a00); // 0x00009a30 196 __ ori(v0, v0, 0x8a00); // 0x00009a30
197 __ xori(v0, v0, 0x83cc); // 0x000019fc 197 __ xori(v0, v0, 0x83cc); // 0x000019fc
198 __ Branch(&error, ne, v0, Operand(0x000019fc)); 198 __ Branch(&error, ne, v0, Operand(0x000019fc));
(...skipping 87 matching lines...) Expand 10 before | Expand all | Expand 10 after
286 __ mul_d(f10, f10, f14); 286 __ mul_d(f10, f10, f14);
287 __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, e)) ); // e = d * 120 = 1.8066e16. 287 __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, e)) ); // e = d * 120 = 1.8066e16.
288 288
289 __ div_d(f12, f10, f4); 289 __ div_d(f12, f10, f4);
290 __ sdc1(f12, MemOperand(a0, OFFSET_OF(T, f)) ); // f = e / a = 120.44. 290 __ sdc1(f12, MemOperand(a0, OFFSET_OF(T, f)) ); // f = e / a = 120.44.
291 291
292 __ sqrt_d(f14, f12); 292 __ sqrt_d(f14, f12);
293 __ sdc1(f14, MemOperand(a0, OFFSET_OF(T, g)) ); 293 __ sdc1(f14, MemOperand(a0, OFFSET_OF(T, g)) );
294 // g = sqrt(f) = 10.97451593465515908537 294 // g = sqrt(f) = 10.97451593465515908537
295 295
296 if (IsMipsArchVariant(kMips32r2)) { 296 if (kArchVariant == kMips32r2) {
297 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, h)) ); 297 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, h)) );
298 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, i)) ); 298 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, i)) );
299 __ madd_d(f14, f6, f4, f6); 299 __ madd_d(f14, f6, f4, f6);
300 __ sdc1(f14, MemOperand(a0, OFFSET_OF(T, h)) ); 300 __ sdc1(f14, MemOperand(a0, OFFSET_OF(T, h)) );
301 } 301 }
302 302
303 __ jr(ra); 303 __ jr(ra);
304 __ nop(); 304 __ nop();
305 305
306 CodeDesc desc; 306 CodeDesc desc;
(...skipping 11 matching lines...) Expand all
318 t.i = 2.75; 318 t.i = 2.75;
319 Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0); 319 Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
320 USE(dummy); 320 USE(dummy);
321 CHECK_EQ(1.5e14, t.a); 321 CHECK_EQ(1.5e14, t.a);
322 CHECK_EQ(1.5e14, t.b); 322 CHECK_EQ(1.5e14, t.b);
323 CHECK_EQ(1.50275e14, t.c); 323 CHECK_EQ(1.50275e14, t.c);
324 CHECK_EQ(1.50550e14, t.d); 324 CHECK_EQ(1.50550e14, t.d);
325 CHECK_EQ(1.8066e16, t.e); 325 CHECK_EQ(1.8066e16, t.e);
326 CHECK_EQ(120.44, t.f); 326 CHECK_EQ(120.44, t.f);
327 CHECK_EQ(10.97451593465515908537, t.g); 327 CHECK_EQ(10.97451593465515908537, t.g);
328 if (IsMipsArchVariant(kMips32r2)) { 328 if (kArchVariant == kMips32r2) {
329 CHECK_EQ(6.875, t.h); 329 CHECK_EQ(6.875, t.h);
330 } 330 }
331 } 331 }
332 332
333 333
334 TEST(MIPS4) { 334 TEST(MIPS4) {
335 // Test moves between floating point and integer registers. 335 // Test moves between floating point and integer registers.
336 CcTest::InitializeVM(); 336 CcTest::InitializeVM();
337 Isolate* isolate = CcTest::i_isolate(); 337 Isolate* isolate = CcTest::i_isolate();
338 HandleScope scope(isolate); 338 HandleScope scope(isolate);
339 339
340 typedef struct { 340 typedef struct {
341 double a; 341 double a;
342 double b; 342 double b;
343 double c; 343 double c;
344 } T; 344 } T;
345 T t; 345 T t;
346 346
347 Assembler assm(isolate, NULL, 0); 347 Assembler assm(isolate, NULL, 0);
348 Label L, C; 348 Label L, C;
349 349
350 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) ); 350 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
351 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) ); 351 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
352 352
353 // Swap f4 and f6, by using four integer registers, t0-t3. 353 // Swap f4 and f6, by using four integer registers, t0-t3.
354 if (!IsFp64Mode()) { 354 __ mfc1(t0, f4);
355 __ mfc1(t0, f4); 355 __ mfc1(t1, f5);
356 __ mfc1(t1, f5); 356 __ mfc1(t2, f6);
357 __ mfc1(t2, f6); 357 __ mfc1(t3, f7);
358 __ mfc1(t3, f7);
359 358
360 __ mtc1(t0, f6); 359 __ mtc1(t0, f6);
361 __ mtc1(t1, f7); 360 __ mtc1(t1, f7);
362 __ mtc1(t2, f4); 361 __ mtc1(t2, f4);
363 __ mtc1(t3, f5); 362 __ mtc1(t3, f5);
364 } else {
365 DCHECK(!IsMipsArchVariant(kMips32r1) && !IsMipsArchVariant(kLoongson));
366 __ mfc1(t0, f4);
367 __ mfhc1(t1, f4);
368 __ mfc1(t2, f6);
369 __ mfhc1(t3, f6);
370 363
371 __ mtc1(t0, f6);
372 __ mthc1(t1, f6);
373 __ mtc1(t2, f4);
374 __ mthc1(t3, f4);
375 }
376 // Store the swapped f4 and f5 back to memory. 364 // Store the swapped f4 and f5 back to memory.
377 __ sdc1(f4, MemOperand(a0, OFFSET_OF(T, a)) ); 365 __ sdc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
378 __ sdc1(f6, MemOperand(a0, OFFSET_OF(T, c)) ); 366 __ sdc1(f6, MemOperand(a0, OFFSET_OF(T, c)) );
379 367
380 __ jr(ra); 368 __ jr(ra);
381 __ nop(); 369 __ nop();
382 370
383 CodeDesc desc; 371 CodeDesc desc;
384 assm.GetCode(&desc); 372 assm.GetCode(&desc);
385 Handle<Code> code = isolate->factory()->NewCode( 373 Handle<Code> code = isolate->factory()->NewCode(
(...skipping 173 matching lines...) Expand 10 before | Expand all | Expand 10 after
559 } T; 547 } T;
560 T t; 548 T t;
561 549
562 // Create a function that accepts &t, and loads, manipulates, and stores 550 // Create a function that accepts &t, and loads, manipulates, and stores
563 // the doubles t.a ... t.f. 551 // the doubles t.a ... t.f.
564 MacroAssembler assm(isolate, NULL, 0); 552 MacroAssembler assm(isolate, NULL, 0);
565 Label neither_is_nan, less_than, outa_here; 553 Label neither_is_nan, less_than, outa_here;
566 554
567 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) ); 555 __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
568 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) ); 556 __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
569 if (!IsMipsArchVariant(kMips32r6)) {
570 __ c(UN, D, f4, f6); 557 __ c(UN, D, f4, f6);
571 __ bc1f(&neither_is_nan); 558 __ bc1f(&neither_is_nan);
572 } else {
573 __ cmp(UN, L, f2, f4, f6);
574 __ bc1eqz(&neither_is_nan, f2);
575 }
576 __ nop(); 559 __ nop();
577 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) ); 560 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
578 __ Branch(&outa_here); 561 __ Branch(&outa_here);
579 562
580 __ bind(&neither_is_nan); 563 __ bind(&neither_is_nan);
581 564
582 if (IsMipsArchVariant(kLoongson)) { 565 if (kArchVariant == kLoongson) {
583 __ c(OLT, D, f6, f4); 566 __ c(OLT, D, f6, f4);
584 __ bc1t(&less_than); 567 __ bc1t(&less_than);
585 } else if (IsMipsArchVariant(kMips32r6)) {
586 __ cmp(OLT, L, f2, f6, f4);
587 __ bc1nez(&less_than, f2);
588 } else { 568 } else {
589 __ c(OLT, D, f6, f4, 2); 569 __ c(OLT, D, f6, f4, 2);
590 __ bc1t(&less_than, 2); 570 __ bc1t(&less_than, 2);
591 } 571 }
592
593 __ nop(); 572 __ nop();
594 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) ); 573 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
595 __ Branch(&outa_here); 574 __ Branch(&outa_here);
596 575
597 __ bind(&less_than); 576 __ bind(&less_than);
598 __ Addu(t0, zero_reg, Operand(1)); 577 __ Addu(t0, zero_reg, Operand(1));
599 __ sw(t0, MemOperand(a0, OFFSET_OF(T, result)) ); // Set true. 578 __ sw(t0, MemOperand(a0, OFFSET_OF(T, result)) ); // Set true.
600 579
601 580
602 // This test-case should have additional tests. 581 // This test-case should have additional tests.
(...skipping 127 matching lines...) Expand 10 before | Expand all | Expand 10 after
730 709
731 TEST(MIPS9) { 710 TEST(MIPS9) {
732 // Test BRANCH improvements. 711 // Test BRANCH improvements.
733 CcTest::InitializeVM(); 712 CcTest::InitializeVM();
734 Isolate* isolate = CcTest::i_isolate(); 713 Isolate* isolate = CcTest::i_isolate();
735 HandleScope scope(isolate); 714 HandleScope scope(isolate);
736 715
737 MacroAssembler assm(isolate, NULL, 0); 716 MacroAssembler assm(isolate, NULL, 0);
738 Label exit, exit2, exit3; 717 Label exit, exit2, exit3;
739 718
740 __ Branch(&exit, ge, a0, Operand(zero_reg)); 719 __ Branch(&exit, ge, a0, Operand(0x00000000));
741 __ Branch(&exit2, ge, a0, Operand(0x00001FFF)); 720 __ Branch(&exit2, ge, a0, Operand(0x00001FFF));
742 __ Branch(&exit3, ge, a0, Operand(0x0001FFFF)); 721 __ Branch(&exit3, ge, a0, Operand(0x0001FFFF));
743 722
744 __ bind(&exit); 723 __ bind(&exit);
745 __ bind(&exit2); 724 __ bind(&exit2);
746 __ bind(&exit3); 725 __ bind(&exit3);
747 __ jr(ra); 726 __ jr(ra);
748 __ nop(); 727 __ nop();
749 728
750 CodeDesc desc; 729 CodeDesc desc;
(...skipping 16 matching lines...) Expand all
767 int32_t dbl_mant; 746 int32_t dbl_mant;
768 int32_t dbl_exp; 747 int32_t dbl_exp;
769 int32_t word; 748 int32_t word;
770 int32_t b_word; 749 int32_t b_word;
771 } T; 750 } T;
772 T t; 751 T t;
773 752
774 Assembler assm(isolate, NULL, 0); 753 Assembler assm(isolate, NULL, 0);
775 Label L, C; 754 Label L, C;
776 755
777 if (!IsMipsArchVariant(kMips32r2)) return; 756 if (kArchVariant == kMips32r2) {
757 // Load all structure elements to registers.
758 __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a)));
778 759
779 // Load all structure elements to registers. 760 // Save the raw bits of the double.
780 __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a))); 761 __ mfc1(t0, f0);
762 __ mfc1(t1, f1);
763 __ sw(t0, MemOperand(a0, OFFSET_OF(T, dbl_mant)));
764 __ sw(t1, MemOperand(a0, OFFSET_OF(T, dbl_exp)));
781 765
782 // Save the raw bits of the double. 766 // Convert double in f0 to long, save hi/lo parts.
783 __ mfc1(t0, f0); 767 __ cvt_w_d(f0, f0);
784 __ mfc1(t1, f1); 768 __ mfc1(t0, f0); // f0 has a 32-bits word.
785 __ sw(t0, MemOperand(a0, OFFSET_OF(T, dbl_mant))); 769 __ sw(t0, MemOperand(a0, OFFSET_OF(T, word)));
786 __ sw(t1, MemOperand(a0, OFFSET_OF(T, dbl_exp)));
787 770
788 // Convert double in f0 to long, save hi/lo parts. 771 // Convert the b long integers to double b.
789 __ cvt_w_d(f0, f0); 772 __ lw(t0, MemOperand(a0, OFFSET_OF(T, b_word)));
790 __ mfc1(t0, f0); // f0 has a 32-bits word. 773 __ mtc1(t0, f8); // f8 has a 32-bits word.
791 __ sw(t0, MemOperand(a0, OFFSET_OF(T, word))); 774 __ cvt_d_w(f10, f8);
775 __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, b)));
792 776
793 // Convert the b long integers to double b. 777 __ jr(ra);
794 __ lw(t0, MemOperand(a0, OFFSET_OF(T, b_word))); 778 __ nop();
795 __ mtc1(t0, f8); // f8 has a 32-bits word.
796 __ cvt_d_w(f10, f8);
797 __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, b)));
798 779
799 __ jr(ra); 780 CodeDesc desc;
800 __ nop(); 781 assm.GetCode(&desc);
782 Handle<Code> code = isolate->factory()->NewCode(
783 desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
784 F3 f = FUNCTION_CAST<F3>(code->entry());
785 t.a = 2.147483646e+09; // 0x7FFFFFFE -> 0xFF80000041DFFFFF as double.
786 t.b_word = 0x0ff00ff0; // 0x0FF00FF0 -> 0x as double.
787 Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
788 USE(dummy);
801 789
802 CodeDesc desc; 790 CHECK_EQ(0x41DFFFFF, t.dbl_exp);
803 assm.GetCode(&desc); 791 CHECK_EQ(0xFF800000, t.dbl_mant);
804 Handle<Code> code = isolate->factory()->NewCode( 792 CHECK_EQ(0X7FFFFFFE, t.word);
805 desc, Code::ComputeFlags(Code::STUB), Handle<Code>()); 793 // 0x0FF00FF0 -> 2.6739096+e08
806 F3 f = FUNCTION_CAST<F3>(code->entry()); 794 CHECK_EQ(2.6739096e08, t.b);
807 t.a = 2.147483646e+09; // 0x7FFFFFFE -> 0xFF80000041DFFFFF as double. 795 }
808 t.b_word = 0x0ff00ff0; // 0x0FF00FF0 -> 0x as double.
809 Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
810 USE(dummy);
811
812 CHECK_EQ(0x41DFFFFF, t.dbl_exp);
813 CHECK_EQ(0xFF800000, t.dbl_mant);
814 CHECK_EQ(0X7FFFFFFE, t.word);
815 // 0x0FF00FF0 -> 2.6739096+e08
816 CHECK_EQ(2.6739096e08, t.b);
817 } 796 }
818 797
819 798
820 TEST(MIPS11) { 799 TEST(MIPS11) {
821 // Do not run test on MIPS32r6, as these instructions are removed.
822 if (IsMipsArchVariant(kMips32r6)) return;
823 // Test LWL, LWR, SWL and SWR instructions. 800 // Test LWL, LWR, SWL and SWR instructions.
824 CcTest::InitializeVM(); 801 CcTest::InitializeVM();
825 Isolate* isolate = CcTest::i_isolate(); 802 Isolate* isolate = CcTest::i_isolate();
826 HandleScope scope(isolate); 803 HandleScope scope(isolate);
827 804
828 typedef struct { 805 typedef struct {
829 int32_t reg_init; 806 int32_t reg_init;
830 int32_t mem_init; 807 int32_t mem_init;
831 int32_t lwl_0; 808 int32_t lwl_0;
832 int32_t lwl_1; 809 int32_t lwl_1;
(...skipping 436 matching lines...) Expand 10 before | Expand all | Expand 10 after
1269 Label target; 1246 Label target;
1270 __ beq(v0, v1, &target); 1247 __ beq(v0, v1, &target);
1271 __ nop(); 1248 __ nop();
1272 __ bne(v0, v1, &target); 1249 __ bne(v0, v1, &target);
1273 __ nop(); 1250 __ nop();
1274 __ bind(&target); 1251 __ bind(&target);
1275 __ nop(); 1252 __ nop();
1276 } 1253 }
1277 1254
1278 #undef __ 1255 #undef __
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