OLD | NEW |
1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_MIPS_CONSTANTS_H_ | 5 #ifndef V8_MIPS_CONSTANTS_H_ |
6 #define V8_MIPS_CONSTANTS_H_ | 6 #define V8_MIPS_CONSTANTS_H_ |
7 #include "src/globals.h" | 7 |
8 // UNIMPLEMENTED_ macro for MIPS. | 8 // UNIMPLEMENTED_ macro for MIPS. |
9 #ifdef DEBUG | 9 #ifdef DEBUG |
10 #define UNIMPLEMENTED_MIPS() \ | 10 #define UNIMPLEMENTED_MIPS() \ |
11 v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \ | 11 v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \ |
12 __FILE__, __LINE__, __func__) | 12 __FILE__, __LINE__, __func__) |
13 #else | 13 #else |
14 #define UNIMPLEMENTED_MIPS() | 14 #define UNIMPLEMENTED_MIPS() |
15 #endif | 15 #endif |
16 | 16 |
17 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n") | 17 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n") |
18 | 18 |
19 enum ArchVariants { | 19 enum ArchVariants { |
20 kMips32r1 = v8::internal::MIPSr1, | 20 kMips32r2, |
21 kMips32r2 = v8::internal::MIPSr2, | 21 kMips32r1, |
22 kMips32r6 = v8::internal::MIPSr6, | |
23 kLoongson | 22 kLoongson |
24 }; | 23 }; |
25 | 24 |
26 #ifdef _MIPS_ARCH_MIPS32R2 | 25 #ifdef _MIPS_ARCH_MIPS32R2 |
27 static const ArchVariants kArchVariant = kMips32r2; | 26 static const ArchVariants kArchVariant = kMips32r2; |
28 #elif _MIPS_ARCH_MIPS32R6 | |
29 static const ArchVariants kArchVariant = kMips32r6; | |
30 #elif _MIPS_ARCH_LOONGSON | 27 #elif _MIPS_ARCH_LOONGSON |
31 // The loongson flag refers to the LOONGSON architectures based on MIPS-III, | 28 // The loongson flag refers to the LOONGSON architectures based on MIPS-III, |
32 // which predates (and is a subset of) the mips32r2 and r1 architectures. | 29 // which predates (and is a subset of) the mips32r2 and r1 architectures. |
33 static const ArchVariants kArchVariant = kLoongson; | 30 static const ArchVariants kArchVariant = kLoongson; |
34 #elif _MIPS_ARCH_MIPS32RX | |
35 // This flags referred to compatibility mode that creates universal code that | |
36 // can run on any MIPS32 architecture revision. The dynamically generated code | |
37 // by v8 is specialized for the MIPS host detected in runtime probing. | |
38 static const ArchVariants kArchVariant = kMips32r1; | |
39 #else | 31 #else |
40 static const ArchVariants kArchVariant = kMips32r1; | 32 static const ArchVariants kArchVariant = kMips32r1; |
41 #endif | 33 #endif |
42 | 34 |
43 enum Endianness { | 35 enum Endianness { |
44 kLittle, | 36 kLittle, |
45 kBig | 37 kBig |
46 }; | 38 }; |
47 | 39 |
48 #if defined(V8_TARGET_LITTLE_ENDIAN) | 40 #if defined(V8_TARGET_LITTLE_ENDIAN) |
49 static const Endianness kArchEndian = kLittle; | 41 static const Endianness kArchEndian = kLittle; |
50 #elif defined(V8_TARGET_BIG_ENDIAN) | 42 #elif defined(V8_TARGET_BIG_ENDIAN) |
51 static const Endianness kArchEndian = kBig; | 43 static const Endianness kArchEndian = kBig; |
52 #else | 44 #else |
53 #error Unknown endianness | 45 #error Unknown endianness |
54 #endif | 46 #endif |
55 | 47 |
56 enum FpuMode { | |
57 kFP32, | |
58 kFP64, | |
59 kFPXX | |
60 }; | |
61 | |
62 #if defined(FPU_MODE_FP32) | |
63 static const FpuMode kFpuMode = kFP32; | |
64 #elif defined(FPU_MODE_FP64) | |
65 static const FpuMode kFpuMode = kFP64; | |
66 #elif defined(FPU_MODE_FPXX) | |
67 static const FpuMode kFpuMode = kFPXX; | |
68 #else | |
69 static const FpuMode kFpuMode = kFP32; | |
70 #endif | |
71 | |
72 #if(defined(__mips_hard_float) && __mips_hard_float != 0) | 48 #if(defined(__mips_hard_float) && __mips_hard_float != 0) |
73 // Use floating-point coprocessor instructions. This flag is raised when | 49 // Use floating-point coprocessor instructions. This flag is raised when |
74 // -mhard-float is passed to the compiler. | 50 // -mhard-float is passed to the compiler. |
75 const bool IsMipsSoftFloatABI = false; | 51 const bool IsMipsSoftFloatABI = false; |
76 #elif(defined(__mips_soft_float) && __mips_soft_float != 0) | 52 #elif(defined(__mips_soft_float) && __mips_soft_float != 0) |
77 // This flag is raised when -msoft-float is passed to the compiler. | 53 // This flag is raised when -msoft-float is passed to the compiler. |
78 // Although FPU is a base requirement for v8, soft-float ABI is used | 54 // Although FPU is a base requirement for v8, soft-float ABI is used |
79 // on soft-float systems with FPU kernel emulation. | 55 // on soft-float systems with FPU kernel emulation. |
80 const bool IsMipsSoftFloatABI = true; | 56 const bool IsMipsSoftFloatABI = true; |
81 #else | 57 #else |
82 const bool IsMipsSoftFloatABI = true; | 58 const bool IsMipsSoftFloatABI = true; |
83 #endif | 59 #endif |
84 | 60 |
85 #if defined(V8_TARGET_LITTLE_ENDIAN) | 61 #if defined(V8_TARGET_LITTLE_ENDIAN) |
86 const uint32_t kHoleNanUpper32Offset = 4; | 62 const uint32_t kHoleNanUpper32Offset = 4; |
87 const uint32_t kHoleNanLower32Offset = 0; | 63 const uint32_t kHoleNanLower32Offset = 0; |
88 #elif defined(V8_TARGET_BIG_ENDIAN) | 64 #elif defined(V8_TARGET_BIG_ENDIAN) |
89 const uint32_t kHoleNanUpper32Offset = 0; | 65 const uint32_t kHoleNanUpper32Offset = 0; |
90 const uint32_t kHoleNanLower32Offset = 4; | 66 const uint32_t kHoleNanLower32Offset = 4; |
91 #else | 67 #else |
92 #error Unknown endianness | 68 #error Unknown endianness |
93 #endif | 69 #endif |
94 | 70 |
95 #ifndef FPU_MODE_FPXX | |
96 #define IsFp64Mode() \ | |
97 (kFpuMode == kFP64) | |
98 #else | |
99 #define IsFp64Mode() \ | |
100 (CpuFeatures::IsSupported(FP64FPU)) | |
101 #endif | |
102 | |
103 #ifndef _MIPS_ARCH_MIPS32RX | |
104 #define IsMipsArchVariant(check) \ | |
105 (kArchVariant == check) | |
106 #else | |
107 #define IsMipsArchVariant(check) \ | |
108 (CpuFeatures::IsSupported(check)) | |
109 #endif | |
110 | |
111 | |
112 #define __STDC_FORMAT_MACROS | |
113 #include <inttypes.h> | |
114 | |
115 // Defines constants and accessor classes to assemble, disassemble and | 71 // Defines constants and accessor classes to assemble, disassemble and |
116 // simulate MIPS32 instructions. | 72 // simulate MIPS32 instructions. |
117 // | 73 // |
118 // See: MIPS32 Architecture For Programmers | 74 // See: MIPS32 Architecture For Programmers |
119 // Volume II: The MIPS32 Instruction Set | 75 // Volume II: The MIPS32 Instruction Set |
120 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf. | 76 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf. |
121 | 77 |
122 namespace v8 { | 78 namespace v8 { |
123 namespace internal { | 79 namespace internal { |
124 | 80 |
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136 const int kPCRegister = 34; | 92 const int kPCRegister = 34; |
137 | 93 |
138 // Number coprocessor registers. | 94 // Number coprocessor registers. |
139 const int kNumFPURegisters = 32; | 95 const int kNumFPURegisters = 32; |
140 const int kInvalidFPURegister = -1; | 96 const int kInvalidFPURegister = -1; |
141 | 97 |
142 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented. | 98 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented. |
143 const int kFCSRRegister = 31; | 99 const int kFCSRRegister = 31; |
144 const int kInvalidFPUControlRegister = -1; | 100 const int kInvalidFPUControlRegister = -1; |
145 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1; | 101 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1; |
146 const uint64_t kFPU64InvalidResult = | |
147 static_cast<uint64_t>(static_cast<uint64_t>(1) << 63) - 1; | |
148 | 102 |
149 // FCSR constants. | 103 // FCSR constants. |
150 const uint32_t kFCSRInexactFlagBit = 2; | 104 const uint32_t kFCSRInexactFlagBit = 2; |
151 const uint32_t kFCSRUnderflowFlagBit = 3; | 105 const uint32_t kFCSRUnderflowFlagBit = 3; |
152 const uint32_t kFCSROverflowFlagBit = 4; | 106 const uint32_t kFCSROverflowFlagBit = 4; |
153 const uint32_t kFCSRDivideByZeroFlagBit = 5; | 107 const uint32_t kFCSRDivideByZeroFlagBit = 5; |
154 const uint32_t kFCSRInvalidOpFlagBit = 6; | 108 const uint32_t kFCSRInvalidOpFlagBit = 6; |
155 | 109 |
156 const uint32_t kFCSRInexactFlagMask = 1 << kFCSRInexactFlagBit; | 110 const uint32_t kFCSRInexactFlagMask = 1 << kFCSRInexactFlagBit; |
157 const uint32_t kFCSRUnderflowFlagMask = 1 << kFCSRUnderflowFlagBit; | 111 const uint32_t kFCSRUnderflowFlagMask = 1 << kFCSRUnderflowFlagBit; |
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255 const int kRdShift = 11; | 209 const int kRdShift = 11; |
256 const int kRdBits = 5; | 210 const int kRdBits = 5; |
257 const int kSaShift = 6; | 211 const int kSaShift = 6; |
258 const int kSaBits = 5; | 212 const int kSaBits = 5; |
259 const int kFunctionShift = 0; | 213 const int kFunctionShift = 0; |
260 const int kFunctionBits = 6; | 214 const int kFunctionBits = 6; |
261 const int kLuiShift = 16; | 215 const int kLuiShift = 16; |
262 | 216 |
263 const int kImm16Shift = 0; | 217 const int kImm16Shift = 0; |
264 const int kImm16Bits = 16; | 218 const int kImm16Bits = 16; |
265 const int kImm21Shift = 0; | |
266 const int kImm21Bits = 21; | |
267 const int kImm26Shift = 0; | 219 const int kImm26Shift = 0; |
268 const int kImm26Bits = 26; | 220 const int kImm26Bits = 26; |
269 const int kImm28Shift = 0; | 221 const int kImm28Shift = 0; |
270 const int kImm28Bits = 28; | 222 const int kImm28Bits = 28; |
271 const int kImm32Shift = 0; | |
272 const int kImm32Bits = 32; | |
273 | 223 |
274 // In branches and jumps immediate fields point to words, not bytes, | 224 // In branches and jumps immediate fields point to words, not bytes, |
275 // and are therefore shifted by 2. | 225 // and are therefore shifted by 2. |
276 const int kImmFieldShift = 2; | 226 const int kImmFieldShift = 2; |
277 | 227 |
278 const int kFrBits = 5; | 228 const int kFrBits = 5; |
279 const int kFrShift = 21; | 229 const int kFrShift = 21; |
280 const int kFsShift = 11; | 230 const int kFsShift = 11; |
281 const int kFsBits = 5; | 231 const int kFsBits = 5; |
282 const int kFtShift = 16; | 232 const int kFtShift = 16; |
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321 BLEZ = ((0 << 3) + 6) << kOpcodeShift, | 271 BLEZ = ((0 << 3) + 6) << kOpcodeShift, |
322 BGTZ = ((0 << 3) + 7) << kOpcodeShift, | 272 BGTZ = ((0 << 3) + 7) << kOpcodeShift, |
323 | 273 |
324 ADDI = ((1 << 3) + 0) << kOpcodeShift, | 274 ADDI = ((1 << 3) + 0) << kOpcodeShift, |
325 ADDIU = ((1 << 3) + 1) << kOpcodeShift, | 275 ADDIU = ((1 << 3) + 1) << kOpcodeShift, |
326 SLTI = ((1 << 3) + 2) << kOpcodeShift, | 276 SLTI = ((1 << 3) + 2) << kOpcodeShift, |
327 SLTIU = ((1 << 3) + 3) << kOpcodeShift, | 277 SLTIU = ((1 << 3) + 3) << kOpcodeShift, |
328 ANDI = ((1 << 3) + 4) << kOpcodeShift, | 278 ANDI = ((1 << 3) + 4) << kOpcodeShift, |
329 ORI = ((1 << 3) + 5) << kOpcodeShift, | 279 ORI = ((1 << 3) + 5) << kOpcodeShift, |
330 XORI = ((1 << 3) + 6) << kOpcodeShift, | 280 XORI = ((1 << 3) + 6) << kOpcodeShift, |
331 LUI = ((1 << 3) + 7) << kOpcodeShift, // LUI/AUI family. | 281 LUI = ((1 << 3) + 7) << kOpcodeShift, |
332 | 282 |
333 BEQC = ((2 << 3) + 0) << kOpcodeShift, | |
334 COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class. | 283 COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class. |
335 BEQL = ((2 << 3) + 4) << kOpcodeShift, | 284 BEQL = ((2 << 3) + 4) << kOpcodeShift, |
336 BNEL = ((2 << 3) + 5) << kOpcodeShift, | 285 BNEL = ((2 << 3) + 5) << kOpcodeShift, |
337 BLEZL = ((2 << 3) + 6) << kOpcodeShift, | 286 BLEZL = ((2 << 3) + 6) << kOpcodeShift, |
338 BGTZL = ((2 << 3) + 7) << kOpcodeShift, | 287 BGTZL = ((2 << 3) + 7) << kOpcodeShift, |
339 | 288 |
340 DADDI = ((3 << 3) + 0) << kOpcodeShift, // This is also BNEC. | |
341 SPECIAL2 = ((3 << 3) + 4) << kOpcodeShift, | 289 SPECIAL2 = ((3 << 3) + 4) << kOpcodeShift, |
342 SPECIAL3 = ((3 << 3) + 7) << kOpcodeShift, | 290 SPECIAL3 = ((3 << 3) + 7) << kOpcodeShift, |
343 | 291 |
344 LB = ((4 << 3) + 0) << kOpcodeShift, | 292 LB = ((4 << 3) + 0) << kOpcodeShift, |
345 LH = ((4 << 3) + 1) << kOpcodeShift, | 293 LH = ((4 << 3) + 1) << kOpcodeShift, |
346 LWL = ((4 << 3) + 2) << kOpcodeShift, | 294 LWL = ((4 << 3) + 2) << kOpcodeShift, |
347 LW = ((4 << 3) + 3) << kOpcodeShift, | 295 LW = ((4 << 3) + 3) << kOpcodeShift, |
348 LBU = ((4 << 3) + 4) << kOpcodeShift, | 296 LBU = ((4 << 3) + 4) << kOpcodeShift, |
349 LHU = ((4 << 3) + 5) << kOpcodeShift, | 297 LHU = ((4 << 3) + 5) << kOpcodeShift, |
350 LWR = ((4 << 3) + 6) << kOpcodeShift, | 298 LWR = ((4 << 3) + 6) << kOpcodeShift, |
351 SB = ((5 << 3) + 0) << kOpcodeShift, | 299 SB = ((5 << 3) + 0) << kOpcodeShift, |
352 SH = ((5 << 3) + 1) << kOpcodeShift, | 300 SH = ((5 << 3) + 1) << kOpcodeShift, |
353 SWL = ((5 << 3) + 2) << kOpcodeShift, | 301 SWL = ((5 << 3) + 2) << kOpcodeShift, |
354 SW = ((5 << 3) + 3) << kOpcodeShift, | 302 SW = ((5 << 3) + 3) << kOpcodeShift, |
355 SWR = ((5 << 3) + 6) << kOpcodeShift, | 303 SWR = ((5 << 3) + 6) << kOpcodeShift, |
356 | 304 |
357 LWC1 = ((6 << 3) + 1) << kOpcodeShift, | 305 LWC1 = ((6 << 3) + 1) << kOpcodeShift, |
358 LDC1 = ((6 << 3) + 5) << kOpcodeShift, | 306 LDC1 = ((6 << 3) + 5) << kOpcodeShift, |
359 BEQZC = ((6 << 3) + 6) << kOpcodeShift, | |
360 | 307 |
361 PREF = ((6 << 3) + 3) << kOpcodeShift, | 308 PREF = ((6 << 3) + 3) << kOpcodeShift, |
362 | 309 |
363 SWC1 = ((7 << 3) + 1) << kOpcodeShift, | 310 SWC1 = ((7 << 3) + 1) << kOpcodeShift, |
364 SDC1 = ((7 << 3) + 5) << kOpcodeShift, | 311 SDC1 = ((7 << 3) + 5) << kOpcodeShift, |
365 BNEZC = ((7 << 3) + 6) << kOpcodeShift, | |
366 | 312 |
367 COP1X = ((1 << 4) + 3) << kOpcodeShift | 313 COP1X = ((1 << 4) + 3) << kOpcodeShift |
368 }; | 314 }; |
369 | 315 |
370 enum SecondaryField { | 316 enum SecondaryField { |
371 // SPECIAL Encoding of Function Field. | 317 // SPECIAL Encoding of Function Field. |
372 SLL = ((0 << 3) + 0), | 318 SLL = ((0 << 3) + 0), |
373 MOVCI = ((0 << 3) + 1), | 319 MOVCI = ((0 << 3) + 1), |
374 SRL = ((0 << 3) + 2), | 320 SRL = ((0 << 3) + 2), |
375 SRA = ((0 << 3) + 3), | 321 SRA = ((0 << 3) + 3), |
376 SLLV = ((0 << 3) + 4), | 322 SLLV = ((0 << 3) + 4), |
377 SRLV = ((0 << 3) + 6), | 323 SRLV = ((0 << 3) + 6), |
378 SRAV = ((0 << 3) + 7), | 324 SRAV = ((0 << 3) + 7), |
379 | 325 |
380 JR = ((1 << 3) + 0), | 326 JR = ((1 << 3) + 0), |
381 JALR = ((1 << 3) + 1), | 327 JALR = ((1 << 3) + 1), |
382 MOVZ = ((1 << 3) + 2), | 328 MOVZ = ((1 << 3) + 2), |
383 MOVN = ((1 << 3) + 3), | 329 MOVN = ((1 << 3) + 3), |
384 BREAK = ((1 << 3) + 5), | 330 BREAK = ((1 << 3) + 5), |
385 | 331 |
386 MFHI = ((2 << 3) + 0), | 332 MFHI = ((2 << 3) + 0), |
387 CLZ_R6 = ((2 << 3) + 0), | |
388 CLO_R6 = ((2 << 3) + 1), | |
389 MFLO = ((2 << 3) + 2), | 333 MFLO = ((2 << 3) + 2), |
390 | 334 |
391 MULT = ((3 << 3) + 0), | 335 MULT = ((3 << 3) + 0), |
392 MULTU = ((3 << 3) + 1), | 336 MULTU = ((3 << 3) + 1), |
393 DIV = ((3 << 3) + 2), | 337 DIV = ((3 << 3) + 2), |
394 DIVU = ((3 << 3) + 3), | 338 DIVU = ((3 << 3) + 3), |
395 | 339 |
396 ADD = ((4 << 3) + 0), | 340 ADD = ((4 << 3) + 0), |
397 ADDU = ((4 << 3) + 1), | 341 ADDU = ((4 << 3) + 1), |
398 SUB = ((4 << 3) + 2), | 342 SUB = ((4 << 3) + 2), |
399 SUBU = ((4 << 3) + 3), | 343 SUBU = ((4 << 3) + 3), |
400 AND = ((4 << 3) + 4), | 344 AND = ((4 << 3) + 4), |
401 OR = ((4 << 3) + 5), | 345 OR = ((4 << 3) + 5), |
402 XOR = ((4 << 3) + 6), | 346 XOR = ((4 << 3) + 6), |
403 NOR = ((4 << 3) + 7), | 347 NOR = ((4 << 3) + 7), |
404 | 348 |
405 SLT = ((5 << 3) + 2), | 349 SLT = ((5 << 3) + 2), |
406 SLTU = ((5 << 3) + 3), | 350 SLTU = ((5 << 3) + 3), |
407 | 351 |
408 TGE = ((6 << 3) + 0), | 352 TGE = ((6 << 3) + 0), |
409 TGEU = ((6 << 3) + 1), | 353 TGEU = ((6 << 3) + 1), |
410 TLT = ((6 << 3) + 2), | 354 TLT = ((6 << 3) + 2), |
411 TLTU = ((6 << 3) + 3), | 355 TLTU = ((6 << 3) + 3), |
412 TEQ = ((6 << 3) + 4), | 356 TEQ = ((6 << 3) + 4), |
413 SELEQZ_S = ((6 << 3) + 5), | |
414 TNE = ((6 << 3) + 6), | 357 TNE = ((6 << 3) + 6), |
415 SELNEZ_S = ((6 << 3) + 7), | |
416 | |
417 // Multiply integers in r6. | |
418 MUL_MUH = ((3 << 3) + 0), // MUL, MUH. | |
419 MUL_MUH_U = ((3 << 3) + 1), // MUL_U, MUH_U. | |
420 | |
421 MUL_OP = ((0 << 3) + 2), | |
422 MUH_OP = ((0 << 3) + 3), | |
423 DIV_OP = ((0 << 3) + 2), | |
424 MOD_OP = ((0 << 3) + 3), | |
425 | |
426 DIV_MOD = ((3 << 3) + 2), | |
427 DIV_MOD_U = ((3 << 3) + 3), | |
428 | 358 |
429 // SPECIAL2 Encoding of Function Field. | 359 // SPECIAL2 Encoding of Function Field. |
430 MUL = ((0 << 3) + 2), | 360 MUL = ((0 << 3) + 2), |
431 CLZ = ((4 << 3) + 0), | 361 CLZ = ((4 << 3) + 0), |
432 CLO = ((4 << 3) + 1), | 362 CLO = ((4 << 3) + 1), |
433 | 363 |
434 // SPECIAL3 Encoding of Function Field. | 364 // SPECIAL3 Encoding of Function Field. |
435 EXT = ((0 << 3) + 0), | 365 EXT = ((0 << 3) + 0), |
436 INS = ((0 << 3) + 4), | 366 INS = ((0 << 3) + 4), |
437 | 367 |
438 // REGIMM encoding of rt Field. | 368 // REGIMM encoding of rt Field. |
439 BLTZ = ((0 << 3) + 0) << 16, | 369 BLTZ = ((0 << 3) + 0) << 16, |
440 BGEZ = ((0 << 3) + 1) << 16, | 370 BGEZ = ((0 << 3) + 1) << 16, |
441 BLTZAL = ((2 << 3) + 0) << 16, | 371 BLTZAL = ((2 << 3) + 0) << 16, |
442 BGEZAL = ((2 << 3) + 1) << 16, | 372 BGEZAL = ((2 << 3) + 1) << 16, |
443 BGEZALL = ((2 << 3) + 3) << 16, | |
444 | 373 |
445 // COP1 Encoding of rs Field. | 374 // COP1 Encoding of rs Field. |
446 MFC1 = ((0 << 3) + 0) << 21, | 375 MFC1 = ((0 << 3) + 0) << 21, |
447 CFC1 = ((0 << 3) + 2) << 21, | 376 CFC1 = ((0 << 3) + 2) << 21, |
448 MFHC1 = ((0 << 3) + 3) << 21, | 377 MFHC1 = ((0 << 3) + 3) << 21, |
449 MTC1 = ((0 << 3) + 4) << 21, | 378 MTC1 = ((0 << 3) + 4) << 21, |
450 CTC1 = ((0 << 3) + 6) << 21, | 379 CTC1 = ((0 << 3) + 6) << 21, |
451 MTHC1 = ((0 << 3) + 7) << 21, | 380 MTHC1 = ((0 << 3) + 7) << 21, |
452 BC1 = ((1 << 3) + 0) << 21, | 381 BC1 = ((1 << 3) + 0) << 21, |
453 S = ((2 << 3) + 0) << 21, | 382 S = ((2 << 3) + 0) << 21, |
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478 MOV_D = ((0 << 3) + 6), | 407 MOV_D = ((0 << 3) + 6), |
479 NEG_D = ((0 << 3) + 7), | 408 NEG_D = ((0 << 3) + 7), |
480 ROUND_L_D = ((1 << 3) + 0), | 409 ROUND_L_D = ((1 << 3) + 0), |
481 TRUNC_L_D = ((1 << 3) + 1), | 410 TRUNC_L_D = ((1 << 3) + 1), |
482 CEIL_L_D = ((1 << 3) + 2), | 411 CEIL_L_D = ((1 << 3) + 2), |
483 FLOOR_L_D = ((1 << 3) + 3), | 412 FLOOR_L_D = ((1 << 3) + 3), |
484 ROUND_W_D = ((1 << 3) + 4), | 413 ROUND_W_D = ((1 << 3) + 4), |
485 TRUNC_W_D = ((1 << 3) + 5), | 414 TRUNC_W_D = ((1 << 3) + 5), |
486 CEIL_W_D = ((1 << 3) + 6), | 415 CEIL_W_D = ((1 << 3) + 6), |
487 FLOOR_W_D = ((1 << 3) + 7), | 416 FLOOR_W_D = ((1 << 3) + 7), |
488 MIN = ((3 << 3) + 4), | |
489 MINA = ((3 << 3) + 5), | |
490 MAX = ((3 << 3) + 6), | |
491 MAXA = ((3 << 3) + 7), | |
492 CVT_S_D = ((4 << 3) + 0), | 417 CVT_S_D = ((4 << 3) + 0), |
493 CVT_W_D = ((4 << 3) + 4), | 418 CVT_W_D = ((4 << 3) + 4), |
494 CVT_L_D = ((4 << 3) + 5), | 419 CVT_L_D = ((4 << 3) + 5), |
495 C_F_D = ((6 << 3) + 0), | 420 C_F_D = ((6 << 3) + 0), |
496 C_UN_D = ((6 << 3) + 1), | 421 C_UN_D = ((6 << 3) + 1), |
497 C_EQ_D = ((6 << 3) + 2), | 422 C_EQ_D = ((6 << 3) + 2), |
498 C_UEQ_D = ((6 << 3) + 3), | 423 C_UEQ_D = ((6 << 3) + 3), |
499 C_OLT_D = ((6 << 3) + 4), | 424 C_OLT_D = ((6 << 3) + 4), |
500 C_ULT_D = ((6 << 3) + 5), | 425 C_ULT_D = ((6 << 3) + 5), |
501 C_OLE_D = ((6 << 3) + 6), | 426 C_OLE_D = ((6 << 3) + 6), |
502 C_ULE_D = ((6 << 3) + 7), | 427 C_ULE_D = ((6 << 3) + 7), |
503 // COP1 Encoding of Function Field When rs=W or L. | 428 // COP1 Encoding of Function Field When rs=W or L. |
504 CVT_S_W = ((4 << 3) + 0), | 429 CVT_S_W = ((4 << 3) + 0), |
505 CVT_D_W = ((4 << 3) + 1), | 430 CVT_D_W = ((4 << 3) + 1), |
506 CVT_S_L = ((4 << 3) + 0), | 431 CVT_S_L = ((4 << 3) + 0), |
507 CVT_D_L = ((4 << 3) + 1), | 432 CVT_D_L = ((4 << 3) + 1), |
508 BC1EQZ = ((2 << 2) + 1) << 21, | |
509 BC1NEZ = ((3 << 2) + 1) << 21, | |
510 // COP1 CMP positive predicates Bit 5..4 = 00. | |
511 CMP_AF = ((0 << 3) + 0), | |
512 CMP_UN = ((0 << 3) + 1), | |
513 CMP_EQ = ((0 << 3) + 2), | |
514 CMP_UEQ = ((0 << 3) + 3), | |
515 CMP_LT = ((0 << 3) + 4), | |
516 CMP_ULT = ((0 << 3) + 5), | |
517 CMP_LE = ((0 << 3) + 6), | |
518 CMP_ULE = ((0 << 3) + 7), | |
519 CMP_SAF = ((1 << 3) + 0), | |
520 CMP_SUN = ((1 << 3) + 1), | |
521 CMP_SEQ = ((1 << 3) + 2), | |
522 CMP_SUEQ = ((1 << 3) + 3), | |
523 CMP_SSLT = ((1 << 3) + 4), | |
524 CMP_SSULT = ((1 << 3) + 5), | |
525 CMP_SLE = ((1 << 3) + 6), | |
526 CMP_SULE = ((1 << 3) + 7), | |
527 // COP1 CMP negative predicates Bit 5..4 = 01. | |
528 CMP_AT = ((2 << 3) + 0), // Reserved, not implemented. | |
529 CMP_OR = ((2 << 3) + 1), | |
530 CMP_UNE = ((2 << 3) + 2), | |
531 CMP_NE = ((2 << 3) + 3), | |
532 CMP_UGE = ((2 << 3) + 4), // Reserved, not implemented. | |
533 CMP_OGE = ((2 << 3) + 5), // Reserved, not implemented. | |
534 CMP_UGT = ((2 << 3) + 6), // Reserved, not implemented. | |
535 CMP_OGT = ((2 << 3) + 7), // Reserved, not implemented. | |
536 CMP_SAT = ((3 << 3) + 0), // Reserved, not implemented. | |
537 CMP_SOR = ((3 << 3) + 1), | |
538 CMP_SUNE = ((3 << 3) + 2), | |
539 CMP_SNE = ((3 << 3) + 3), | |
540 CMP_SUGE = ((3 << 3) + 4), // Reserved, not implemented. | |
541 CMP_SOGE = ((3 << 3) + 5), // Reserved, not implemented. | |
542 CMP_SUGT = ((3 << 3) + 6), // Reserved, not implemented. | |
543 CMP_SOGT = ((3 << 3) + 7), // Reserved, not implemented. | |
544 | |
545 SEL = ((2 << 3) + 0), | |
546 SELEQZ_C = ((2 << 3) + 4), // COP1 on FPR registers. | |
547 SELNEZ_C = ((2 << 3) + 7), // COP1 on FPR registers. | |
548 // COP1 Encoding of Function Field When rs=PS. | 433 // COP1 Encoding of Function Field When rs=PS. |
549 // COP1X Encoding of Function Field. | 434 // COP1X Encoding of Function Field. |
550 MADD_D = ((4 << 3) + 1), | 435 MADD_D = ((4 << 3) + 1), |
551 | 436 |
552 NULLSF = 0 | 437 NULLSF = 0 |
553 }; | 438 }; |
554 | 439 |
555 | 440 |
556 // ----- Emulated conditions. | 441 // ----- Emulated conditions. |
557 // On MIPS we use this enum to abstract from conditionnal branch instructions. | 442 // On MIPS we use this enum to abstract from conditionnal branch instructions. |
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883 default: | 768 default: |
884 return NULLSF; | 769 return NULLSF; |
885 } | 770 } |
886 } | 771 } |
887 | 772 |
888 inline int32_t Imm16Value() const { | 773 inline int32_t Imm16Value() const { |
889 DCHECK(InstructionType() == kImmediateType); | 774 DCHECK(InstructionType() == kImmediateType); |
890 return Bits(kImm16Shift + kImm16Bits - 1, kImm16Shift); | 775 return Bits(kImm16Shift + kImm16Bits - 1, kImm16Shift); |
891 } | 776 } |
892 | 777 |
893 inline int32_t Imm21Value() const { | |
894 DCHECK(InstructionType() == kImmediateType); | |
895 return Bits(kImm21Shift + kImm21Bits - 1, kImm21Shift); | |
896 } | |
897 | |
898 inline int32_t Imm26Value() const { | 778 inline int32_t Imm26Value() const { |
899 DCHECK(InstructionType() == kJumpType); | 779 DCHECK(InstructionType() == kJumpType); |
900 return Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift); | 780 return Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift); |
901 } | 781 } |
902 | 782 |
903 // Say if the instruction should not be used in a branch delay slot. | 783 // Say if the instruction should not be used in a branch delay slot. |
904 bool IsForbiddenInBranchDelay() const; | 784 bool IsForbiddenInBranchDelay() const; |
905 // Say if the instruction 'links'. e.g. jal, bal. | 785 // Say if the instruction 'links'. e.g. jal, bal. |
906 bool IsLinkingInstruction() const; | 786 bool IsLinkingInstruction() const; |
907 // Say if the instruction is a break or a trap. | 787 // Say if the instruction is a break or a trap. |
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930 // JS argument slots size. | 810 // JS argument slots size. |
931 const int kJSArgsSlotsSize = 0 * Instruction::kInstrSize; | 811 const int kJSArgsSlotsSize = 0 * Instruction::kInstrSize; |
932 // Assembly builtins argument slots size. | 812 // Assembly builtins argument slots size. |
933 const int kBArgsSlotsSize = 0 * Instruction::kInstrSize; | 813 const int kBArgsSlotsSize = 0 * Instruction::kInstrSize; |
934 | 814 |
935 const int kBranchReturnOffset = 2 * Instruction::kInstrSize; | 815 const int kBranchReturnOffset = 2 * Instruction::kInstrSize; |
936 | 816 |
937 } } // namespace v8::internal | 817 } } // namespace v8::internal |
938 | 818 |
939 #endif // #ifndef V8_MIPS_CONSTANTS_H_ | 819 #endif // #ifndef V8_MIPS_CONSTANTS_H_ |
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