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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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321 // cp is assumed to be a callee saved register. | 321 // cp is assumed to be a callee saved register. |
322 // Defined using #define instead of "static const Register&" because Clang | 322 // Defined using #define instead of "static const Register&" because Clang |
323 // complains otherwise when a compilation unit that includes this header | 323 // complains otherwise when a compilation unit that includes this header |
324 // doesn't use the variables. | 324 // doesn't use the variables. |
325 #define kRootRegister s6 | 325 #define kRootRegister s6 |
326 #define cp s7 | 326 #define cp s7 |
327 #define kLithiumScratchReg s3 | 327 #define kLithiumScratchReg s3 |
328 #define kLithiumScratchReg2 s4 | 328 #define kLithiumScratchReg2 s4 |
329 #define kLithiumScratchDouble f30 | 329 #define kLithiumScratchDouble f30 |
330 #define kDoubleRegZero f28 | 330 #define kDoubleRegZero f28 |
331 // Used on mips32r6 for compare operations. | |
332 #define kDoubleCompareReg f31 | |
333 | 331 |
334 // FPU (coprocessor 1) control registers. | 332 // FPU (coprocessor 1) control registers. |
335 // Currently only FCSR (#31) is implemented. | 333 // Currently only FCSR (#31) is implemented. |
336 struct FPUControlRegister { | 334 struct FPUControlRegister { |
337 bool is_valid() const { return code_ == kFCSRRegister; } | 335 bool is_valid() const { return code_ == kFCSRRegister; } |
338 bool is(FPUControlRegister creg) const { return code_ == creg.code_; } | 336 bool is(FPUControlRegister creg) const { return code_ == creg.code_; } |
339 int code() const { | 337 int code() const { |
340 DCHECK(is_valid()); | 338 DCHECK(is_valid()); |
341 return code_; | 339 return code_; |
342 } | 340 } |
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460 // but it may be bound only once. | 458 // but it may be bound only once. |
461 void bind(Label* L); // Binds an unbound label L to current code position. | 459 void bind(Label* L); // Binds an unbound label L to current code position. |
462 // Determines if Label is bound and near enough so that branch instruction | 460 // Determines if Label is bound and near enough so that branch instruction |
463 // can be used to reach it, instead of jump instruction. | 461 // can be used to reach it, instead of jump instruction. |
464 bool is_near(Label* L); | 462 bool is_near(Label* L); |
465 | 463 |
466 // Returns the branch offset to the given label from the current code | 464 // Returns the branch offset to the given label from the current code |
467 // position. Links the label to the current position if it is still unbound. | 465 // position. Links the label to the current position if it is still unbound. |
468 // Manages the jump elimination optimization if the second parameter is true. | 466 // Manages the jump elimination optimization if the second parameter is true. |
469 int32_t branch_offset(Label* L, bool jump_elimination_allowed); | 467 int32_t branch_offset(Label* L, bool jump_elimination_allowed); |
470 int32_t branch_offset_compact(Label* L, bool jump_elimination_allowed); | |
471 int32_t branch_offset21(Label* L, bool jump_elimination_allowed); | |
472 int32_t branch_offset21_compact(Label* L, bool jump_elimination_allowed); | |
473 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) { | 468 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) { |
474 int32_t o = branch_offset(L, jump_elimination_allowed); | 469 int32_t o = branch_offset(L, jump_elimination_allowed); |
475 DCHECK((o & 3) == 0); // Assert the offset is aligned. | 470 DCHECK((o & 3) == 0); // Assert the offset is aligned. |
476 return o >> 2; | 471 return o >> 2; |
477 } | 472 } |
478 int32_t shifted_branch_offset_compact(Label* L, | |
479 bool jump_elimination_allowed) { | |
480 int32_t o = branch_offset_compact(L, jump_elimination_allowed); | |
481 DCHECK((o & 3) == 0); // Assert the offset is aligned. | |
482 return o >> 2; | |
483 } | |
484 uint32_t jump_address(Label* L); | 473 uint32_t jump_address(Label* L); |
485 | 474 |
486 // Puts a labels target address at the given position. | 475 // Puts a labels target address at the given position. |
487 // The high 8 bits are set to zero. | 476 // The high 8 bits are set to zero. |
488 void label_at_put(Label* L, int at_offset); | 477 void label_at_put(Label* L, int at_offset); |
489 | 478 |
490 // Read/Modify the code target address in the branch/call instruction at pc. | 479 // Read/Modify the code target address in the branch/call instruction at pc. |
491 static Address target_address_at(Address pc); | 480 static Address target_address_at(Address pc); |
492 static void set_target_address_at(Address pc, | 481 static void set_target_address_at(Address pc, |
493 Address target, | 482 Address target, |
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631 void b(int16_t offset); | 620 void b(int16_t offset); |
632 void b(Label* L) { b(branch_offset(L, false)>>2); } | 621 void b(Label* L) { b(branch_offset(L, false)>>2); } |
633 void bal(int16_t offset); | 622 void bal(int16_t offset); |
634 void bal(Label* L) { bal(branch_offset(L, false)>>2); } | 623 void bal(Label* L) { bal(branch_offset(L, false)>>2); } |
635 | 624 |
636 void beq(Register rs, Register rt, int16_t offset); | 625 void beq(Register rs, Register rt, int16_t offset); |
637 void beq(Register rs, Register rt, Label* L) { | 626 void beq(Register rs, Register rt, Label* L) { |
638 beq(rs, rt, branch_offset(L, false) >> 2); | 627 beq(rs, rt, branch_offset(L, false) >> 2); |
639 } | 628 } |
640 void bgez(Register rs, int16_t offset); | 629 void bgez(Register rs, int16_t offset); |
641 void bgezc(Register rt, int16_t offset); | |
642 void bgezc(Register rt, Label* L) { | |
643 bgezc(rt, branch_offset_compact(L, false)>>2); | |
644 } | |
645 void bgeuc(Register rs, Register rt, int16_t offset); | |
646 void bgeuc(Register rs, Register rt, Label* L) { | |
647 bgeuc(rs, rt, branch_offset_compact(L, false)>>2); | |
648 } | |
649 void bgec(Register rs, Register rt, int16_t offset); | |
650 void bgec(Register rs, Register rt, Label* L) { | |
651 bgec(rs, rt, branch_offset_compact(L, false)>>2); | |
652 } | |
653 void bgezal(Register rs, int16_t offset); | 630 void bgezal(Register rs, int16_t offset); |
654 void bgezalc(Register rt, int16_t offset); | |
655 void bgezalc(Register rt, Label* L) { | |
656 bgezalc(rt, branch_offset_compact(L, false)>>2); | |
657 } | |
658 void bgezall(Register rs, int16_t offset); | |
659 void bgezall(Register rs, Label* L) { | |
660 bgezall(rs, branch_offset(L, false)>>2); | |
661 } | |
662 void bgtz(Register rs, int16_t offset); | 631 void bgtz(Register rs, int16_t offset); |
663 void bgtzc(Register rt, int16_t offset); | |
664 void bgtzc(Register rt, Label* L) { | |
665 bgtzc(rt, branch_offset_compact(L, false)>>2); | |
666 } | |
667 void blez(Register rs, int16_t offset); | 632 void blez(Register rs, int16_t offset); |
668 void blezc(Register rt, int16_t offset); | |
669 void blezc(Register rt, Label* L) { | |
670 blezc(rt, branch_offset_compact(L, false)>>2); | |
671 } | |
672 void bltz(Register rs, int16_t offset); | 633 void bltz(Register rs, int16_t offset); |
673 void bltzc(Register rt, int16_t offset); | |
674 void bltzc(Register rt, Label* L) { | |
675 bltzc(rt, branch_offset_compact(L, false)>>2); | |
676 } | |
677 void bltuc(Register rs, Register rt, int16_t offset); | |
678 void bltuc(Register rs, Register rt, Label* L) { | |
679 bltuc(rs, rt, branch_offset_compact(L, false)>>2); | |
680 } | |
681 void bltc(Register rs, Register rt, int16_t offset); | |
682 void bltc(Register rs, Register rt, Label* L) { | |
683 bltc(rs, rt, branch_offset_compact(L, false)>>2); | |
684 } | |
685 void bltzal(Register rs, int16_t offset); | 634 void bltzal(Register rs, int16_t offset); |
686 void blezalc(Register rt, int16_t offset); | |
687 void blezalc(Register rt, Label* L) { | |
688 blezalc(rt, branch_offset_compact(L, false)>>2); | |
689 } | |
690 void bltzalc(Register rt, int16_t offset); | |
691 void bltzalc(Register rt, Label* L) { | |
692 bltzalc(rt, branch_offset_compact(L, false)>>2); | |
693 } | |
694 void bgtzalc(Register rt, int16_t offset); | |
695 void bgtzalc(Register rt, Label* L) { | |
696 bgtzalc(rt, branch_offset_compact(L, false)>>2); | |
697 } | |
698 void beqzalc(Register rt, int16_t offset); | |
699 void beqzalc(Register rt, Label* L) { | |
700 beqzalc(rt, branch_offset_compact(L, false)>>2); | |
701 } | |
702 void beqc(Register rs, Register rt, int16_t offset); | |
703 void beqc(Register rs, Register rt, Label* L) { | |
704 beqc(rs, rt, branch_offset_compact(L, false)>>2); | |
705 } | |
706 void beqzc(Register rs, int32_t offset); | |
707 void beqzc(Register rs, Label* L) { | |
708 beqzc(rs, branch_offset21_compact(L, false)>>2); | |
709 } | |
710 void bnezalc(Register rt, int16_t offset); | |
711 void bnezalc(Register rt, Label* L) { | |
712 bnezalc(rt, branch_offset_compact(L, false)>>2); | |
713 } | |
714 void bnec(Register rs, Register rt, int16_t offset); | |
715 void bnec(Register rs, Register rt, Label* L) { | |
716 bnec(rs, rt, branch_offset_compact(L, false)>>2); | |
717 } | |
718 void bnezc(Register rt, int32_t offset); | |
719 void bnezc(Register rt, Label* L) { | |
720 bnezc(rt, branch_offset21_compact(L, false)>>2); | |
721 } | |
722 void bne(Register rs, Register rt, int16_t offset); | 635 void bne(Register rs, Register rt, int16_t offset); |
723 void bne(Register rs, Register rt, Label* L) { | 636 void bne(Register rs, Register rt, Label* L) { |
724 bne(rs, rt, branch_offset(L, false)>>2); | 637 bne(rs, rt, branch_offset(L, false)>>2); |
725 } | 638 } |
726 void bovc(Register rs, Register rt, int16_t offset); | |
727 void bovc(Register rs, Register rt, Label* L) { | |
728 bovc(rs, rt, branch_offset_compact(L, false)>>2); | |
729 } | |
730 void bnvc(Register rs, Register rt, int16_t offset); | |
731 void bnvc(Register rs, Register rt, Label* L) { | |
732 bnvc(rs, rt, branch_offset_compact(L, false)>>2); | |
733 } | |
734 | 639 |
735 // Never use the int16_t b(l)cond version with a branch offset | 640 // Never use the int16_t b(l)cond version with a branch offset |
736 // instead of using the Label* version. | 641 // instead of using the Label* version. |
737 | 642 |
738 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits. | 643 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits. |
739 void j(int32_t target); | 644 void j(int32_t target); |
740 void jal(int32_t target); | 645 void jal(int32_t target); |
741 void jalr(Register rs, Register rd = ra); | 646 void jalr(Register rs, Register rd = ra); |
742 void jr(Register target); | 647 void jr(Register target); |
743 void j_or_jr(int32_t target, Register rs); | 648 void j_or_jr(int32_t target, Register rs); |
744 void jal_or_jalr(int32_t target, Register rs); | 649 void jal_or_jalr(int32_t target, Register rs); |
745 | 650 |
746 | 651 |
747 // -------Data-processing-instructions--------- | 652 // -------Data-processing-instructions--------- |
748 | 653 |
749 // Arithmetic. | 654 // Arithmetic. |
750 void addu(Register rd, Register rs, Register rt); | 655 void addu(Register rd, Register rs, Register rt); |
751 void subu(Register rd, Register rs, Register rt); | 656 void subu(Register rd, Register rs, Register rt); |
752 void mult(Register rs, Register rt); | 657 void mult(Register rs, Register rt); |
753 void multu(Register rs, Register rt); | 658 void multu(Register rs, Register rt); |
754 void div(Register rs, Register rt); | 659 void div(Register rs, Register rt); |
755 void divu(Register rs, Register rt); | 660 void divu(Register rs, Register rt); |
756 void div(Register rd, Register rs, Register rt); | |
757 void divu(Register rd, Register rs, Register rt); | |
758 void mod(Register rd, Register rs, Register rt); | |
759 void modu(Register rd, Register rs, Register rt); | |
760 void mul(Register rd, Register rs, Register rt); | 661 void mul(Register rd, Register rs, Register rt); |
761 void muh(Register rd, Register rs, Register rt); | |
762 void mulu(Register rd, Register rs, Register rt); | |
763 void muhu(Register rd, Register rs, Register rt); | |
764 | 662 |
765 void addiu(Register rd, Register rs, int32_t j); | 663 void addiu(Register rd, Register rs, int32_t j); |
766 | 664 |
767 // Logical. | 665 // Logical. |
768 void and_(Register rd, Register rs, Register rt); | 666 void and_(Register rd, Register rs, Register rt); |
769 void or_(Register rd, Register rs, Register rt); | 667 void or_(Register rd, Register rs, Register rt); |
770 void xor_(Register rd, Register rs, Register rt); | 668 void xor_(Register rd, Register rs, Register rt); |
771 void nor(Register rd, Register rs, Register rt); | 669 void nor(Register rd, Register rs, Register rt); |
772 | 670 |
773 void andi(Register rd, Register rs, int32_t j); | 671 void andi(Register rd, Register rs, int32_t j); |
774 void ori(Register rd, Register rs, int32_t j); | 672 void ori(Register rd, Register rs, int32_t j); |
775 void xori(Register rd, Register rs, int32_t j); | 673 void xori(Register rd, Register rs, int32_t j); |
776 void lui(Register rd, int32_t j); | 674 void lui(Register rd, int32_t j); |
777 void aui(Register rs, Register rt, int32_t j); | |
778 | 675 |
779 // Shifts. | 676 // Shifts. |
780 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop | 677 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop |
781 // and may cause problems in normal code. coming_from_nop makes sure this | 678 // and may cause problems in normal code. coming_from_nop makes sure this |
782 // doesn't happen. | 679 // doesn't happen. |
783 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); | 680 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); |
784 void sllv(Register rd, Register rt, Register rs); | 681 void sllv(Register rd, Register rt, Register rs); |
785 void srl(Register rd, Register rt, uint16_t sa); | 682 void srl(Register rd, Register rt, uint16_t sa); |
786 void srlv(Register rd, Register rt, Register rs); | 683 void srlv(Register rd, Register rt, Register rs); |
787 void sra(Register rt, Register rd, uint16_t sa); | 684 void sra(Register rt, Register rd, uint16_t sa); |
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832 void sltu(Register rd, Register rs, Register rt); | 729 void sltu(Register rd, Register rs, Register rt); |
833 void slti(Register rd, Register rs, int32_t j); | 730 void slti(Register rd, Register rs, int32_t j); |
834 void sltiu(Register rd, Register rs, int32_t j); | 731 void sltiu(Register rd, Register rs, int32_t j); |
835 | 732 |
836 // Conditional move. | 733 // Conditional move. |
837 void movz(Register rd, Register rs, Register rt); | 734 void movz(Register rd, Register rs, Register rt); |
838 void movn(Register rd, Register rs, Register rt); | 735 void movn(Register rd, Register rs, Register rt); |
839 void movt(Register rd, Register rs, uint16_t cc = 0); | 736 void movt(Register rd, Register rs, uint16_t cc = 0); |
840 void movf(Register rd, Register rs, uint16_t cc = 0); | 737 void movf(Register rd, Register rs, uint16_t cc = 0); |
841 | 738 |
842 void sel(SecondaryField fmt, FPURegister fd, FPURegister ft, | |
843 FPURegister fs, uint8_t sel); | |
844 void seleqz(Register rs, Register rt, Register rd); | |
845 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister ft, | |
846 FPURegister fs); | |
847 void selnez(Register rs, Register rt, Register rd); | |
848 void selnez(SecondaryField fmt, FPURegister fd, FPURegister ft, | |
849 FPURegister fs); | |
850 | |
851 // Bit twiddling. | 739 // Bit twiddling. |
852 void clz(Register rd, Register rs); | 740 void clz(Register rd, Register rs); |
853 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); | 741 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); |
854 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); | 742 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); |
855 | 743 |
856 // --------Coprocessor-instructions---------------- | 744 // --------Coprocessor-instructions---------------- |
857 | 745 |
858 // Load, store, and move. | 746 // Load, store, and move. |
859 void lwc1(FPURegister fd, const MemOperand& src); | 747 void lwc1(FPURegister fd, const MemOperand& src); |
860 void ldc1(FPURegister fd, const MemOperand& src); | 748 void ldc1(FPURegister fd, const MemOperand& src); |
861 | 749 |
862 void swc1(FPURegister fs, const MemOperand& dst); | 750 void swc1(FPURegister fs, const MemOperand& dst); |
863 void sdc1(FPURegister fs, const MemOperand& dst); | 751 void sdc1(FPURegister fs, const MemOperand& dst); |
864 | 752 |
865 void mtc1(Register rt, FPURegister fs); | 753 void mtc1(Register rt, FPURegister fs); |
866 void mthc1(Register rt, FPURegister fs); | |
867 | |
868 void mfc1(Register rt, FPURegister fs); | 754 void mfc1(Register rt, FPURegister fs); |
869 void mfhc1(Register rt, FPURegister fs); | |
870 | 755 |
871 void ctc1(Register rt, FPUControlRegister fs); | 756 void ctc1(Register rt, FPUControlRegister fs); |
872 void cfc1(Register rt, FPUControlRegister fs); | 757 void cfc1(Register rt, FPUControlRegister fs); |
873 | 758 |
874 // Arithmetic. | 759 // Arithmetic. |
875 void add_d(FPURegister fd, FPURegister fs, FPURegister ft); | 760 void add_d(FPURegister fd, FPURegister fs, FPURegister ft); |
876 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft); | 761 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft); |
877 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft); | 762 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft); |
878 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); | 763 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); |
879 void div_d(FPURegister fd, FPURegister fs, FPURegister ft); | 764 void div_d(FPURegister fd, FPURegister fs, FPURegister ft); |
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898 void cvt_l_d(FPURegister fd, FPURegister fs); | 783 void cvt_l_d(FPURegister fd, FPURegister fs); |
899 void trunc_l_s(FPURegister fd, FPURegister fs); | 784 void trunc_l_s(FPURegister fd, FPURegister fs); |
900 void trunc_l_d(FPURegister fd, FPURegister fs); | 785 void trunc_l_d(FPURegister fd, FPURegister fs); |
901 void round_l_s(FPURegister fd, FPURegister fs); | 786 void round_l_s(FPURegister fd, FPURegister fs); |
902 void round_l_d(FPURegister fd, FPURegister fs); | 787 void round_l_d(FPURegister fd, FPURegister fs); |
903 void floor_l_s(FPURegister fd, FPURegister fs); | 788 void floor_l_s(FPURegister fd, FPURegister fs); |
904 void floor_l_d(FPURegister fd, FPURegister fs); | 789 void floor_l_d(FPURegister fd, FPURegister fs); |
905 void ceil_l_s(FPURegister fd, FPURegister fs); | 790 void ceil_l_s(FPURegister fd, FPURegister fs); |
906 void ceil_l_d(FPURegister fd, FPURegister fs); | 791 void ceil_l_d(FPURegister fd, FPURegister fs); |
907 | 792 |
908 void min(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs); | |
909 void mina(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs); | |
910 void max(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs); | |
911 void maxa(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs); | |
912 | |
913 void cvt_s_w(FPURegister fd, FPURegister fs); | 793 void cvt_s_w(FPURegister fd, FPURegister fs); |
914 void cvt_s_l(FPURegister fd, FPURegister fs); | 794 void cvt_s_l(FPURegister fd, FPURegister fs); |
915 void cvt_s_d(FPURegister fd, FPURegister fs); | 795 void cvt_s_d(FPURegister fd, FPURegister fs); |
916 | 796 |
917 void cvt_d_w(FPURegister fd, FPURegister fs); | 797 void cvt_d_w(FPURegister fd, FPURegister fs); |
918 void cvt_d_l(FPURegister fd, FPURegister fs); | 798 void cvt_d_l(FPURegister fd, FPURegister fs); |
919 void cvt_d_s(FPURegister fd, FPURegister fs); | 799 void cvt_d_s(FPURegister fd, FPURegister fs); |
920 | 800 |
921 // Conditions and branches for MIPSr6. | 801 // Conditions and branches. |
922 void cmp(FPUCondition cond, SecondaryField fmt, | |
923 FPURegister fd, FPURegister ft, FPURegister fs); | |
924 | |
925 void bc1eqz(int16_t offset, FPURegister ft); | |
926 void bc1eqz(Label* L, FPURegister ft) { | |
927 bc1eqz(branch_offset(L, false)>>2, ft); | |
928 } | |
929 void bc1nez(int16_t offset, FPURegister ft); | |
930 void bc1nez(Label* L, FPURegister ft) { | |
931 bc1nez(branch_offset(L, false)>>2, ft); | |
932 } | |
933 | |
934 // Conditions and branches for non MIPSr6. | |
935 void c(FPUCondition cond, SecondaryField fmt, | 802 void c(FPUCondition cond, SecondaryField fmt, |
936 FPURegister ft, FPURegister fs, uint16_t cc = 0); | 803 FPURegister ft, FPURegister fs, uint16_t cc = 0); |
937 | 804 |
938 void bc1f(int16_t offset, uint16_t cc = 0); | 805 void bc1f(int16_t offset, uint16_t cc = 0); |
939 void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); } | 806 void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); } |
940 void bc1t(int16_t offset, uint16_t cc = 0); | 807 void bc1t(int16_t offset, uint16_t cc = 0); |
941 void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); } | 808 void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); } |
942 void fcmp(FPURegister src1, const double src2, FPUCondition cond); | 809 void fcmp(FPURegister src1, const double src2, FPUCondition cond); |
943 | 810 |
944 // Check the code size generated from label to here. | 811 // Check the code size generated from label to here. |
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1370 class EnsureSpace BASE_EMBEDDED { | 1237 class EnsureSpace BASE_EMBEDDED { |
1371 public: | 1238 public: |
1372 explicit EnsureSpace(Assembler* assembler) { | 1239 explicit EnsureSpace(Assembler* assembler) { |
1373 assembler->CheckBuffer(); | 1240 assembler->CheckBuffer(); |
1374 } | 1241 } |
1375 }; | 1242 }; |
1376 | 1243 |
1377 } } // namespace v8::internal | 1244 } } // namespace v8::internal |
1378 | 1245 |
1379 #endif // V8_ARM_ASSEMBLER_MIPS_H_ | 1246 #endif // V8_ARM_ASSEMBLER_MIPS_H_ |
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