Subzero: Randomize register assignment.

tests_lit/llvm2ice_tests/randomize-regalloc.ll

Index: tests_lit/llvm2ice_tests/randomize-regalloc.ll
diff --git a/tests_lit/llvm2ice_tests/randomize-regalloc.ll b/tests_lit/llvm2ice_tests/randomize-regalloc.ll
new file mode 100644
index 0000000000000000000000000000000000000000..a2d18af59ffbeb7a78ee84812df0eed3e746051d
--- /dev/null
+++ b/tests_lit/llvm2ice_tests/randomize-regalloc.ll
@@ -0,0 +1,50 @@
+; This is a smoke test of randomized register allocation.  The output
+; of this test will change with changes to the random number generator
+; implementation.
+
+; RUN: %llvm2ice -O2  -rng-seed=1 -randomize-regalloc %s \
+; RUN:                               | FileCheck %s --check-prefix=CHECK
+; RUN: %llvm2ice -Om1 -rng-seed=1 -randomize-regalloc %s \
+; RUN:                               | FileCheck %s --check-prefix=OPTM1
+; RUN: %llvm2ice -O2 -rng-seed=1 -randomize-regalloc %s \
+; RUN:     | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: %llvm2ice -Om1 -rng-seed=1 -randomize-regalloc %s \
+; RUN:     | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
+; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
+; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
+; RUN:                           | FileCheck --check-prefix=DUMP %s
+
+define <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
+entry:
+  %res = mul <4 x i32> %a, %b
+  ret <4 x i32> %res
+; OPTM1-LABEL: mul_v4i32:
+; OPTM1: sub     esp, 60
+; OPTM1: movups  xmmword ptr [esp+32], xmm0
+; OPTM1: movups  xmmword ptr [esp+16], xmm1
+; OPTM1: movups  xmm7, xmmword ptr [esp+32]
+; OPTM1: pshufd  xmm0, xmmword ptr [esp+32], 49
+; OPTM1: pshufd  xmm1, xmmword ptr [esp+16], 49
+; OPTM1: pmuludq xmm7, xmmword ptr [esp+16]
+; OPTM1: pmuludq xmm0, xmm1
+; OPTM1: shufps  xmm7, xmm0, 136
+; OPTM1: pshufd  xmm2, xmm7, 216
+; OPTM1: movups  xmmword ptr [esp], xmm2
+; OPTM1: movups  xmm0, xmmword ptr [esp]
+; OPTM1: add     esp, 60
+; OPTM1: ret
+
+; CHECK-LABEL: mul_v4i32:
+; CHECK: movups  xmm5, xmm0
+; CHECK: pshufd  xmm0, xmm0, 49
+; CHECK: pshufd  xmm2, xmm1, 49
+; CHECK: pmuludq xmm5, xmm1
+; CHECK: pmuludq xmm0, xmm2
+; CHECK: shufps  xmm5, xmm0, 136
+; CHECK: pshufd  xmm0, xmm5, 216
+; CHECK: ret
+}
+
+; ERRORS-NOT: ICE translation error
+; DUMP-NOT: SZ