Subzero: Randomize register assignment.

src/IceTargetLowering.cpp

 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the skeleton of the TargetLowering class,
 // specifically invoking the appropriate lowering method for a given
 // instruction kind and driving global register allocation.  It also
 // implements the non-deleted instruction iteration in
 // LoweringContext.
 //
 //===----------------------------------------------------------------------===//
 
 #include "IceCfg.h" // setError()
 #include "IceCfgNode.h"
 #include "IceOperand.h"
 #include "IceRegAlloc.h"
 #include "IceTargetLowering.h"
 #include "IceTargetLoweringX8632.h"
+#include "llvm/Support/CommandLine.h"
 
 namespace Ice {
 
+namespace {
+
+namespace cl = ::llvm::cl;
+cl::opt<bool>
+    CLRandomizeRegisterAllocation("randomize-regalloc",
+                                  cl::desc("Randomize register allocation"),
+                                  cl::init(false));
+
+} // end of anonymous namespace
+
 void LoweringContext::init(CfgNode *N) {
   Node = N;
   Begin = getNode()->getInsts().begin();
   Cur = Begin;
   End = getNode()->getInsts().end();
   skipDeleted(Cur);
   Next = Cur;
   advanceForward(Next);
 }
 
@@ skipping 37 matching lines @@
     return IceTargetX8664::create(Func);
   if (Target == Target_ARM32)
     return IceTargetARM32::create(Func);
   if (Target == Target_ARM64)
     return IceTargetARM64::create(Func);
 #endif
   Func->setError("Unsupported target");
   return NULL;
 }
 
+TargetLowering::TargetLowering(Cfg *Func)
+    : Func(Func), Ctx(Func->getContext()), HasComputedFrame(false),
+      StackAdjustment(0),
+      RandomizeRegisterAllocation(CLRandomizeRegisterAllocation) {}
+
 void TargetLowering::doAddressOpt() {
   if (llvm::isa<InstLoad>(*Context.getCur()))
     doAddressOptLoad();
   else if (llvm::isa<InstStore>(*Context.getCur()))
     doAddressOptStore();
   Context.advanceCur();
   Context.advanceNext();
 }
 
 // Lowers a single instruction according to the information in
@@ skipping 89 matching lines @@
 // registers e.g. for performance testing.
 void TargetLowering::regAlloc() {
   LinearScan LinearScan(Func);
   RegSetMask RegInclude = RegSet_None;
   RegSetMask RegExclude = RegSet_None;
   RegInclude |= RegSet_CallerSave;
   RegInclude |= RegSet_CalleeSave;
   if (hasFramePointer())
     RegExclude |= RegSet_FramePointer;
   llvm::SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude);
-  LinearScan.scan(RegMask);
+  LinearScan.scan(RegMask, RandomizeRegisterAllocation);
 }
 
 TargetGlobalInitLowering *
 TargetGlobalInitLowering::createLowering(TargetArch Target,
                                          GlobalContext *Ctx) {
   // These statements can be #ifdef'd to specialize the code generator
   // to a subset of the available targets.  TODO: use CRTP.
   if (Target == Target_X8632)
     return TargetGlobalInitX8632::create(Ctx);
 #if 0
   if (Target == Target_X8664)
     return IceTargetGlobalInitX8664::create(Ctx);
   if (Target == Target_ARM32)
     return IceTargetGlobalInitARM32::create(Ctx);
   if (Target == Target_ARM64)
     return IceTargetGlobalInitARM64::create(Ctx);
 #endif
   llvm_unreachable("Unsupported target");
   return NULL;
 }
 
 TargetGlobalInitLowering::~TargetGlobalInitLowering() {}
 
 } // end of namespace Ice