Subzero: Randomize register assignment.

tests_lit/llvm2ice_tests/randomize-regalloc.ll

+; This is a smoke test of randomized register allocation.
+
+; RUN: %llvm2ice -rng-seed=1 -randomize-regalloc %s \

[Jim Stichnoth, 2014/08/14 01:10:29]

Add an explicit -Om1 option.

Also, add the rest of the usual test configurations?  And the target triple
option?

May be worth documenting that everything changes when the RNG implementation
changes.

[wala, 2014/08/15 03:37:23]

Done.

+; RUN:                               | FileCheck %s --check-prefix=OPTM1
+; RUN: %llvm2ice -O2 -rng-seed=1 -randomize-regalloc %s \
+; RUN:                               | FileCheck %s --check-prefix=CHECK
+
+define <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
+entry:
+  %res = mul <4 x i32> %a, %b
+  ret <4 x i32> %res
+; OPTM1-LABEL: mul_v4i32:
+; OPTM1: sub esp, 48
+; OPTM1: movups xmmword ptr [esp+32], xmm0
+; OPTM1: movups xmmword ptr [esp+16], xmm1
+; OPTM1: movups xmm1, xmmword ptr [esp+32]
+; OPTM1: movups xmm6, xmmword ptr [esp+32]
+; OPTM1: movups xmm3, xmmword ptr [esp+16]
+; OPTM1: pshufd xmm2, xmm6, 49
+; OPTM1: pshufd xmm4, xmm3, 49
+; OPTM1: pmuludq xmm1, xmm3
+; OPTM1: pmuludq xmm2, xmm4
+; OPTM1: shufps xmm1, xmm2, 136
+; OPTM1: pshufd xmm0, xmm1, 216
+; OPTM1: movups xmmword ptr [esp], xmm0
+; OPTM1: movups xmm0, xmmword ptr [esp]
+; OPTM1: add esp, 48
+; OPTM1: ret
+
+; CHECK-LABEL: mul_v4i32:
+; CHECK: movups xmm5, xmm0
+; CHECK: pshufd xmm0, xmm0, 49
+; CHECK: pshufd xmm2, xmm1, 49
+; CHECK: pmuludq xmm5, xmm1
+; CHECK: pmuludq xmm0, xmm2
+; CHECK: shufps xmm5, xmm0, 136
+; CHECK: pshufd xmm0, xmm5, 216
+; CHECK: ret
+}