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1 # Copyright 2013 the V8 project authors. All rights reserved. | 1 # Copyright 2013 the V8 project authors. All rights reserved. |
2 # Redistribution and use in source and binary forms, with or without | 2 # Redistribution and use in source and binary forms, with or without |
3 # modification, are permitted provided that the following conditions are | 3 # modification, are permitted provided that the following conditions are |
4 # met: | 4 # met: |
5 # | 5 # |
6 # * Redistributions of source code must retain the above copyright | 6 # * Redistributions of source code must retain the above copyright |
7 # notice, this list of conditions and the following disclaimer. | 7 # notice, this list of conditions and the following disclaimer. |
8 # * Redistributions in binary form must reproduce the above | 8 # * Redistributions in binary form must reproduce the above |
9 # copyright notice, this list of conditions and the following | 9 # copyright notice, this list of conditions and the following |
10 # disclaimer in the documentation and/or other materials provided | 10 # disclaimer in the documentation and/or other materials provided |
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51 | 51 |
52 # Similar to vfp but on MIPS. | 52 # Similar to vfp but on MIPS. |
53 'v8_can_use_fpu_instructions%': 'true', | 53 'v8_can_use_fpu_instructions%': 'true', |
54 | 54 |
55 # Similar to the ARM hard float ABI but on MIPS. | 55 # Similar to the ARM hard float ABI but on MIPS. |
56 'v8_use_mips_abi_hardfloat%': 'true', | 56 'v8_use_mips_abi_hardfloat%': 'true', |
57 | 57 |
58 # Default arch variant for MIPS. | 58 # Default arch variant for MIPS. |
59 'mips_arch_variant%': 'r2', | 59 'mips_arch_variant%': 'r2', |
60 | 60 |
61 # Possible values fp32, fp64, fpxx. | |
62 # fp32 - 32 32-bit FPU registers are available, doubles are placed in | |
63 # register pairs. | |
64 # fp64 - 32 64-bit FPU registers are available. | |
65 # fpxx - compatibility mode, it chooses fp32 or fp64 depending on runtime | |
66 # detection | |
67 'mips_fpu_mode%': 'fp32', | |
68 | |
61 'v8_enable_backtrace%': 0, | 69 'v8_enable_backtrace%': 0, |
62 | 70 |
63 # Enable profiling support. Only required on Windows. | 71 # Enable profiling support. Only required on Windows. |
64 'v8_enable_prof%': 0, | 72 'v8_enable_prof%': 0, |
65 | 73 |
66 # Some versions of GCC 4.5 seem to need -fno-strict-aliasing. | 74 # Some versions of GCC 4.5 seem to need -fno-strict-aliasing. |
67 'v8_no_strict_aliasing%': 0, | 75 'v8_no_strict_aliasing%': 0, |
68 | 76 |
69 # Chrome needs this definition unconditionally. For standalone V8 builds, | 77 # Chrome needs this definition unconditionally. For standalone V8 builds, |
70 # it's handled in build/standalone.gypi. | 78 # it's handled in build/standalone.gypi. |
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265 'cflags': ['-EB'], | 273 'cflags': ['-EB'], |
266 'ldflags': ['-EB'], | 274 'ldflags': ['-EB'], |
267 'conditions': [ | 275 'conditions': [ |
268 [ 'v8_use_mips_abi_hardfloat=="true"', { | 276 [ 'v8_use_mips_abi_hardfloat=="true"', { |
269 'cflags': ['-mhard-float'], | 277 'cflags': ['-mhard-float'], |
270 'ldflags': ['-mhard-float'], | 278 'ldflags': ['-mhard-float'], |
271 }, { | 279 }, { |
272 'cflags': ['-msoft-float'], | 280 'cflags': ['-msoft-float'], |
273 'ldflags': ['-msoft-float'], | 281 'ldflags': ['-msoft-float'], |
274 }], | 282 }], |
283 ['mips_fpu_mode=="fp64"', { | |
284 'cflags': ['-mfp64',], | |
Jakob Kummerow
2014/08/11 08:00:46
nit: the comma before ']' isn't necessary (but I d
| |
285 }], | |
286 ['mips_fpu_mode=="fpxx"', { | |
287 'cflags': ['-mfpxx',], | |
288 }], | |
289 ['mips_fpu_mode=="fp32"', { | |
290 'cflags': ['-mfp32',], | |
291 }], | |
292 ['mips_arch_variant=="r6"', { | |
293 'cflags!': ['-mfp32'], | |
294 'cflags': ['-mips32r6', '-Wa,-mips32r6'], | |
295 'ldflags': [ | |
296 '-mips32r6', | |
297 '-Wl,--dynamic-linker=$(LDSO_PATH)', | |
298 '-Wl,--rpath=$(LD_R_PATH)', | |
299 ], | |
300 }], | |
275 ['mips_arch_variant=="r2"', { | 301 ['mips_arch_variant=="r2"', { |
276 'cflags': ['-mips32r2', '-Wa,-mips32r2'], | 302 'cflags': ['-mips32r2', '-Wa,-mips32r2'], |
277 }], | 303 }], |
278 ['mips_arch_variant=="r1"', { | 304 ['mips_arch_variant=="r1"', { |
305 'cflags!': ['-mfp64'], | |
306 'cflags': ['-mips32', '-Wa,-mips32'], | |
307 }], | |
308 ['mips_arch_variant=="rx"', { | |
309 'cflags!': ['-mfp64'], | |
279 'cflags': ['-mips32', '-Wa,-mips32'], | 310 'cflags': ['-mips32', '-Wa,-mips32'], |
280 }], | 311 }], |
281 ], | 312 ], |
282 }], | 313 }], |
283 ], | 314 ], |
284 }], | 315 }], |
285 [ 'v8_can_use_fpu_instructions=="true"', { | 316 [ 'v8_can_use_fpu_instructions=="true"', { |
286 'defines': [ | 317 'defines': [ |
287 'CAN_USE_FPU_INSTRUCTIONS', | 318 'CAN_USE_FPU_INSTRUCTIONS', |
288 ], | 319 ], |
289 }], | 320 }], |
290 [ 'v8_use_mips_abi_hardfloat=="true"', { | 321 [ 'v8_use_mips_abi_hardfloat=="true"', { |
291 'defines': [ | 322 'defines': [ |
292 '__mips_hard_float=1', | 323 '__mips_hard_float=1', |
293 'CAN_USE_FPU_INSTRUCTIONS', | 324 'CAN_USE_FPU_INSTRUCTIONS', |
294 ], | 325 ], |
295 }, { | 326 }, { |
296 'defines': [ | 327 'defines': [ |
297 '__mips_soft_float=1' | 328 '__mips_soft_float=1' |
298 ], | 329 ], |
299 }], | 330 }], |
331 ['mips_arch_variant=="rx"', { | |
332 'defines': ['_MIPS_ARCH_MIPS32RX',], | |
333 'defines': ['FPU_MODE_FPXX',], | |
334 }], | |
335 ['mips_arch_variant=="r6"', { | |
336 'defines': ['_MIPS_ARCH_MIPS32R6','FPU_MODE_FP64',], | |
Jakob Kummerow
2014/08/11 08:00:46
nit: space after comma please
| |
337 }], | |
300 ['mips_arch_variant=="r2"', { | 338 ['mips_arch_variant=="r2"', { |
301 'defines': ['_MIPS_ARCH_MIPS32R2',], | 339 'defines': ['_MIPS_ARCH_MIPS32R2',], |
340 'conditions': [ | |
341 ['mips_fpu_mode=="fp64"', { | |
342 'defines': ['FPU_MODE_FP64',], | |
343 }], | |
344 ['mips_fpu_mode=="fpxx"', { | |
345 'defines': ['FPU_MODE_FPXX',], | |
346 }], | |
347 ['mips_fpu_mode=="fp32"', { | |
348 'defines': ['FPU_MODE_FP32',], | |
349 }], | |
350 ], | |
351 }], | |
352 ['mips_arch_variant=="r1"', { | |
353 'defines': ['FPU_MODE_FP32',], | |
302 }], | 354 }], |
303 ], | 355 ], |
304 }], # v8_target_arch=="mips" | 356 }], # v8_target_arch=="mips" |
305 ['v8_target_arch=="mipsel"', { | 357 ['v8_target_arch=="mipsel"', { |
306 'defines': [ | 358 'defines': [ |
307 'V8_TARGET_ARCH_MIPS', | 359 'V8_TARGET_ARCH_MIPS', |
308 ], | 360 ], |
309 'conditions': [ | 361 'conditions': [ |
310 ['v8_target_arch==target_arch and android_webview_build==0', { | 362 ['v8_target_arch==target_arch and android_webview_build==0', { |
311 # Target built with a Mips CXX compiler. | 363 # Target built with a Mips CXX compiler. |
312 'target_conditions': [ | 364 'target_conditions': [ |
313 ['_toolset=="target"', { | 365 ['_toolset=="target"', { |
314 'cflags': ['-EL'], | 366 'cflags': ['-EL'], |
315 'ldflags': ['-EL'], | 367 'ldflags': ['-EL'], |
316 'conditions': [ | 368 'conditions': [ |
317 [ 'v8_use_mips_abi_hardfloat=="true"', { | 369 [ 'v8_use_mips_abi_hardfloat=="true"', { |
318 'cflags': ['-mhard-float'], | 370 'cflags': ['-mhard-float'], |
319 'ldflags': ['-mhard-float'], | 371 'ldflags': ['-mhard-float'], |
320 }, { | 372 }, { |
321 'cflags': ['-msoft-float'], | 373 'cflags': ['-msoft-float'], |
322 'ldflags': ['-msoft-float'], | 374 'ldflags': ['-msoft-float'], |
323 }], | 375 }], |
376 ['mips_fpu_mode=="fp64"', { | |
377 'cflags': ['-mfp64',], | |
378 }], | |
379 ['mips_fpu_mode=="fpxx"', { | |
380 'cflags': ['-mfpxx',], | |
381 }], | |
382 ['mips_fpu_mode=="fp32"', { | |
383 'cflags': ['-mfp32',], | |
384 }], | |
385 ['mips_arch_variant=="r6"', { | |
386 'cflags!': ['-mfp32'], | |
387 'cflags': ['-mips32r6', '-Wa,-mips32r6'], | |
388 'ldflags': [ | |
389 '-mips32r6', | |
390 '-Wl,--dynamic-linker=$(LDSO_PATH)', | |
391 '-Wl,--rpath=$(LD_R_PATH)', | |
392 ], | |
393 }], | |
324 ['mips_arch_variant=="r2"', { | 394 ['mips_arch_variant=="r2"', { |
325 'cflags': ['-mips32r2', '-Wa,-mips32r2'], | 395 'cflags': ['-mips32r2', '-Wa,-mips32r2'], |
326 }], | 396 }], |
327 ['mips_arch_variant=="r1"', { | 397 ['mips_arch_variant=="r1"', { |
398 'cflags!': ['-mfp64'], | |
328 'cflags': ['-mips32', '-Wa,-mips32'], | 399 'cflags': ['-mips32', '-Wa,-mips32'], |
329 }], | 400 }], |
401 ['mips_arch_variant=="rx"', { | |
402 'cflags!': ['-mfp64'], | |
403 'cflags': ['-mips32', '-Wa,-mips32'], | |
404 }], | |
330 ['mips_arch_variant=="loongson"', { | 405 ['mips_arch_variant=="loongson"', { |
406 'cflags!': ['-mfp64'], | |
331 'cflags': ['-mips3', '-Wa,-mips3'], | 407 'cflags': ['-mips3', '-Wa,-mips3'], |
332 }], | 408 }], |
333 ], | 409 ], |
334 }], | 410 }], |
335 ], | 411 ], |
336 }], | 412 }], |
337 [ 'v8_can_use_fpu_instructions=="true"', { | 413 [ 'v8_can_use_fpu_instructions=="true"', { |
338 'defines': [ | 414 'defines': [ |
339 'CAN_USE_FPU_INSTRUCTIONS', | 415 'CAN_USE_FPU_INSTRUCTIONS', |
340 ], | 416 ], |
341 }], | 417 }], |
342 [ 'v8_use_mips_abi_hardfloat=="true"', { | 418 [ 'v8_use_mips_abi_hardfloat=="true"', { |
343 'defines': [ | 419 'defines': [ |
344 '__mips_hard_float=1', | 420 '__mips_hard_float=1', |
345 'CAN_USE_FPU_INSTRUCTIONS', | 421 'CAN_USE_FPU_INSTRUCTIONS', |
346 ], | 422 ], |
347 }, { | 423 }, { |
348 'defines': [ | 424 'defines': [ |
349 '__mips_soft_float=1' | 425 '__mips_soft_float=1' |
350 ], | 426 ], |
351 }], | 427 }], |
428 ['mips_arch_variant=="rx"', { | |
429 'defines': ['_MIPS_ARCH_MIPS32RX',], | |
430 'defines': ['FPU_MODE_FPXX',], | |
431 }], | |
432 ['mips_arch_variant=="r6"', { | |
433 'defines': ['_MIPS_ARCH_MIPS32R6','FPU_MODE_FP64',], | |
434 }], | |
352 ['mips_arch_variant=="r2"', { | 435 ['mips_arch_variant=="r2"', { |
353 'defines': ['_MIPS_ARCH_MIPS32R2',], | 436 'defines': ['_MIPS_ARCH_MIPS32R2',], |
437 'conditions': [ | |
438 ['mips_fpu_mode=="fp64"', { | |
439 'defines': ['FPU_MODE_FP64',], | |
440 }], | |
441 ['mips_fpu_mode=="fpxx"', { | |
442 'defines': ['FPU_MODE_FPXX',], | |
443 }], | |
444 ['mips_fpu_mode=="fp32"', { | |
445 'defines': ['FPU_MODE_FP32',], | |
446 }], | |
447 ], | |
448 }], | |
449 ['mips_arch_variant=="r1"', { | |
450 'defines': ['FPU_MODE_FP32',], | |
354 }], | 451 }], |
355 ['mips_arch_variant=="loongson"', { | 452 ['mips_arch_variant=="loongson"', { |
356 'defines': ['_MIPS_ARCH_LOONGSON',], | 453 'defines': ['_MIPS_ARCH_LOONGSON',], |
454 'defines': ['FPU_MODE_FP32',], | |
357 }], | 455 }], |
358 ], | 456 ], |
359 }], # v8_target_arch=="mipsel" | 457 }], # v8_target_arch=="mipsel" |
360 ['v8_target_arch=="mips64el"', { | 458 ['v8_target_arch=="mips64el"', { |
361 'defines': [ | 459 'defines': [ |
362 'V8_TARGET_ARCH_MIPS64', | 460 'V8_TARGET_ARCH_MIPS64', |
363 ], | 461 ], |
364 'conditions': [ | 462 'conditions': [ |
365 ['v8_target_arch==target_arch and android_webview_build==0', { | 463 ['v8_target_arch==target_arch and android_webview_build==0', { |
366 # Target built with a Mips CXX compiler. | 464 # Target built with a Mips CXX compiler. |
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841 'OptimizeReferences': '2', | 939 'OptimizeReferences': '2', |
842 'EnableCOMDATFolding': '2', | 940 'EnableCOMDATFolding': '2', |
843 }, | 941 }, |
844 }, | 942 }, |
845 }], # OS=="win" | 943 }], # OS=="win" |
846 ], # conditions | 944 ], # conditions |
847 }, # Release | 945 }, # Release |
848 }, # configurations | 946 }, # configurations |
849 }, # target_defaults | 947 }, # target_defaults |
850 } | 948 } |
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