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Issue 443203003: Subzero: Use scalar arithmetic when no vector instruction exists. (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Minor fixes: whitespace, formatting, variable names, etc. Created 6 years, 4 months ago
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1 ; This test checks support for vector arithmetic. 1 ; This test checks support for vector arithmetic.
2 2
3 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s 3 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
4 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s 4 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
5 ; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \ 5 ; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
6 ; RUN: | FileCheck %s --check-prefix=SSE41 6 ; RUN: | FileCheck %s --check-prefix=SSE41
7 ; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \ 7 ; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
8 ; RUN: | FileCheck %s --check-prefix=SSE41 8 ; RUN: | FileCheck %s --check-prefix=SSE41
9 ; RUN: %llvm2ice -O2 --verbose none %s \ 9 ; RUN: %llvm2ice -O2 --verbose none %s \
10 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj 10 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj
(...skipping 38 matching lines...) Expand 10 before | Expand all | Expand 10 after
49 ret <4 x float> %res 49 ret <4 x float> %res
50 ; CHECK-LABEL: test_fdiv: 50 ; CHECK-LABEL: test_fdiv:
51 ; CHECK: divps 51 ; CHECK: divps
52 } 52 }
53 53
54 define <4 x float> @test_frem(<4 x float> %arg0, <4 x float> %arg1) { 54 define <4 x float> @test_frem(<4 x float> %arg0, <4 x float> %arg1) {
55 entry: 55 entry:
56 %res = frem <4 x float> %arg0, %arg1 56 %res = frem <4 x float> %arg0, %arg1
57 ret <4 x float> %res 57 ret <4 x float> %res
58 ; CHECK-LABEL: test_frem: 58 ; CHECK-LABEL: test_frem:
59 ; CHECK: Sz_frem_v4f32 59 ; CHECK: fmodf
60 ; CHECK: fmodf
61 ; CHECK: fmodf
62 ; CHECK: fmodf
60 } 63 }
61 64
62 define <16 x i8> @test_add_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) { 65 define <16 x i8> @test_add_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
63 entry: 66 entry:
64 %res = add <16 x i8> %arg0, %arg1 67 %res = add <16 x i8> %arg0, %arg1
65 ret <16 x i8> %res 68 ret <16 x i8> %res
66 ; CHECK-LABEL: test_add_v16i8: 69 ; CHECK-LABEL: test_add_v16i8:
67 ; CHECK: paddb 70 ; CHECK: paddb
68 } 71 }
69 72
(...skipping 27 matching lines...) Expand all
97 ret <16 x i8> %res 100 ret <16 x i8> %res
98 ; CHECK-LABEL: test_sub_v16i8: 101 ; CHECK-LABEL: test_sub_v16i8:
99 ; CHECK: psubb 102 ; CHECK: psubb
100 } 103 }
101 104
102 define <16 x i8> @test_mul_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) { 105 define <16 x i8> @test_mul_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
103 entry: 106 entry:
104 %res = mul <16 x i8> %arg0, %arg1 107 %res = mul <16 x i8> %arg0, %arg1
105 ret <16 x i8> %res 108 ret <16 x i8> %res
106 ; CHECK-LABEL: test_mul_v16i8: 109 ; CHECK-LABEL: test_mul_v16i8:
107 ; CHECK: Sz_mul_v16i8 110 ; CHECK: imul
111 ; CHECK: imul
112 ; CHECK: imul
113 ; CHECK: imul
114 ; CHECK: imul
115 ; CHECK: imul
116 ; CHECK: imul
117 ; CHECK: imul
118 ; CHECK: imul
119 ; CHECK: imul
120 ; CHECK: imul
121 ; CHECK: imul
122 ; CHECK: imul
123 ; CHECK: imul
124 ; CHECK: imul
125 ; CHECK: imul
108 } 126 }
109 127
110 define <16 x i8> @test_shl_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) { 128 define <16 x i8> @test_shl_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
111 entry: 129 entry:
112 %res = shl <16 x i8> %arg0, %arg1 130 %res = shl <16 x i8> %arg0, %arg1
113 ret <16 x i8> %res 131 ret <16 x i8> %res
114 ; CHECK-LABEL: test_shl_v16i8: 132 ; CHECK-LABEL: test_shl_v16i8:
115 ; CHECK: Sz_shl_v16i8 133 ; CHECK: shl
134 ; CHECK: shl
135 ; CHECK: shl
136 ; CHECK: shl
137 ; CHECK: shl
138 ; CHECK: shl
139 ; CHECK: shl
140 ; CHECK: shl
141 ; CHECK: shl
142 ; CHECK: shl
143 ; CHECK: shl
144 ; CHECK: shl
145 ; CHECK: shl
146 ; CHECK: shl
147 ; CHECK: shl
148 ; CHECK: shl
116 } 149 }
117 150
118 define <16 x i8> @test_lshr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) { 151 define <16 x i8> @test_lshr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
119 entry: 152 entry:
120 %res = lshr <16 x i8> %arg0, %arg1 153 %res = lshr <16 x i8> %arg0, %arg1
121 ret <16 x i8> %res 154 ret <16 x i8> %res
122 ; CHECK-LABEL: test_lshr_v16i8: 155 ; CHECK-LABEL: test_lshr_v16i8:
123 ; CHECK: Sz_lshr_v16i8 156 ; CHECK: shr
157 ; CHECK: shr
158 ; CHECK: shr
159 ; CHECK: shr
160 ; CHECK: shr
161 ; CHECK: shr
162 ; CHECK: shr
163 ; CHECK: shr
164 ; CHECK: shr
165 ; CHECK: shr
166 ; CHECK: shr
167 ; CHECK: shr
168 ; CHECK: shr
169 ; CHECK: shr
170 ; CHECK: shr
171 ; CHECK: shr
124 } 172 }
125 173
126 define <16 x i8> @test_ashr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) { 174 define <16 x i8> @test_ashr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
127 entry: 175 entry:
128 %res = ashr <16 x i8> %arg0, %arg1 176 %res = ashr <16 x i8> %arg0, %arg1
129 ret <16 x i8> %res 177 ret <16 x i8> %res
130 ; CHECK-LABEL: test_ashr_v16i8: 178 ; CHECK-LABEL: test_ashr_v16i8:
131 ; CHECK: Sz_ashr_v16i8 179 ; CHECK: sar
180 ; CHECK: sar
181 ; CHECK: sar
182 ; CHECK: sar
183 ; CHECK: sar
184 ; CHECK: sar
185 ; CHECK: sar
186 ; CHECK: sar
187 ; CHECK: sar
188 ; CHECK: sar
189 ; CHECK: sar
190 ; CHECK: sar
191 ; CHECK: sar
192 ; CHECK: sar
193 ; CHECK: sar
194 ; CHECK: sar
132 } 195 }
133 196
134 define <16 x i8> @test_udiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) { 197 define <16 x i8> @test_udiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
135 entry: 198 entry:
136 %res = udiv <16 x i8> %arg0, %arg1 199 %res = udiv <16 x i8> %arg0, %arg1
137 ret <16 x i8> %res 200 ret <16 x i8> %res
138 ; CHECK-LABEL: test_udiv_v16i8: 201 ; CHECK-LABEL: test_udiv_v16i8:
139 ; CHECK: Sz_udiv_v16i8 202 ; CHECK: div
203 ; CHECK: div
204 ; CHECK: div
205 ; CHECK: div
206 ; CHECK: div
207 ; CHECK: div
208 ; CHECK: div
209 ; CHECK: div
210 ; CHECK: div
211 ; CHECK: div
212 ; CHECK: div
213 ; CHECK: div
214 ; CHECK: div
215 ; CHECK: div
216 ; CHECK: div
217 ; CHECK: div
140 } 218 }
141 219
142 define <16 x i8> @test_sdiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) { 220 define <16 x i8> @test_sdiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
143 entry: 221 entry:
144 %res = sdiv <16 x i8> %arg0, %arg1 222 %res = sdiv <16 x i8> %arg0, %arg1
145 ret <16 x i8> %res 223 ret <16 x i8> %res
146 ; CHECK-LABEL: test_sdiv_v16i8: 224 ; CHECK-LABEL: test_sdiv_v16i8:
147 ; CHECK: Sz_sdiv_v16i8 225 ; CHECK: idiv
226 ; CHECK: idiv
227 ; CHECK: idiv
228 ; CHECK: idiv
229 ; CHECK: idiv
230 ; CHECK: idiv
231 ; CHECK: idiv
232 ; CHECK: idiv
233 ; CHECK: idiv
234 ; CHECK: idiv
235 ; CHECK: idiv
236 ; CHECK: idiv
237 ; CHECK: idiv
238 ; CHECK: idiv
239 ; CHECK: idiv
240 ; CHECK: idiv
148 } 241 }
149 242
150 define <16 x i8> @test_urem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) { 243 define <16 x i8> @test_urem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
151 entry: 244 entry:
152 %res = urem <16 x i8> %arg0, %arg1 245 %res = urem <16 x i8> %arg0, %arg1
153 ret <16 x i8> %res 246 ret <16 x i8> %res
154 ; CHECK-LABEL: test_urem_v16i8: 247 ; CHECK-LABEL: test_urem_v16i8:
155 ; CHECK: Sz_urem_v16i8 248 ; CHECK: div
249 ; CHECK: div
250 ; CHECK: div
251 ; CHECK: div
252 ; CHECK: div
253 ; CHECK: div
254 ; CHECK: div
255 ; CHECK: div
256 ; CHECK: div
257 ; CHECK: div
258 ; CHECK: div
259 ; CHECK: div
260 ; CHECK: div
261 ; CHECK: div
262 ; CHECK: div
263 ; CHECK: div
156 } 264 }
157 265
158 define <16 x i8> @test_srem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) { 266 define <16 x i8> @test_srem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
159 entry: 267 entry:
160 %res = srem <16 x i8> %arg0, %arg1 268 %res = srem <16 x i8> %arg0, %arg1
161 ret <16 x i8> %res 269 ret <16 x i8> %res
162 ; CHECK-LABEL: test_srem_v16i8: 270 ; CHECK-LABEL: test_srem_v16i8:
163 ; CHECK: Sz_srem_v16i8 271 ; CHECK: idiv
272 ; CHECK: idiv
273 ; CHECK: idiv
274 ; CHECK: idiv
275 ; CHECK: idiv
276 ; CHECK: idiv
277 ; CHECK: idiv
278 ; CHECK: idiv
279 ; CHECK: idiv
280 ; CHECK: idiv
281 ; CHECK: idiv
282 ; CHECK: idiv
283 ; CHECK: idiv
284 ; CHECK: idiv
285 ; CHECK: idiv
286 ; CHECK: idiv
164 } 287 }
165 288
166 define <8 x i16> @test_add_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { 289 define <8 x i16> @test_add_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
167 entry: 290 entry:
168 %res = add <8 x i16> %arg0, %arg1 291 %res = add <8 x i16> %arg0, %arg1
169 ret <8 x i16> %res 292 ret <8 x i16> %res
170 ; CHECK-LABEL: test_add_v8i16: 293 ; CHECK-LABEL: test_add_v8i16:
171 ; CHECK: paddw 294 ; CHECK: paddw
172 } 295 }
173 296
(...skipping 35 matching lines...) Expand 10 before | Expand all | Expand 10 after
209 ret <8 x i16> %res 332 ret <8 x i16> %res
210 ; CHECK-LABEL: test_mul_v8i16: 333 ; CHECK-LABEL: test_mul_v8i16:
211 ; CHECK: pmullw 334 ; CHECK: pmullw
212 } 335 }
213 336
214 define <8 x i16> @test_shl_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { 337 define <8 x i16> @test_shl_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
215 entry: 338 entry:
216 %res = shl <8 x i16> %arg0, %arg1 339 %res = shl <8 x i16> %arg0, %arg1
217 ret <8 x i16> %res 340 ret <8 x i16> %res
218 ; CHECK-LABEL: test_shl_v8i16: 341 ; CHECK-LABEL: test_shl_v8i16:
219 ; CHECK: Sz_shl_v8i16 342 ; CHECK: shl
343 ; CHECK: shl
344 ; CHECK: shl
345 ; CHECK: shl
346 ; CHECK: shl
347 ; CHECK: shl
348 ; CHECK: shl
349 ; CHECK: shl
220 } 350 }
221 351
222 define <8 x i16> @test_lshr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { 352 define <8 x i16> @test_lshr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
223 entry: 353 entry:
224 %res = lshr <8 x i16> %arg0, %arg1 354 %res = lshr <8 x i16> %arg0, %arg1
225 ret <8 x i16> %res 355 ret <8 x i16> %res
226 ; CHECK-LABEL: test_lshr_v8i16: 356 ; CHECK-LABEL: test_lshr_v8i16:
227 ; CHECK: Sz_lshr_v8i16 357 ; CHECK: shr
358 ; CHECK: shr
359 ; CHECK: shr
360 ; CHECK: shr
361 ; CHECK: shr
362 ; CHECK: shr
363 ; CHECK: shr
364 ; CHECK: shr
228 } 365 }
229 366
230 define <8 x i16> @test_ashr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { 367 define <8 x i16> @test_ashr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
231 entry: 368 entry:
232 %res = ashr <8 x i16> %arg0, %arg1 369 %res = ashr <8 x i16> %arg0, %arg1
233 ret <8 x i16> %res 370 ret <8 x i16> %res
234 ; CHECK-LABEL: test_ashr_v8i16: 371 ; CHECK-LABEL: test_ashr_v8i16:
235 ; CHECK: Sz_ashr_v8i16 372 ; CHECK: sar
373 ; CHECK: sar
374 ; CHECK: sar
375 ; CHECK: sar
376 ; CHECK: sar
377 ; CHECK: sar
378 ; CHECK: sar
379 ; CHECK: sar
236 } 380 }
237 381
238 define <8 x i16> @test_udiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { 382 define <8 x i16> @test_udiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
239 entry: 383 entry:
240 %res = udiv <8 x i16> %arg0, %arg1 384 %res = udiv <8 x i16> %arg0, %arg1
241 ret <8 x i16> %res 385 ret <8 x i16> %res
242 ; CHECK-LABEL: test_udiv_v8i16: 386 ; CHECK-LABEL: test_udiv_v8i16:
243 ; CHECK: Sz_udiv_v8i16 387 ; CHECK: div
388 ; CHECK: div
389 ; CHECK: div
390 ; CHECK: div
391 ; CHECK: div
392 ; CHECK: div
393 ; CHECK: div
394 ; CHECK: div
244 } 395 }
245 396
246 define <8 x i16> @test_sdiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { 397 define <8 x i16> @test_sdiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
247 entry: 398 entry:
248 %res = sdiv <8 x i16> %arg0, %arg1 399 %res = sdiv <8 x i16> %arg0, %arg1
249 ret <8 x i16> %res 400 ret <8 x i16> %res
250 ; CHECK-LABEL: test_sdiv_v8i16: 401 ; CHECK-LABEL: test_sdiv_v8i16:
251 ; CHECK: Sz_sdiv_v8i16 402 ; CHECK: idiv
403 ; CHECK: idiv
404 ; CHECK: idiv
405 ; CHECK: idiv
406 ; CHECK: idiv
407 ; CHECK: idiv
408 ; CHECK: idiv
409 ; CHECK: idiv
252 } 410 }
253 411
254 define <8 x i16> @test_urem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { 412 define <8 x i16> @test_urem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
255 entry: 413 entry:
256 %res = urem <8 x i16> %arg0, %arg1 414 %res = urem <8 x i16> %arg0, %arg1
257 ret <8 x i16> %res 415 ret <8 x i16> %res
258 ; CHECK-LABEL: test_urem_v8i16: 416 ; CHECK-LABEL: test_urem_v8i16:
259 ; CHECK: Sz_urem_v8i16 417 ; CHECK: div
418 ; CHECK: div
419 ; CHECK: div
420 ; CHECK: div
421 ; CHECK: div
422 ; CHECK: div
423 ; CHECK: div
424 ; CHECK: div
260 } 425 }
261 426
262 define <8 x i16> @test_srem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { 427 define <8 x i16> @test_srem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
263 entry: 428 entry:
264 %res = srem <8 x i16> %arg0, %arg1 429 %res = srem <8 x i16> %arg0, %arg1
265 ret <8 x i16> %res 430 ret <8 x i16> %res
266 ; CHECK-LABEL: test_srem_v8i16: 431 ; CHECK-LABEL: test_srem_v8i16:
267 ; CHECK: Sz_srem_v8i16 432 ; CHECK: idiv
433 ; CHECK: idiv
434 ; CHECK: idiv
435 ; CHECK: idiv
436 ; CHECK: idiv
437 ; CHECK: idiv
438 ; CHECK: idiv
439 ; CHECK: idiv
268 } 440 }
269 441
270 define <4 x i32> @test_add_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { 442 define <4 x i32> @test_add_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
271 entry: 443 entry:
272 %res = add <4 x i32> %arg0, %arg1 444 %res = add <4 x i32> %arg0, %arg1
273 ret <4 x i32> %res 445 ret <4 x i32> %res
274 ; CHECK-LABEL: test_add_v4i32: 446 ; CHECK-LABEL: test_add_v4i32:
275 ; CHECK: paddd 447 ; CHECK: paddd
276 } 448 }
277 449
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
317 ; 489 ;
318 ; SSE41-LABEL: test_mul_v4i32: 490 ; SSE41-LABEL: test_mul_v4i32:
319 ; SSE41: pmulld 491 ; SSE41: pmulld
320 } 492 }
321 493
322 define <4 x i32> @test_shl_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { 494 define <4 x i32> @test_shl_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
323 entry: 495 entry:
324 %res = shl <4 x i32> %arg0, %arg1 496 %res = shl <4 x i32> %arg0, %arg1
325 ret <4 x i32> %res 497 ret <4 x i32> %res
326 ; CHECK-LABEL: test_shl_v4i32: 498 ; CHECK-LABEL: test_shl_v4i32:
327 ; CHECK: Sz_shl_v4i32 499 ; CHECK: shl
500 ; CHECK: shl
501 ; CHECK: shl
502 ; CHECK: shl
328 503
329 ; This line is to ensure that pmulld is generated in test_mul_v4i32 above. 504 ; This line is to ensure that pmulld is generated in test_mul_v4i32 above.
330 ; SSE41-LABEL: test_shl_v4i32: 505 ; SSE41-LABEL: test_shl_v4i32:
331 } 506 }
332 507
333 define <4 x i32> @test_lshr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { 508 define <4 x i32> @test_lshr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
334 entry: 509 entry:
335 %res = lshr <4 x i32> %arg0, %arg1 510 %res = lshr <4 x i32> %arg0, %arg1
336 ret <4 x i32> %res 511 ret <4 x i32> %res
337 ; CHECK-LABEL: test_lshr_v4i32: 512 ; CHECK-LABEL: test_lshr_v4i32:
338 ; CHECK: Sz_lshr_v4i32 513 ; CHECK: shr
514 ; CHECK: shr
515 ; CHECK: shr
516 ; CHECK: shr
339 } 517 }
340 518
341 define <4 x i32> @test_ashr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { 519 define <4 x i32> @test_ashr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
342 entry: 520 entry:
343 %res = ashr <4 x i32> %arg0, %arg1 521 %res = ashr <4 x i32> %arg0, %arg1
344 ret <4 x i32> %res 522 ret <4 x i32> %res
345 ; CHECK-LABEL: test_ashr_v4i32: 523 ; CHECK-LABEL: test_ashr_v4i32:
346 ; CHECK: Sz_ashr_v4i32 524 ; CHECK: sar
525 ; CHECK: sar
526 ; CHECK: sar
527 ; CHECK: sar
347 } 528 }
348 529
349 define <4 x i32> @test_udiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { 530 define <4 x i32> @test_udiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
350 entry: 531 entry:
351 %res = udiv <4 x i32> %arg0, %arg1 532 %res = udiv <4 x i32> %arg0, %arg1
352 ret <4 x i32> %res 533 ret <4 x i32> %res
353 ; CHECK-LABEL: test_udiv_v4i32: 534 ; CHECK-LABEL: test_udiv_v4i32:
354 ; CHECK: Sz_udiv_v4i32 535 ; CHECK: div
536 ; CHECK: div
537 ; CHECK: div
538 ; CHECK: div
355 } 539 }
356 540
357 define <4 x i32> @test_sdiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { 541 define <4 x i32> @test_sdiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
358 entry: 542 entry:
359 %res = sdiv <4 x i32> %arg0, %arg1 543 %res = sdiv <4 x i32> %arg0, %arg1
360 ret <4 x i32> %res 544 ret <4 x i32> %res
361 ; CHECK-LABEL: test_sdiv_v4i32: 545 ; CHECK-LABEL: test_sdiv_v4i32:
362 ; CHECK: Sz_sdiv_v4i32 546 ; CHECK: idiv
547 ; CHECK: idiv
548 ; CHECK: idiv
549 ; CHECK: idiv
363 } 550 }
364 551
365 define <4 x i32> @test_urem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { 552 define <4 x i32> @test_urem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
366 entry: 553 entry:
367 %res = urem <4 x i32> %arg0, %arg1 554 %res = urem <4 x i32> %arg0, %arg1
368 ret <4 x i32> %res 555 ret <4 x i32> %res
369 ; CHECK-LABEL: test_urem_v4i32: 556 ; CHECK-LABEL: test_urem_v4i32:
370 ; CHECK: Sz_urem_v4i32 557 ; CHECK: div
558 ; CHECK: div
559 ; CHECK: div
560 ; CHECK: div
371 } 561 }
372 562
373 define <4 x i32> @test_srem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { 563 define <4 x i32> @test_srem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
374 entry: 564 entry:
375 %res = srem <4 x i32> %arg0, %arg1 565 %res = srem <4 x i32> %arg0, %arg1
376 ret <4 x i32> %res 566 ret <4 x i32> %res
377 ; CHECK-LABEL: test_srem_v4i32: 567 ; CHECK-LABEL: test_srem_v4i32:
378 ; CHECK: Sz_srem_v4i32 568 ; CHECK: idiv
569 ; CHECK: idiv
570 ; CHECK: idiv
571 ; CHECK: idiv
379 } 572 }
380 573
381 ; ERRORS-NOT: ICE translation error 574 ; ERRORS-NOT: ICE translation error
382 ; DUMP-NOT: SZ 575 ; DUMP-NOT: SZ
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