OLD | NEW |
1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <list> | 5 #include <list> |
6 | 6 |
7 #include "test/cctest/compiler/instruction-selector-tester.h" | 7 #include "test/cctest/compiler/instruction-selector-tester.h" |
8 #include "test/cctest/compiler/value-helper.h" | 8 #include "test/cctest/compiler/value-helper.h" |
9 | 9 |
10 using namespace v8::internal; | 10 using namespace v8::internal; |
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112 InstructionSelectorTester m; | 112 InstructionSelectorTester m; |
113 m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Parameter(1))); | 113 m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Parameter(1))); |
114 m.SelectInstructions(); | 114 m.SelectInstructions(); |
115 CHECK_EQ(1, m.code.size()); | 115 CHECK_EQ(1, m.code.size()); |
116 CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode()); | 116 CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode()); |
117 CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode()); | 117 CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode()); |
118 } | 118 } |
119 } | 119 } |
120 | 120 |
121 | 121 |
| 122 TEST(InstructionSelectorDPIImm) { |
| 123 DPIs dpis; |
| 124 Immediates immediates; |
| 125 for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) { |
| 126 DPI dpi = *i; |
| 127 for (Immediates::const_iterator j = immediates.begin(); |
| 128 j != immediates.end(); ++j) { |
| 129 int32_t imm = *j; |
| 130 { |
| 131 InstructionSelectorTester m; |
| 132 m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Int32Constant(imm))); |
| 133 m.SelectInstructions(); |
| 134 CHECK_EQ(1, m.code.size()); |
| 135 CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode()); |
| 136 CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode()); |
| 137 } |
| 138 { |
| 139 InstructionSelectorTester m; |
| 140 m.Return(m.NewNode(dpi.op, m.Int32Constant(imm), m.Parameter(0))); |
| 141 m.SelectInstructions(); |
| 142 CHECK_EQ(1, m.code.size()); |
| 143 CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode()); |
| 144 CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode()); |
| 145 } |
| 146 } |
| 147 } |
| 148 } |
| 149 |
| 150 |
122 TEST(InstructionSelectorDPIAndShiftP) { | 151 TEST(InstructionSelectorDPIAndShiftP) { |
123 DPIs dpis; | 152 DPIs dpis; |
124 Shifts shifts; | 153 Shifts shifts; |
125 for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) { | 154 for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) { |
126 DPI dpi = *i; | 155 DPI dpi = *i; |
127 for (Shifts::const_iterator j = shifts.begin(); j != shifts.end(); ++j) { | 156 for (Shifts::const_iterator j = shifts.begin(); j != shifts.end(); ++j) { |
128 Shift shift = *j; | 157 Shift shift = *j; |
129 { | 158 { |
130 InstructionSelectorTester m; | 159 InstructionSelectorTester m; |
131 m.Return( | 160 m.Return( |
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865 InstructionSelectorTester m; | 894 InstructionSelectorTester m; |
866 m.Return(m.Int32Mul(m.Int32Constant((1 << k) - 1), m.Parameter(0))); | 895 m.Return(m.Int32Mul(m.Int32Constant((1 << k) - 1), m.Parameter(0))); |
867 m.SelectInstructions(); | 896 m.SelectInstructions(); |
868 CHECK_EQ(1, m.code.size()); | 897 CHECK_EQ(1, m.code.size()); |
869 CHECK_EQ(kArmRsb, m.code[0]->arch_opcode()); | 898 CHECK_EQ(kArmRsb, m.code[0]->arch_opcode()); |
870 CHECK_EQ(kMode_Operand2_R_LSL_I, m.code[0]->addressing_mode()); | 899 CHECK_EQ(kMode_Operand2_R_LSL_I, m.code[0]->addressing_mode()); |
871 } | 900 } |
872 } | 901 } |
873 | 902 |
874 | 903 |
875 // The following tests depend on the exact CPU features available, which we do | 904 TEST(InstructionSelectorWord32AndImm_ARMv7) { |
876 // only fully control in a simulator build. | |
877 #ifdef USE_SIMULATOR | |
878 | |
879 TEST(InstructionSelectorDPIImm_ARMv7AndVFP3Disabled) { | |
880 i::FLAG_enable_armv7 = false; | |
881 i::FLAG_enable_vfp3 = false; | |
882 DPIs dpis; | |
883 Immediates immediates; | |
884 for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) { | |
885 DPI dpi = *i; | |
886 for (Immediates::const_iterator j = immediates.begin(); | |
887 j != immediates.end(); ++j) { | |
888 int32_t imm = *j; | |
889 { | |
890 InstructionSelectorTester m; | |
891 m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Int32Constant(imm))); | |
892 m.SelectInstructions(); | |
893 CHECK_EQ(1, m.code.size()); | |
894 CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode()); | |
895 CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode()); | |
896 } | |
897 { | |
898 InstructionSelectorTester m; | |
899 m.Return(m.NewNode(dpi.op, m.Int32Constant(imm), m.Parameter(0))); | |
900 m.SelectInstructions(); | |
901 CHECK_EQ(1, m.code.size()); | |
902 CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode()); | |
903 CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode()); | |
904 } | |
905 } | |
906 } | |
907 } | |
908 | |
909 | |
910 TEST(InstructionSelectorWord32AndImm_ARMv7Enabled) { | |
911 i::FLAG_enable_armv7 = true; | |
912 for (uint32_t width = 1; width <= 32; ++width) { | 905 for (uint32_t width = 1; width <= 32; ++width) { |
913 InstructionSelectorTester m; | 906 InstructionSelectorTester m; |
914 m.Return(m.Word32And(m.Parameter(0), | 907 m.Return(m.Word32And(m.Parameter(0), |
915 m.Int32Constant(0xffffffffu >> (32 - width)))); | 908 m.Int32Constant(0xffffffffu >> (32 - width)))); |
916 m.SelectInstructions(); | 909 m.SelectInstructions(ARMv7); |
917 CHECK_EQ(1, m.code.size()); | 910 CHECK_EQ(1, m.code.size()); |
918 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); | 911 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); |
919 CHECK_EQ(3, m.code[0]->InputCount()); | 912 CHECK_EQ(3, m.code[0]->InputCount()); |
920 CHECK_EQ(0, m.ToInt32(m.code[0]->InputAt(1))); | 913 CHECK_EQ(0, m.ToInt32(m.code[0]->InputAt(1))); |
921 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); | 914 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); |
922 } | 915 } |
923 for (uint32_t lsb = 0; lsb <= 31; ++lsb) { | 916 for (uint32_t lsb = 0; lsb <= 31; ++lsb) { |
924 for (uint32_t width = 1; width < 32 - lsb; ++width) { | 917 for (uint32_t width = 1; width < 32 - lsb; ++width) { |
925 uint32_t msk = ~((0xffffffffu >> (32 - width)) << lsb); | 918 uint32_t msk = ~((0xffffffffu >> (32 - width)) << lsb); |
926 InstructionSelectorTester m; | 919 InstructionSelectorTester m; |
927 m.Return(m.Word32And(m.Parameter(0), m.Int32Constant(msk))); | 920 m.Return(m.Word32And(m.Parameter(0), m.Int32Constant(msk))); |
928 m.SelectInstructions(); | 921 m.SelectInstructions(ARMv7); |
929 CHECK_EQ(1, m.code.size()); | 922 CHECK_EQ(1, m.code.size()); |
930 CHECK_EQ(kArmBfc, m.code[0]->arch_opcode()); | 923 CHECK_EQ(kArmBfc, m.code[0]->arch_opcode()); |
931 CHECK_EQ(1, m.code[0]->OutputCount()); | 924 CHECK_EQ(1, m.code[0]->OutputCount()); |
932 CHECK(UnallocatedOperand::cast(m.code[0]->Output()) | 925 CHECK(UnallocatedOperand::cast(m.code[0]->Output()) |
933 ->HasSameAsInputPolicy()); | 926 ->HasSameAsInputPolicy()); |
934 CHECK_EQ(3, m.code[0]->InputCount()); | 927 CHECK_EQ(3, m.code[0]->InputCount()); |
935 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); | 928 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); |
936 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); | 929 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); |
937 } | 930 } |
938 } | 931 } |
939 } | 932 } |
940 | 933 |
941 | 934 |
942 TEST(InstructionSelectorWord32AndAndWord32ShrImm_ARMv7Enabled) { | 935 TEST(InstructionSelectorWord32AndAndWord32ShrImm_ARMv7) { |
943 i::FLAG_enable_armv7 = true; | |
944 for (uint32_t lsb = 0; lsb <= 31; ++lsb) { | 936 for (uint32_t lsb = 0; lsb <= 31; ++lsb) { |
945 for (uint32_t width = 1; width <= 32 - lsb; ++width) { | 937 for (uint32_t width = 1; width <= 32 - lsb; ++width) { |
946 { | 938 { |
947 InstructionSelectorTester m; | 939 InstructionSelectorTester m; |
948 m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb)), | 940 m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb)), |
949 m.Int32Constant(0xffffffffu >> (32 - width)))); | 941 m.Int32Constant(0xffffffffu >> (32 - width)))); |
950 m.SelectInstructions(); | 942 m.SelectInstructions(ARMv7); |
951 CHECK_EQ(1, m.code.size()); | 943 CHECK_EQ(1, m.code.size()); |
952 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); | 944 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); |
953 CHECK_EQ(3, m.code[0]->InputCount()); | 945 CHECK_EQ(3, m.code[0]->InputCount()); |
954 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); | 946 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); |
955 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); | 947 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); |
956 } | 948 } |
957 { | 949 { |
958 InstructionSelectorTester m; | 950 InstructionSelectorTester m; |
959 m.Return( | 951 m.Return( |
960 m.Word32And(m.Int32Constant(0xffffffffu >> (32 - width)), | 952 m.Word32And(m.Int32Constant(0xffffffffu >> (32 - width)), |
961 m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb)))); | 953 m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb)))); |
962 m.SelectInstructions(); | 954 m.SelectInstructions(ARMv7); |
963 CHECK_EQ(1, m.code.size()); | 955 CHECK_EQ(1, m.code.size()); |
964 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); | 956 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); |
965 CHECK_EQ(3, m.code[0]->InputCount()); | 957 CHECK_EQ(3, m.code[0]->InputCount()); |
966 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); | 958 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); |
967 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); | 959 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); |
968 } | 960 } |
969 } | 961 } |
970 } | 962 } |
971 } | 963 } |
972 | 964 |
973 | 965 |
974 TEST(InstructionSelectorWord32ShrAndWord32AndImm_ARMv7Enabled) { | 966 TEST(InstructionSelectorWord32ShrAndWord32AndImm_ARMv7) { |
975 i::FLAG_enable_armv7 = true; | |
976 for (uint32_t lsb = 0; lsb <= 31; ++lsb) { | 967 for (uint32_t lsb = 0; lsb <= 31; ++lsb) { |
977 for (uint32_t width = 1; width <= 32 - lsb; ++width) { | 968 for (uint32_t width = 1; width <= 32 - lsb; ++width) { |
978 uint32_t max = 1 << lsb; | 969 uint32_t max = 1 << lsb; |
979 if (max > static_cast<uint32_t>(kMaxInt)) max -= 1; | 970 if (max > static_cast<uint32_t>(kMaxInt)) max -= 1; |
980 uint32_t jnk = CcTest::random_number_generator()->NextInt(max); | 971 uint32_t jnk = CcTest::random_number_generator()->NextInt(max); |
981 uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk; | 972 uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk; |
982 { | 973 { |
983 InstructionSelectorTester m; | 974 InstructionSelectorTester m; |
984 m.Return(m.Word32Shr(m.Word32And(m.Parameter(0), m.Int32Constant(msk)), | 975 m.Return(m.Word32Shr(m.Word32And(m.Parameter(0), m.Int32Constant(msk)), |
985 m.Int32Constant(lsb))); | 976 m.Int32Constant(lsb))); |
986 m.SelectInstructions(); | 977 m.SelectInstructions(ARMv7); |
987 CHECK_EQ(1, m.code.size()); | 978 CHECK_EQ(1, m.code.size()); |
988 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); | 979 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); |
989 CHECK_EQ(3, m.code[0]->InputCount()); | 980 CHECK_EQ(3, m.code[0]->InputCount()); |
990 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); | 981 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); |
991 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); | 982 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); |
992 } | 983 } |
993 { | 984 { |
994 InstructionSelectorTester m; | 985 InstructionSelectorTester m; |
995 m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(msk), m.Parameter(0)), | 986 m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(msk), m.Parameter(0)), |
996 m.Int32Constant(lsb))); | 987 m.Int32Constant(lsb))); |
997 m.SelectInstructions(); | 988 m.SelectInstructions(ARMv7); |
998 CHECK_EQ(1, m.code.size()); | 989 CHECK_EQ(1, m.code.size()); |
999 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); | 990 CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode()); |
1000 CHECK_EQ(3, m.code[0]->InputCount()); | 991 CHECK_EQ(3, m.code[0]->InputCount()); |
1001 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); | 992 CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1))); |
1002 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); | 993 CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2))); |
1003 } | 994 } |
1004 } | 995 } |
1005 } | 996 } |
1006 } | 997 } |
1007 | 998 |
1008 | 999 |
1009 TEST(InstructionSelectorInt32SubAndInt32MulP_MlsEnabled) { | 1000 TEST(InstructionSelectorInt32SubAndInt32MulP) { |
1010 i::FLAG_enable_mls = true; | |
1011 InstructionSelectorTester m; | 1001 InstructionSelectorTester m; |
1012 m.Return( | 1002 m.Return( |
1013 m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2)))); | 1003 m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2)))); |
1014 m.SelectInstructions(); | |
1015 CHECK_EQ(1, m.code.size()); | |
1016 CHECK_EQ(kArmMls, m.code[0]->arch_opcode()); | |
1017 } | |
1018 | |
1019 | |
1020 TEST(InstructionSelectorInt32SubAndInt32MulP_MlsDisabled) { | |
1021 i::FLAG_enable_mls = false; | |
1022 InstructionSelectorTester m; | |
1023 m.Return( | |
1024 m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2)))); | |
1025 m.SelectInstructions(); | 1004 m.SelectInstructions(); |
1026 CHECK_EQ(2, m.code.size()); | 1005 CHECK_EQ(2, m.code.size()); |
1027 CHECK_EQ(kArmMul, m.code[0]->arch_opcode()); | 1006 CHECK_EQ(kArmMul, m.code[0]->arch_opcode()); |
1028 CHECK_EQ(1, m.code[0]->OutputCount()); | 1007 CHECK_EQ(1, m.code[0]->OutputCount()); |
1029 CHECK_EQ(kArmSub, m.code[1]->arch_opcode()); | 1008 CHECK_EQ(kArmSub, m.code[1]->arch_opcode()); |
1030 CHECK_EQ(2, m.code[1]->InputCount()); | 1009 CHECK_EQ(2, m.code[1]->InputCount()); |
1031 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(1)); | 1010 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(1)); |
1032 } | 1011 } |
1033 | 1012 |
1034 | 1013 |
1035 TEST(InstructionSelectorInt32DivP_ARMv7AndSudivEnabled) { | 1014 TEST(InstructionSelectorInt32SubAndInt32MulP_MLS) { |
1036 i::FLAG_enable_armv7 = true; | 1015 InstructionSelectorTester m; |
1037 i::FLAG_enable_sudiv = true; | 1016 m.Return( |
| 1017 m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2)))); |
| 1018 m.SelectInstructions(MLS); |
| 1019 CHECK_EQ(1, m.code.size()); |
| 1020 CHECK_EQ(kArmMls, m.code[0]->arch_opcode()); |
| 1021 } |
| 1022 |
| 1023 |
| 1024 TEST(InstructionSelectorInt32DivP) { |
1038 InstructionSelectorTester m; | 1025 InstructionSelectorTester m; |
1039 m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1))); | 1026 m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1))); |
1040 m.SelectInstructions(); | 1027 m.SelectInstructions(); |
1041 CHECK_EQ(1, m.code.size()); | |
1042 CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode()); | |
1043 } | |
1044 | |
1045 | |
1046 TEST(InstructionSelectorInt32DivP_SudivDisabled) { | |
1047 i::FLAG_enable_sudiv = false; | |
1048 InstructionSelectorTester m; | |
1049 m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1))); | |
1050 m.SelectInstructions(); | |
1051 CHECK_EQ(4, m.code.size()); | 1028 CHECK_EQ(4, m.code.size()); |
1052 CHECK_EQ(kArmVcvtF64S32, m.code[0]->arch_opcode()); | 1029 CHECK_EQ(kArmVcvtF64S32, m.code[0]->arch_opcode()); |
1053 CHECK_EQ(1, m.code[0]->OutputCount()); | 1030 CHECK_EQ(1, m.code[0]->OutputCount()); |
1054 CHECK_EQ(kArmVcvtF64S32, m.code[1]->arch_opcode()); | 1031 CHECK_EQ(kArmVcvtF64S32, m.code[1]->arch_opcode()); |
1055 CHECK_EQ(1, m.code[1]->OutputCount()); | 1032 CHECK_EQ(1, m.code[1]->OutputCount()); |
1056 CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode()); | 1033 CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode()); |
1057 CHECK_EQ(2, m.code[2]->InputCount()); | 1034 CHECK_EQ(2, m.code[2]->InputCount()); |
1058 CHECK_EQ(1, m.code[2]->OutputCount()); | 1035 CHECK_EQ(1, m.code[2]->OutputCount()); |
1059 CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0)); | 1036 CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0)); |
1060 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); | 1037 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); |
1061 CHECK_EQ(kArmVcvtS32F64, m.code[3]->arch_opcode()); | 1038 CHECK_EQ(kArmVcvtS32F64, m.code[3]->arch_opcode()); |
1062 CHECK_EQ(1, m.code[3]->InputCount()); | 1039 CHECK_EQ(1, m.code[3]->InputCount()); |
1063 CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0)); | 1040 CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0)); |
1064 } | 1041 } |
1065 | 1042 |
1066 | 1043 |
1067 TEST(InstructionSelectorInt32UDivP_ARMv7AndSudivEnabled) { | 1044 TEST(InstructionSelectorInt32DivP_SUDIV) { |
1068 i::FLAG_enable_armv7 = true; | 1045 InstructionSelectorTester m; |
1069 i::FLAG_enable_sudiv = true; | 1046 m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1))); |
| 1047 m.SelectInstructions(SUDIV); |
| 1048 CHECK_EQ(1, m.code.size()); |
| 1049 CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode()); |
| 1050 } |
| 1051 |
| 1052 |
| 1053 TEST(InstructionSelectorInt32UDivP) { |
1070 InstructionSelectorTester m; | 1054 InstructionSelectorTester m; |
1071 m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1))); | 1055 m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1))); |
1072 m.SelectInstructions(); | 1056 m.SelectInstructions(); |
1073 CHECK_EQ(1, m.code.size()); | |
1074 CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode()); | |
1075 } | |
1076 | |
1077 | |
1078 TEST(InstructionSelectorInt32UDivP_SudivDisabled) { | |
1079 i::FLAG_enable_sudiv = false; | |
1080 InstructionSelectorTester m; | |
1081 m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1))); | |
1082 m.SelectInstructions(); | |
1083 CHECK_EQ(4, m.code.size()); | 1057 CHECK_EQ(4, m.code.size()); |
1084 CHECK_EQ(kArmVcvtF64U32, m.code[0]->arch_opcode()); | 1058 CHECK_EQ(kArmVcvtF64U32, m.code[0]->arch_opcode()); |
1085 CHECK_EQ(1, m.code[0]->OutputCount()); | 1059 CHECK_EQ(1, m.code[0]->OutputCount()); |
1086 CHECK_EQ(kArmVcvtF64U32, m.code[1]->arch_opcode()); | 1060 CHECK_EQ(kArmVcvtF64U32, m.code[1]->arch_opcode()); |
1087 CHECK_EQ(1, m.code[1]->OutputCount()); | 1061 CHECK_EQ(1, m.code[1]->OutputCount()); |
1088 CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode()); | 1062 CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode()); |
1089 CHECK_EQ(2, m.code[2]->InputCount()); | 1063 CHECK_EQ(2, m.code[2]->InputCount()); |
1090 CHECK_EQ(1, m.code[2]->OutputCount()); | 1064 CHECK_EQ(1, m.code[2]->OutputCount()); |
1091 CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0)); | 1065 CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0)); |
1092 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); | 1066 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); |
1093 CHECK_EQ(kArmVcvtU32F64, m.code[3]->arch_opcode()); | 1067 CHECK_EQ(kArmVcvtU32F64, m.code[3]->arch_opcode()); |
1094 CHECK_EQ(1, m.code[3]->InputCount()); | 1068 CHECK_EQ(1, m.code[3]->InputCount()); |
1095 CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0)); | 1069 CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0)); |
1096 } | 1070 } |
1097 | 1071 |
1098 | 1072 |
1099 TEST(InstructionSelectorInt32ModP_ARMv7AndMlsAndSudivEnabled) { | 1073 TEST(InstructionSelectorInt32UDivP_SUDIV) { |
1100 i::FLAG_enable_armv7 = true; | 1074 InstructionSelectorTester m; |
1101 i::FLAG_enable_mls = true; | 1075 m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1))); |
1102 i::FLAG_enable_sudiv = true; | 1076 m.SelectInstructions(SUDIV); |
| 1077 CHECK_EQ(1, m.code.size()); |
| 1078 CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode()); |
| 1079 } |
| 1080 |
| 1081 |
| 1082 TEST(InstructionSelectorInt32ModP) { |
1103 InstructionSelectorTester m; | 1083 InstructionSelectorTester m; |
1104 m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1))); | 1084 m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1))); |
1105 m.SelectInstructions(); | 1085 m.SelectInstructions(); |
1106 CHECK_EQ(2, m.code.size()); | |
1107 CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode()); | |
1108 CHECK_EQ(1, m.code[0]->OutputCount()); | |
1109 CHECK_EQ(2, m.code[0]->InputCount()); | |
1110 CHECK_EQ(kArmMls, m.code[1]->arch_opcode()); | |
1111 CHECK_EQ(1, m.code[1]->OutputCount()); | |
1112 CHECK_EQ(3, m.code[1]->InputCount()); | |
1113 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0)); | |
1114 CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1)); | |
1115 CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2)); | |
1116 } | |
1117 | |
1118 | |
1119 TEST(InstructionSelectorInt32ModP_ARMv7AndSudivEnabled) { | |
1120 i::FLAG_enable_armv7 = true; | |
1121 i::FLAG_enable_mls = false; | |
1122 i::FLAG_enable_sudiv = true; | |
1123 InstructionSelectorTester m; | |
1124 m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1))); | |
1125 m.SelectInstructions(); | |
1126 CHECK_EQ(3, m.code.size()); | |
1127 CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode()); | |
1128 CHECK_EQ(1, m.code[0]->OutputCount()); | |
1129 CHECK_EQ(2, m.code[0]->InputCount()); | |
1130 CHECK_EQ(kArmMul, m.code[1]->arch_opcode()); | |
1131 CHECK_EQ(1, m.code[1]->OutputCount()); | |
1132 CHECK_EQ(2, m.code[1]->InputCount()); | |
1133 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0)); | |
1134 CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1)); | |
1135 CHECK_EQ(kArmSub, m.code[2]->arch_opcode()); | |
1136 CHECK_EQ(1, m.code[2]->OutputCount()); | |
1137 CHECK_EQ(2, m.code[2]->InputCount()); | |
1138 CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0)); | |
1139 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); | |
1140 } | |
1141 | |
1142 | |
1143 TEST(InstructionSelectorInt32ModP_ARMv7AndMlsAndSudivDisabled) { | |
1144 i::FLAG_enable_armv7 = false; | |
1145 i::FLAG_enable_mls = false; | |
1146 i::FLAG_enable_sudiv = false; | |
1147 InstructionSelectorTester m; | |
1148 m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1))); | |
1149 m.SelectInstructions(); | |
1150 CHECK_EQ(6, m.code.size()); | 1086 CHECK_EQ(6, m.code.size()); |
1151 CHECK_EQ(kArmVcvtF64S32, m.code[0]->arch_opcode()); | 1087 CHECK_EQ(kArmVcvtF64S32, m.code[0]->arch_opcode()); |
1152 CHECK_EQ(1, m.code[0]->OutputCount()); | 1088 CHECK_EQ(1, m.code[0]->OutputCount()); |
1153 CHECK_EQ(kArmVcvtF64S32, m.code[1]->arch_opcode()); | 1089 CHECK_EQ(kArmVcvtF64S32, m.code[1]->arch_opcode()); |
1154 CHECK_EQ(1, m.code[1]->OutputCount()); | 1090 CHECK_EQ(1, m.code[1]->OutputCount()); |
1155 CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode()); | 1091 CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode()); |
1156 CHECK_EQ(2, m.code[2]->InputCount()); | 1092 CHECK_EQ(2, m.code[2]->InputCount()); |
1157 CHECK_EQ(1, m.code[2]->OutputCount()); | 1093 CHECK_EQ(1, m.code[2]->OutputCount()); |
1158 CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0)); | 1094 CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0)); |
1159 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); | 1095 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); |
1160 CHECK_EQ(kArmVcvtS32F64, m.code[3]->arch_opcode()); | 1096 CHECK_EQ(kArmVcvtS32F64, m.code[3]->arch_opcode()); |
1161 CHECK_EQ(1, m.code[3]->InputCount()); | 1097 CHECK_EQ(1, m.code[3]->InputCount()); |
1162 CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0)); | 1098 CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0)); |
1163 CHECK_EQ(kArmMul, m.code[4]->arch_opcode()); | 1099 CHECK_EQ(kArmMul, m.code[4]->arch_opcode()); |
1164 CHECK_EQ(1, m.code[4]->OutputCount()); | 1100 CHECK_EQ(1, m.code[4]->OutputCount()); |
1165 CHECK_EQ(2, m.code[4]->InputCount()); | 1101 CHECK_EQ(2, m.code[4]->InputCount()); |
1166 CheckSameVreg(m.code[3]->Output(), m.code[4]->InputAt(0)); | 1102 CheckSameVreg(m.code[3]->Output(), m.code[4]->InputAt(0)); |
1167 CheckSameVreg(m.code[1]->InputAt(0), m.code[4]->InputAt(1)); | 1103 CheckSameVreg(m.code[1]->InputAt(0), m.code[4]->InputAt(1)); |
1168 CHECK_EQ(kArmSub, m.code[5]->arch_opcode()); | 1104 CHECK_EQ(kArmSub, m.code[5]->arch_opcode()); |
1169 CHECK_EQ(1, m.code[5]->OutputCount()); | 1105 CHECK_EQ(1, m.code[5]->OutputCount()); |
1170 CHECK_EQ(2, m.code[5]->InputCount()); | 1106 CHECK_EQ(2, m.code[5]->InputCount()); |
1171 CheckSameVreg(m.code[0]->InputAt(0), m.code[5]->InputAt(0)); | 1107 CheckSameVreg(m.code[0]->InputAt(0), m.code[5]->InputAt(0)); |
1172 CheckSameVreg(m.code[4]->Output(), m.code[5]->InputAt(1)); | 1108 CheckSameVreg(m.code[4]->Output(), m.code[5]->InputAt(1)); |
1173 } | 1109 } |
1174 | 1110 |
1175 | 1111 |
1176 TEST(InstructionSelectorInt32UModP_ARMv7AndMlsAndSudivEnabled) { | 1112 TEST(InstructionSelectorInt32ModP_SUDIV) { |
1177 i::FLAG_enable_armv7 = true; | |
1178 i::FLAG_enable_mls = true; | |
1179 i::FLAG_enable_sudiv = true; | |
1180 InstructionSelectorTester m; | 1113 InstructionSelectorTester m; |
1181 m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1))); | 1114 m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1))); |
1182 m.SelectInstructions(); | 1115 m.SelectInstructions(SUDIV); |
1183 CHECK_EQ(2, m.code.size()); | |
1184 CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode()); | |
1185 CHECK_EQ(1, m.code[0]->OutputCount()); | |
1186 CHECK_EQ(2, m.code[0]->InputCount()); | |
1187 CHECK_EQ(kArmMls, m.code[1]->arch_opcode()); | |
1188 CHECK_EQ(1, m.code[1]->OutputCount()); | |
1189 CHECK_EQ(3, m.code[1]->InputCount()); | |
1190 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0)); | |
1191 CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1)); | |
1192 CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2)); | |
1193 } | |
1194 | |
1195 | |
1196 TEST(InstructionSelectorInt32UModP_ARMv7AndSudivEnabled) { | |
1197 i::FLAG_enable_armv7 = true; | |
1198 i::FLAG_enable_mls = false; | |
1199 i::FLAG_enable_sudiv = true; | |
1200 InstructionSelectorTester m; | |
1201 m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1))); | |
1202 m.SelectInstructions(); | |
1203 CHECK_EQ(3, m.code.size()); | 1116 CHECK_EQ(3, m.code.size()); |
1204 CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode()); | 1117 CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode()); |
1205 CHECK_EQ(1, m.code[0]->OutputCount()); | 1118 CHECK_EQ(1, m.code[0]->OutputCount()); |
1206 CHECK_EQ(2, m.code[0]->InputCount()); | 1119 CHECK_EQ(2, m.code[0]->InputCount()); |
1207 CHECK_EQ(kArmMul, m.code[1]->arch_opcode()); | 1120 CHECK_EQ(kArmMul, m.code[1]->arch_opcode()); |
1208 CHECK_EQ(1, m.code[1]->OutputCount()); | 1121 CHECK_EQ(1, m.code[1]->OutputCount()); |
1209 CHECK_EQ(2, m.code[1]->InputCount()); | 1122 CHECK_EQ(2, m.code[1]->InputCount()); |
1210 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0)); | 1123 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0)); |
1211 CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1)); | 1124 CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1)); |
1212 CHECK_EQ(kArmSub, m.code[2]->arch_opcode()); | 1125 CHECK_EQ(kArmSub, m.code[2]->arch_opcode()); |
1213 CHECK_EQ(1, m.code[2]->OutputCount()); | 1126 CHECK_EQ(1, m.code[2]->OutputCount()); |
1214 CHECK_EQ(2, m.code[2]->InputCount()); | 1127 CHECK_EQ(2, m.code[2]->InputCount()); |
1215 CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0)); | 1128 CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0)); |
1216 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); | 1129 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); |
1217 } | 1130 } |
1218 | 1131 |
1219 | 1132 |
1220 TEST(InstructionSelectorInt32UModP_ARMv7AndMlsAndSudivDisabled) { | 1133 TEST(InstructionSelectorInt32ModP_MLS_SUDIV) { |
1221 i::FLAG_enable_armv7 = false; | 1134 InstructionSelectorTester m; |
1222 i::FLAG_enable_mls = false; | 1135 m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1))); |
1223 i::FLAG_enable_sudiv = false; | 1136 m.SelectInstructions(MLS, SUDIV); |
| 1137 CHECK_EQ(2, m.code.size()); |
| 1138 CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode()); |
| 1139 CHECK_EQ(1, m.code[0]->OutputCount()); |
| 1140 CHECK_EQ(2, m.code[0]->InputCount()); |
| 1141 CHECK_EQ(kArmMls, m.code[1]->arch_opcode()); |
| 1142 CHECK_EQ(1, m.code[1]->OutputCount()); |
| 1143 CHECK_EQ(3, m.code[1]->InputCount()); |
| 1144 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0)); |
| 1145 CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1)); |
| 1146 CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2)); |
| 1147 } |
| 1148 |
| 1149 |
| 1150 TEST(InstructionSelectorInt32UModP) { |
1224 InstructionSelectorTester m; | 1151 InstructionSelectorTester m; |
1225 m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1))); | 1152 m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1))); |
1226 m.SelectInstructions(); | 1153 m.SelectInstructions(); |
1227 CHECK_EQ(6, m.code.size()); | 1154 CHECK_EQ(6, m.code.size()); |
1228 CHECK_EQ(kArmVcvtF64U32, m.code[0]->arch_opcode()); | 1155 CHECK_EQ(kArmVcvtF64U32, m.code[0]->arch_opcode()); |
1229 CHECK_EQ(1, m.code[0]->OutputCount()); | 1156 CHECK_EQ(1, m.code[0]->OutputCount()); |
1230 CHECK_EQ(kArmVcvtF64U32, m.code[1]->arch_opcode()); | 1157 CHECK_EQ(kArmVcvtF64U32, m.code[1]->arch_opcode()); |
1231 CHECK_EQ(1, m.code[1]->OutputCount()); | 1158 CHECK_EQ(1, m.code[1]->OutputCount()); |
1232 CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode()); | 1159 CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode()); |
1233 CHECK_EQ(2, m.code[2]->InputCount()); | 1160 CHECK_EQ(2, m.code[2]->InputCount()); |
1234 CHECK_EQ(1, m.code[2]->OutputCount()); | 1161 CHECK_EQ(1, m.code[2]->OutputCount()); |
1235 CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0)); | 1162 CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0)); |
1236 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); | 1163 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); |
1237 CHECK_EQ(kArmVcvtU32F64, m.code[3]->arch_opcode()); | 1164 CHECK_EQ(kArmVcvtU32F64, m.code[3]->arch_opcode()); |
1238 CHECK_EQ(1, m.code[3]->InputCount()); | 1165 CHECK_EQ(1, m.code[3]->InputCount()); |
1239 CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0)); | 1166 CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0)); |
1240 CHECK_EQ(kArmMul, m.code[4]->arch_opcode()); | 1167 CHECK_EQ(kArmMul, m.code[4]->arch_opcode()); |
1241 CHECK_EQ(1, m.code[4]->OutputCount()); | 1168 CHECK_EQ(1, m.code[4]->OutputCount()); |
1242 CHECK_EQ(2, m.code[4]->InputCount()); | 1169 CHECK_EQ(2, m.code[4]->InputCount()); |
1243 CheckSameVreg(m.code[3]->Output(), m.code[4]->InputAt(0)); | 1170 CheckSameVreg(m.code[3]->Output(), m.code[4]->InputAt(0)); |
1244 CheckSameVreg(m.code[1]->InputAt(0), m.code[4]->InputAt(1)); | 1171 CheckSameVreg(m.code[1]->InputAt(0), m.code[4]->InputAt(1)); |
1245 CHECK_EQ(kArmSub, m.code[5]->arch_opcode()); | 1172 CHECK_EQ(kArmSub, m.code[5]->arch_opcode()); |
1246 CHECK_EQ(1, m.code[5]->OutputCount()); | 1173 CHECK_EQ(1, m.code[5]->OutputCount()); |
1247 CHECK_EQ(2, m.code[5]->InputCount()); | 1174 CHECK_EQ(2, m.code[5]->InputCount()); |
1248 CheckSameVreg(m.code[0]->InputAt(0), m.code[5]->InputAt(0)); | 1175 CheckSameVreg(m.code[0]->InputAt(0), m.code[5]->InputAt(0)); |
1249 CheckSameVreg(m.code[4]->Output(), m.code[5]->InputAt(1)); | 1176 CheckSameVreg(m.code[4]->Output(), m.code[5]->InputAt(1)); |
1250 } | 1177 } |
1251 | 1178 |
1252 #endif // USE_SIMULATOR | 1179 |
| 1180 TEST(InstructionSelectorInt32UModP_SUDIV) { |
| 1181 InstructionSelectorTester m; |
| 1182 m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1))); |
| 1183 m.SelectInstructions(SUDIV); |
| 1184 CHECK_EQ(3, m.code.size()); |
| 1185 CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode()); |
| 1186 CHECK_EQ(1, m.code[0]->OutputCount()); |
| 1187 CHECK_EQ(2, m.code[0]->InputCount()); |
| 1188 CHECK_EQ(kArmMul, m.code[1]->arch_opcode()); |
| 1189 CHECK_EQ(1, m.code[1]->OutputCount()); |
| 1190 CHECK_EQ(2, m.code[1]->InputCount()); |
| 1191 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0)); |
| 1192 CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1)); |
| 1193 CHECK_EQ(kArmSub, m.code[2]->arch_opcode()); |
| 1194 CHECK_EQ(1, m.code[2]->OutputCount()); |
| 1195 CHECK_EQ(2, m.code[2]->InputCount()); |
| 1196 CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0)); |
| 1197 CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1)); |
| 1198 } |
| 1199 |
| 1200 |
| 1201 TEST(InstructionSelectorInt32UModP_MLS_SUDIV) { |
| 1202 InstructionSelectorTester m; |
| 1203 m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1))); |
| 1204 m.SelectInstructions(MLS, SUDIV); |
| 1205 CHECK_EQ(2, m.code.size()); |
| 1206 CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode()); |
| 1207 CHECK_EQ(1, m.code[0]->OutputCount()); |
| 1208 CHECK_EQ(2, m.code[0]->InputCount()); |
| 1209 CHECK_EQ(kArmMls, m.code[1]->arch_opcode()); |
| 1210 CHECK_EQ(1, m.code[1]->OutputCount()); |
| 1211 CHECK_EQ(3, m.code[1]->InputCount()); |
| 1212 CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0)); |
| 1213 CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1)); |
| 1214 CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2)); |
| 1215 } |
1253 | 1216 |
1254 | 1217 |
1255 TEST(InstructionSelectorWord32EqualP) { | 1218 TEST(InstructionSelectorWord32EqualP) { |
1256 InstructionSelectorTester m; | 1219 InstructionSelectorTester m; |
1257 m.Return(m.Word32Equal(m.Parameter(0), m.Parameter(1))); | 1220 m.Return(m.Word32Equal(m.Parameter(0), m.Parameter(1))); |
1258 m.SelectInstructions(); | 1221 m.SelectInstructions(); |
1259 CHECK_EQ(1, m.code.size()); | 1222 CHECK_EQ(1, m.code.size()); |
1260 CHECK_EQ(kArmCmp, m.code[0]->arch_opcode()); | 1223 CHECK_EQ(kArmCmp, m.code[0]->arch_opcode()); |
1261 CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode()); | 1224 CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode()); |
1262 CHECK_EQ(kFlags_set, m.code[0]->flags_mode()); | 1225 CHECK_EQ(kFlags_set, m.code[0]->flags_mode()); |
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1891 CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode()); | 1854 CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode()); |
1892 CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode()); | 1855 CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode()); |
1893 CHECK_EQ(kFlags_branch, m.code[0]->flags_mode()); | 1856 CHECK_EQ(kFlags_branch, m.code[0]->flags_mode()); |
1894 CHECK_EQ(kNotOverflow, m.code[0]->flags_condition()); | 1857 CHECK_EQ(kNotOverflow, m.code[0]->flags_condition()); |
1895 CHECK_LE(2, m.code[0]->InputCount()); | 1858 CHECK_LE(2, m.code[0]->InputCount()); |
1896 CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1))); | 1859 CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1))); |
1897 } | 1860 } |
1898 } | 1861 } |
1899 } | 1862 } |
1900 } | 1863 } |
OLD | NEW |