[turbofan] Improve testability of the InstructionSelector.

test/cctest/compiler/test-instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <list>
 
 #include "test/cctest/compiler/instruction-selector-tester.h"
 #include "test/cctest/compiler/value-helper.h"
 
 using namespace v8::internal;
@@ skipping 101 matching lines @@
     InstructionSelectorTester m;
     m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Parameter(1)));
     m.SelectInstructions();
     CHECK_EQ(1, m.code.size());
     CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
     CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
   }
 }
 
 
+TEST(InstructionSelectorDPIImm) {
+  DPIs dpis;
+  Immediates immediates;
+  for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
+    DPI dpi = *i;
+    for (Immediates::const_iterator j = immediates.begin();
+         j != immediates.end(); ++j) {
+      int32_t imm = *j;
+      {
+        InstructionSelectorTester m;
+        m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Int32Constant(imm)));
+        m.SelectInstructions();
+        CHECK_EQ(1, m.code.size());
+        CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
+        CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
+      }
+      {
+        InstructionSelectorTester m;
+        m.Return(m.NewNode(dpi.op, m.Int32Constant(imm), m.Parameter(0)));
+        m.SelectInstructions();
+        CHECK_EQ(1, m.code.size());
+        CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode());
+        CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
+      }
+    }
+  }
+}
+
+
 TEST(InstructionSelectorDPIAndShiftP) {
   DPIs dpis;
   Shifts shifts;
   for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
     DPI dpi = *i;
     for (Shifts::const_iterator j = shifts.begin(); j != shifts.end(); ++j) {
       Shift shift = *j;
       {
         InstructionSelectorTester m;
         m.Return(
@@ skipping 733 matching lines @@
     InstructionSelectorTester m;
     m.Return(m.Int32Mul(m.Int32Constant((1 << k) - 1), m.Parameter(0)));
     m.SelectInstructions();
     CHECK_EQ(1, m.code.size());
     CHECK_EQ(kArmRsb, m.code[0]->arch_opcode());
     CHECK_EQ(kMode_Operand2_R_LSL_I, m.code[0]->addressing_mode());
   }
 }
 
 
-// The following tests depend on the exact CPU features available, which we do
-// only fully control in a simulator build.
-#ifdef USE_SIMULATOR
-
-TEST(InstructionSelectorDPIImm_ARMv7AndVFP3Disabled) {
-  i::FLAG_enable_armv7 = false;
-  i::FLAG_enable_vfp3 = false;
-  DPIs dpis;
-  Immediates immediates;
-  for (DPIs::const_iterator i = dpis.begin(); i != dpis.end(); ++i) {
-    DPI dpi = *i;
-    for (Immediates::const_iterator j = immediates.begin();
-         j != immediates.end(); ++j) {
-      int32_t imm = *j;
-      {
-        InstructionSelectorTester m;
-        m.Return(m.NewNode(dpi.op, m.Parameter(0), m.Int32Constant(imm)));
-        m.SelectInstructions();
-        CHECK_EQ(1, m.code.size());
-        CHECK_EQ(dpi.arch_opcode, m.code[0]->arch_opcode());
-        CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
-      }
-      {
-        InstructionSelectorTester m;
-        m.Return(m.NewNode(dpi.op, m.Int32Constant(imm), m.Parameter(0)));
-        m.SelectInstructions();
-        CHECK_EQ(1, m.code.size());
-        CHECK_EQ(dpi.reverse_arch_opcode, m.code[0]->arch_opcode());
-        CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
-      }
-    }
-  }
-}
-
-
-TEST(InstructionSelectorWord32AndImm_ARMv7Enabled) {
-  i::FLAG_enable_armv7 = true;
+TEST(InstructionSelectorWord32AndImm_ARMv7) {
   for (uint32_t width = 1; width <= 32; ++width) {
     InstructionSelectorTester m;
     m.Return(m.Word32And(m.Parameter(0),
                          m.Int32Constant(0xffffffffu >> (32 - width))));
-    m.SelectInstructions();
+    m.SelectInstructions(ARMv7);
     CHECK_EQ(1, m.code.size());
     CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
     CHECK_EQ(3, m.code[0]->InputCount());
     CHECK_EQ(0, m.ToInt32(m.code[0]->InputAt(1)));
     CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
   }
   for (uint32_t lsb = 0; lsb <= 31; ++lsb) {
     for (uint32_t width = 1; width < 32 - lsb; ++width) {
       uint32_t msk = ~((0xffffffffu >> (32 - width)) << lsb);
       InstructionSelectorTester m;
       m.Return(m.Word32And(m.Parameter(0), m.Int32Constant(msk)));
-      m.SelectInstructions();
+      m.SelectInstructions(ARMv7);
       CHECK_EQ(1, m.code.size());
       CHECK_EQ(kArmBfc, m.code[0]->arch_opcode());
       CHECK_EQ(1, m.code[0]->OutputCount());
       CHECK(UnallocatedOperand::cast(m.code[0]->Output())
                 ->HasSameAsInputPolicy());
       CHECK_EQ(3, m.code[0]->InputCount());
       CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
       CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
     }
   }
 }
 
 
-TEST(InstructionSelectorWord32AndAndWord32ShrImm_ARMv7Enabled) {
-  i::FLAG_enable_armv7 = true;
+TEST(InstructionSelectorWord32AndAndWord32ShrImm_ARMv7) {
   for (uint32_t lsb = 0; lsb <= 31; ++lsb) {
     for (uint32_t width = 1; width <= 32 - lsb; ++width) {
       {
         InstructionSelectorTester m;
         m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb)),
                              m.Int32Constant(0xffffffffu >> (32 - width))));
-        m.SelectInstructions();
+        m.SelectInstructions(ARMv7);
         CHECK_EQ(1, m.code.size());
         CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
         CHECK_EQ(3, m.code[0]->InputCount());
         CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
         CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
       }
       {
         InstructionSelectorTester m;
         m.Return(
             m.Word32And(m.Int32Constant(0xffffffffu >> (32 - width)),
                         m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb))));
-        m.SelectInstructions();
+        m.SelectInstructions(ARMv7);
         CHECK_EQ(1, m.code.size());
         CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
         CHECK_EQ(3, m.code[0]->InputCount());
         CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
         CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
       }
     }
   }
 }
 
 
-TEST(InstructionSelectorWord32ShrAndWord32AndImm_ARMv7Enabled) {
-  i::FLAG_enable_armv7 = true;
+TEST(InstructionSelectorWord32ShrAndWord32AndImm_ARMv7) {
   for (uint32_t lsb = 0; lsb <= 31; ++lsb) {
     for (uint32_t width = 1; width <= 32 - lsb; ++width) {
       uint32_t max = 1 << lsb;
       if (max > static_cast<uint32_t>(kMaxInt)) max -= 1;
       uint32_t jnk = CcTest::random_number_generator()->NextInt(max);
       uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk;
       {
         InstructionSelectorTester m;
         m.Return(m.Word32Shr(m.Word32And(m.Parameter(0), m.Int32Constant(msk)),
                              m.Int32Constant(lsb)));
-        m.SelectInstructions();
+        m.SelectInstructions(ARMv7);
         CHECK_EQ(1, m.code.size());
         CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
         CHECK_EQ(3, m.code[0]->InputCount());
         CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
         CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
       }
       {
         InstructionSelectorTester m;
         m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(msk), m.Parameter(0)),
                              m.Int32Constant(lsb)));
-        m.SelectInstructions();
+        m.SelectInstructions(ARMv7);
         CHECK_EQ(1, m.code.size());
         CHECK_EQ(kArmUbfx, m.code[0]->arch_opcode());
         CHECK_EQ(3, m.code[0]->InputCount());
         CHECK_EQ(lsb, m.ToInt32(m.code[0]->InputAt(1)));
         CHECK_EQ(width, m.ToInt32(m.code[0]->InputAt(2)));
       }
     }
   }
 }
 
 
-TEST(InstructionSelectorInt32SubAndInt32MulP_MlsEnabled) {
-  i::FLAG_enable_mls = true;
+TEST(InstructionSelectorInt32SubAndInt32MulP) {
   InstructionSelectorTester m;
   m.Return(
       m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2))));
-  m.SelectInstructions();
-  CHECK_EQ(1, m.code.size());
-  CHECK_EQ(kArmMls, m.code[0]->arch_opcode());
-}
-
-
-TEST(InstructionSelectorInt32SubAndInt32MulP_MlsDisabled) {
-  i::FLAG_enable_mls = false;
-  InstructionSelectorTester m;
-  m.Return(
-      m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2))));
   m.SelectInstructions();
   CHECK_EQ(2, m.code.size());
   CHECK_EQ(kArmMul, m.code[0]->arch_opcode());
   CHECK_EQ(1, m.code[0]->OutputCount());
   CHECK_EQ(kArmSub, m.code[1]->arch_opcode());
   CHECK_EQ(2, m.code[1]->InputCount());
   CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(1));
 }
 
 
-TEST(InstructionSelectorInt32DivP_ARMv7AndSudivEnabled) {
-  i::FLAG_enable_armv7 = true;
-  i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32SubAndInt32MulP_MLS) {
+  InstructionSelectorTester m;
+  m.Return(
+      m.Int32Sub(m.Parameter(0), m.Int32Mul(m.Parameter(1), m.Parameter(2))));
+  m.SelectInstructions(MLS);
+  CHECK_EQ(1, m.code.size());
+  CHECK_EQ(kArmMls, m.code[0]->arch_opcode());
+}
+
+
+TEST(InstructionSelectorInt32DivP) {
   InstructionSelectorTester m;
   m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1)));
   m.SelectInstructions();
-  CHECK_EQ(1, m.code.size());
-  CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
-}
-
-
-TEST(InstructionSelectorInt32DivP_SudivDisabled) {
-  i::FLAG_enable_sudiv = false;
-  InstructionSelectorTester m;
-  m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1)));
-  m.SelectInstructions();
   CHECK_EQ(4, m.code.size());
   CHECK_EQ(kArmVcvtF64S32, m.code[0]->arch_opcode());
   CHECK_EQ(1, m.code[0]->OutputCount());
   CHECK_EQ(kArmVcvtF64S32, m.code[1]->arch_opcode());
   CHECK_EQ(1, m.code[1]->OutputCount());
   CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode());
   CHECK_EQ(2, m.code[2]->InputCount());
   CHECK_EQ(1, m.code[2]->OutputCount());
   CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0));
   CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
   CHECK_EQ(kArmVcvtS32F64, m.code[3]->arch_opcode());
   CHECK_EQ(1, m.code[3]->InputCount());
   CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0));
 }
 
 
-TEST(InstructionSelectorInt32UDivP_ARMv7AndSudivEnabled) {
-  i::FLAG_enable_armv7 = true;
-  i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32DivP_SUDIV) {
+  InstructionSelectorTester m;
+  m.Return(m.Int32Div(m.Parameter(0), m.Parameter(1)));
+  m.SelectInstructions(SUDIV);
+  CHECK_EQ(1, m.code.size());
+  CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
+}
+
+
+TEST(InstructionSelectorInt32UDivP) {
   InstructionSelectorTester m;
   m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
   m.SelectInstructions();
-  CHECK_EQ(1, m.code.size());
-  CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
-}
-
-
-TEST(InstructionSelectorInt32UDivP_SudivDisabled) {
-  i::FLAG_enable_sudiv = false;
-  InstructionSelectorTester m;
-  m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
-  m.SelectInstructions();
   CHECK_EQ(4, m.code.size());
   CHECK_EQ(kArmVcvtF64U32, m.code[0]->arch_opcode());
   CHECK_EQ(1, m.code[0]->OutputCount());
   CHECK_EQ(kArmVcvtF64U32, m.code[1]->arch_opcode());
   CHECK_EQ(1, m.code[1]->OutputCount());
   CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode());
   CHECK_EQ(2, m.code[2]->InputCount());
   CHECK_EQ(1, m.code[2]->OutputCount());
   CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0));
   CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
   CHECK_EQ(kArmVcvtU32F64, m.code[3]->arch_opcode());
   CHECK_EQ(1, m.code[3]->InputCount());
   CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0));
 }
 
 
-TEST(InstructionSelectorInt32ModP_ARMv7AndMlsAndSudivEnabled) {
-  i::FLAG_enable_armv7 = true;
-  i::FLAG_enable_mls = true;
-  i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32UDivP_SUDIV) {
+  InstructionSelectorTester m;
+  m.Return(m.Int32UDiv(m.Parameter(0), m.Parameter(1)));
+  m.SelectInstructions(SUDIV);
+  CHECK_EQ(1, m.code.size());
+  CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
+}
+
+
+TEST(InstructionSelectorInt32ModP) {
   InstructionSelectorTester m;
   m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
   m.SelectInstructions();
-  CHECK_EQ(2, m.code.size());
-  CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
-  CHECK_EQ(1, m.code[0]->OutputCount());
-  CHECK_EQ(2, m.code[0]->InputCount());
-  CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
-  CHECK_EQ(1, m.code[1]->OutputCount());
-  CHECK_EQ(3, m.code[1]->InputCount());
-  CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
-  CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
-  CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
-}
-
-
-TEST(InstructionSelectorInt32ModP_ARMv7AndSudivEnabled) {
-  i::FLAG_enable_armv7 = true;
-  i::FLAG_enable_mls = false;
-  i::FLAG_enable_sudiv = true;
-  InstructionSelectorTester m;
-  m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
-  m.SelectInstructions();
-  CHECK_EQ(3, m.code.size());
-  CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
-  CHECK_EQ(1, m.code[0]->OutputCount());
-  CHECK_EQ(2, m.code[0]->InputCount());
-  CHECK_EQ(kArmMul, m.code[1]->arch_opcode());
-  CHECK_EQ(1, m.code[1]->OutputCount());
-  CHECK_EQ(2, m.code[1]->InputCount());
-  CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
-  CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
-  CHECK_EQ(kArmSub, m.code[2]->arch_opcode());
-  CHECK_EQ(1, m.code[2]->OutputCount());
-  CHECK_EQ(2, m.code[2]->InputCount());
-  CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0));
-  CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
-}
-
-
-TEST(InstructionSelectorInt32ModP_ARMv7AndMlsAndSudivDisabled) {
-  i::FLAG_enable_armv7 = false;
-  i::FLAG_enable_mls = false;
-  i::FLAG_enable_sudiv = false;
-  InstructionSelectorTester m;
-  m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
-  m.SelectInstructions();
   CHECK_EQ(6, m.code.size());
   CHECK_EQ(kArmVcvtF64S32, m.code[0]->arch_opcode());
   CHECK_EQ(1, m.code[0]->OutputCount());
   CHECK_EQ(kArmVcvtF64S32, m.code[1]->arch_opcode());
   CHECK_EQ(1, m.code[1]->OutputCount());
   CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode());
   CHECK_EQ(2, m.code[2]->InputCount());
   CHECK_EQ(1, m.code[2]->OutputCount());
   CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0));
   CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
   CHECK_EQ(kArmVcvtS32F64, m.code[3]->arch_opcode());
   CHECK_EQ(1, m.code[3]->InputCount());
   CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0));
   CHECK_EQ(kArmMul, m.code[4]->arch_opcode());
   CHECK_EQ(1, m.code[4]->OutputCount());
   CHECK_EQ(2, m.code[4]->InputCount());
   CheckSameVreg(m.code[3]->Output(), m.code[4]->InputAt(0));
   CheckSameVreg(m.code[1]->InputAt(0), m.code[4]->InputAt(1));
   CHECK_EQ(kArmSub, m.code[5]->arch_opcode());
   CHECK_EQ(1, m.code[5]->OutputCount());
   CHECK_EQ(2, m.code[5]->InputCount());
   CheckSameVreg(m.code[0]->InputAt(0), m.code[5]->InputAt(0));
   CheckSameVreg(m.code[4]->Output(), m.code[5]->InputAt(1));
 }
 
 
-TEST(InstructionSelectorInt32UModP_ARMv7AndMlsAndSudivEnabled) {
-  i::FLAG_enable_armv7 = true;
-  i::FLAG_enable_mls = true;
-  i::FLAG_enable_sudiv = true;
+TEST(InstructionSelectorInt32ModP_SUDIV) {
   InstructionSelectorTester m;
-  m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
-  m.SelectInstructions();
-  CHECK_EQ(2, m.code.size());
-  CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
-  CHECK_EQ(1, m.code[0]->OutputCount());
-  CHECK_EQ(2, m.code[0]->InputCount());
-  CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
-  CHECK_EQ(1, m.code[1]->OutputCount());
-  CHECK_EQ(3, m.code[1]->InputCount());
-  CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
-  CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
-  CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
-}
-
-
-TEST(InstructionSelectorInt32UModP_ARMv7AndSudivEnabled) {
-  i::FLAG_enable_armv7 = true;
-  i::FLAG_enable_mls = false;
-  i::FLAG_enable_sudiv = true;
-  InstructionSelectorTester m;
-  m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
-  m.SelectInstructions();
+  m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
+  m.SelectInstructions(SUDIV);
   CHECK_EQ(3, m.code.size());
-  CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
+  CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
   CHECK_EQ(1, m.code[0]->OutputCount());
   CHECK_EQ(2, m.code[0]->InputCount());
   CHECK_EQ(kArmMul, m.code[1]->arch_opcode());
   CHECK_EQ(1, m.code[1]->OutputCount());
   CHECK_EQ(2, m.code[1]->InputCount());
   CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
   CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
   CHECK_EQ(kArmSub, m.code[2]->arch_opcode());
   CHECK_EQ(1, m.code[2]->OutputCount());
   CHECK_EQ(2, m.code[2]->InputCount());
   CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0));
   CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
 }
 
 
-TEST(InstructionSelectorInt32UModP_ARMv7AndMlsAndSudivDisabled) {
-  i::FLAG_enable_armv7 = false;
-  i::FLAG_enable_mls = false;
-  i::FLAG_enable_sudiv = false;
+TEST(InstructionSelectorInt32ModP_MLS_SUDIV) {
+  InstructionSelectorTester m;
+  m.Return(m.Int32Mod(m.Parameter(0), m.Parameter(1)));
+  m.SelectInstructions(MLS, SUDIV);
+  CHECK_EQ(2, m.code.size());
+  CHECK_EQ(kArmSdiv, m.code[0]->arch_opcode());
+  CHECK_EQ(1, m.code[0]->OutputCount());
+  CHECK_EQ(2, m.code[0]->InputCount());
+  CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
+  CHECK_EQ(1, m.code[1]->OutputCount());
+  CHECK_EQ(3, m.code[1]->InputCount());
+  CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
+  CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
+  CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
+}
+
+
+TEST(InstructionSelectorInt32UModP) {
   InstructionSelectorTester m;
   m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
   m.SelectInstructions();
   CHECK_EQ(6, m.code.size());
   CHECK_EQ(kArmVcvtF64U32, m.code[0]->arch_opcode());
   CHECK_EQ(1, m.code[0]->OutputCount());
   CHECK_EQ(kArmVcvtF64U32, m.code[1]->arch_opcode());
   CHECK_EQ(1, m.code[1]->OutputCount());
   CHECK_EQ(kArmVdivF64, m.code[2]->arch_opcode());
   CHECK_EQ(2, m.code[2]->InputCount());
   CHECK_EQ(1, m.code[2]->OutputCount());
   CheckSameVreg(m.code[0]->Output(), m.code[2]->InputAt(0));
   CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
   CHECK_EQ(kArmVcvtU32F64, m.code[3]->arch_opcode());
   CHECK_EQ(1, m.code[3]->InputCount());
   CheckSameVreg(m.code[2]->Output(), m.code[3]->InputAt(0));
   CHECK_EQ(kArmMul, m.code[4]->arch_opcode());
   CHECK_EQ(1, m.code[4]->OutputCount());
   CHECK_EQ(2, m.code[4]->InputCount());
   CheckSameVreg(m.code[3]->Output(), m.code[4]->InputAt(0));
   CheckSameVreg(m.code[1]->InputAt(0), m.code[4]->InputAt(1));
   CHECK_EQ(kArmSub, m.code[5]->arch_opcode());
   CHECK_EQ(1, m.code[5]->OutputCount());
   CHECK_EQ(2, m.code[5]->InputCount());
   CheckSameVreg(m.code[0]->InputAt(0), m.code[5]->InputAt(0));
   CheckSameVreg(m.code[4]->Output(), m.code[5]->InputAt(1));
 }
 
-#endif  // USE_SIMULATOR
+
+TEST(InstructionSelectorInt32UModP_SUDIV) {
+  InstructionSelectorTester m;
+  m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
+  m.SelectInstructions(SUDIV);
+  CHECK_EQ(3, m.code.size());
+  CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
+  CHECK_EQ(1, m.code[0]->OutputCount());
+  CHECK_EQ(2, m.code[0]->InputCount());
+  CHECK_EQ(kArmMul, m.code[1]->arch_opcode());
+  CHECK_EQ(1, m.code[1]->OutputCount());
+  CHECK_EQ(2, m.code[1]->InputCount());
+  CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
+  CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
+  CHECK_EQ(kArmSub, m.code[2]->arch_opcode());
+  CHECK_EQ(1, m.code[2]->OutputCount());
+  CHECK_EQ(2, m.code[2]->InputCount());
+  CheckSameVreg(m.code[0]->InputAt(0), m.code[2]->InputAt(0));
+  CheckSameVreg(m.code[1]->Output(), m.code[2]->InputAt(1));
+}
+
+
+TEST(InstructionSelectorInt32UModP_MLS_SUDIV) {
+  InstructionSelectorTester m;
+  m.Return(m.Int32UMod(m.Parameter(0), m.Parameter(1)));
+  m.SelectInstructions(MLS, SUDIV);
+  CHECK_EQ(2, m.code.size());
+  CHECK_EQ(kArmUdiv, m.code[0]->arch_opcode());
+  CHECK_EQ(1, m.code[0]->OutputCount());
+  CHECK_EQ(2, m.code[0]->InputCount());
+  CHECK_EQ(kArmMls, m.code[1]->arch_opcode());
+  CHECK_EQ(1, m.code[1]->OutputCount());
+  CHECK_EQ(3, m.code[1]->InputCount());
+  CheckSameVreg(m.code[0]->Output(), m.code[1]->InputAt(0));
+  CheckSameVreg(m.code[0]->InputAt(1), m.code[1]->InputAt(1));
+  CheckSameVreg(m.code[0]->InputAt(0), m.code[1]->InputAt(2));
+}
 
 
 TEST(InstructionSelectorWord32EqualP) {
   InstructionSelectorTester m;
   m.Return(m.Word32Equal(m.Parameter(0), m.Parameter(1)));
   m.SelectInstructions();
   CHECK_EQ(1, m.code.size());
   CHECK_EQ(kArmCmp, m.code[0]->arch_opcode());
   CHECK_EQ(kMode_Operand2_R, m.code[0]->addressing_mode());
   CHECK_EQ(kFlags_set, m.code[0]->flags_mode());
@@ skipping 628 matching lines @@
         CHECK_EQ(odpi.reverse_arch_opcode, m.code[0]->arch_opcode());
         CHECK_EQ(kMode_Operand2_I, m.code[0]->addressing_mode());
         CHECK_EQ(kFlags_branch, m.code[0]->flags_mode());
         CHECK_EQ(kNotOverflow, m.code[0]->flags_condition());
         CHECK_LE(2, m.code[0]->InputCount());
         CHECK_EQ(imm, m.ToInt32(m.code[0]->InputAt(1)));
       }
     }
   }
 }