[turbofan] Improve testability of the InstructionSelector.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler-intrinsics.h"
 
 namespace v8 {
 namespace internal {
@@ skipping 419 matching lines @@
       return;
     }
   }
   if (m.right().IsWord32Xor() && CanCover(node, m.right().node())) {
     Int32BinopMatcher mright(m.right().node());
     if (mright.right().Is(-1)) {
       EmitBic(this, node, m.left().node(), mright.left().node());
       return;
     }
   }
-  if (CpuFeatures::IsSupported(ARMv7) && m.right().HasValue()) {
+  if (IsSupported(ARMv7) && m.right().HasValue()) {
     uint32_t value = m.right().Value();
     uint32_t width = CompilerIntrinsics::CountSetBits(value);
     uint32_t msb = CompilerIntrinsics::CountLeadingZeros(value);
     if (width != 0 && msb + width == 32) {
       DCHECK_EQ(0, CompilerIntrinsics::CountTrailingZeros(value));
       if (m.left().IsWord32Shr()) {
         Int32BinopMatcher mleft(m.left().node());
         if (mleft.right().IsInRange(0, 31)) {
           Emit(kArmUbfx, g.DefineAsRegister(node),
                g.UseRegister(mleft.left().node()),
@@ skipping 67 matching lines @@
 
 
 void InstructionSelector::VisitWord32Shl(Node* node) {
   VisitShift(this, node, TryMatchLSL);
 }
 
 
 void InstructionSelector::VisitWord32Shr(Node* node) {
   ArmOperandGenerator g(this);
   Int32BinopMatcher m(node);
-  if (CpuFeatures::IsSupported(ARMv7) && m.left().IsWord32And() &&
+  if (IsSupported(ARMv7) && m.left().IsWord32And() &&
       m.right().IsInRange(0, 31)) {
     int32_t lsb = m.right().Value();
     Int32BinopMatcher mleft(m.left().node());
     if (mleft.right().HasValue()) {
       uint32_t value = (mleft.right().Value() >> lsb) << lsb;
       uint32_t width = CompilerIntrinsics::CountSetBits(value);
       uint32_t msb = CompilerIntrinsics::CountLeadingZeros(value);
       if (msb + width + lsb == 32) {
         DCHECK_EQ(lsb, CompilerIntrinsics::CountTrailingZeros(value));
         Emit(kArmUbfx, g.DefineAsRegister(node),
@@ skipping 27 matching lines @@
          g.UseRegister(mright.right().node()), g.UseRegister(m.left().node()));
     return;
   }
   VisitBinop(this, node, kArmAdd, kArmAdd);
 }
 
 
 void InstructionSelector::VisitInt32Sub(Node* node) {
   ArmOperandGenerator g(this);
   Int32BinopMatcher m(node);
-  if (CpuFeatures::IsSupported(MLS) && m.right().IsInt32Mul() &&
+  if (IsSupported(MLS) && m.right().IsInt32Mul() &&
       CanCover(node, m.right().node())) {
     Int32BinopMatcher mright(m.right().node());
     Emit(kArmMls, g.DefineAsRegister(node), g.UseRegister(mright.left().node()),
          g.UseRegister(mright.right().node()), g.UseRegister(m.left().node()));
     return;
   }
   VisitBinop(this, node, kArmSub, kArmRsb);
 }
 
 
@@ skipping 21 matching lines @@
        g.UseRegister(m.right().node()));
 }
 
 
 static void EmitDiv(InstructionSelector* selector, ArchOpcode div_opcode,
                     ArchOpcode f64i32_opcode, ArchOpcode i32f64_opcode,
                     InstructionOperand* result_operand,
                     InstructionOperand* left_operand,
                     InstructionOperand* right_operand) {
   ArmOperandGenerator g(selector);
-  if (CpuFeatures::IsSupported(SUDIV)) {
+  if (selector->IsSupported(SUDIV)) {
     selector->Emit(div_opcode, result_operand, left_operand, right_operand);
     return;
   }
   InstructionOperand* left_double_operand = g.TempDoubleRegister();
   InstructionOperand* right_double_operand = g.TempDoubleRegister();
   InstructionOperand* result_double_operand = g.TempDoubleRegister();
   selector->Emit(f64i32_opcode, left_double_operand, left_operand);
   selector->Emit(f64i32_opcode, right_double_operand, right_operand);
   selector->Emit(kArmVdivF64, result_double_operand, left_double_operand,
                  right_double_operand);
@@ skipping 26 matching lines @@
                      ArchOpcode div_opcode, ArchOpcode f64i32_opcode,
                      ArchOpcode i32f64_opcode) {
   ArmOperandGenerator g(selector);
   Int32BinopMatcher m(node);
   InstructionOperand* div_operand = g.TempRegister();
   InstructionOperand* result_operand = g.DefineAsRegister(node);
   InstructionOperand* left_operand = g.UseRegister(m.left().node());
   InstructionOperand* right_operand = g.UseRegister(m.right().node());
   EmitDiv(selector, div_opcode, f64i32_opcode, i32f64_opcode, div_operand,
           left_operand, right_operand);
-  if (CpuFeatures::IsSupported(MLS)) {
+  if (selector->IsSupported(MLS)) {
     selector->Emit(kArmMls, result_operand, div_operand, right_operand,
                    left_operand);
     return;
   }
   InstructionOperand* mul_operand = g.TempRegister();
   selector->Emit(kArmMul, mul_operand, div_operand, right_operand);
   selector->Emit(kArmSub, result_operand, left_operand, mul_operand);
 }
 
 
@@ skipping 258 matching lines @@
     DCHECK(cont->IsSet());
     Emit(cont->Encode(kArmVcmpF64), g.DefineAsRegister(cont->result()),
          g.UseDoubleRegister(m.left().node()),
          g.UseDoubleRegister(m.right().node()));
   }
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8