Index: src/arm64/macro-assembler-arm64-inl.h |
diff --git a/src/arm64/macro-assembler-arm64-inl.h b/src/arm64/macro-assembler-arm64-inl.h |
index cf5062d054452649f06cad07449ddc352489eb59..f7c724842ac55ffb1584d4770962fd0996306c3e 100644 |
--- a/src/arm64/macro-assembler-arm64-inl.h |
+++ b/src/arm64/macro-assembler-arm64-inl.h |
@@ -299,6 +299,16 @@ LS_MACRO_LIST(DEFINE_FUNCTION) |
#undef DEFINE_FUNCTION |
+#define DEFINE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \ |
+ void MacroAssembler::FN(const REGTYPE REG, const REGTYPE REG2, \ |
+ const MemOperand& addr) { \ |
+ DCHECK(allow_macro_instructions_); \ |
+ LoadStorePairMacro(REG, REG2, addr, OP); \ |
+ } |
+LSPAIR_MACRO_LIST(DEFINE_FUNCTION) |
+#undef DEFINE_FUNCTION |
+ |
+ |
void MacroAssembler::Asr(const Register& rd, |
const Register& rn, |
unsigned shift) { |
@@ -861,25 +871,6 @@ void MacroAssembler::Ldnp(const CPURegister& rt, |
} |
-void MacroAssembler::Ldp(const CPURegister& rt, |
- const CPURegister& rt2, |
- const MemOperand& src) { |
- DCHECK(allow_macro_instructions_); |
- DCHECK(!AreAliased(rt, rt2)); |
- ldp(rt, rt2, src); |
-} |
- |
- |
-void MacroAssembler::Ldpsw(const Register& rt, |
- const Register& rt2, |
- const MemOperand& src) { |
- DCHECK(allow_macro_instructions_); |
- DCHECK(!rt.IsZero()); |
- DCHECK(!rt2.IsZero()); |
- ldpsw(rt, rt2, src); |
-} |
- |
- |
void MacroAssembler::Ldr(const CPURegister& rt, const Immediate& imm) { |
DCHECK(allow_macro_instructions_); |
ldr(rt, imm); |
@@ -1136,14 +1127,6 @@ void MacroAssembler::Stnp(const CPURegister& rt, |
} |
-void MacroAssembler::Stp(const CPURegister& rt, |
- const CPURegister& rt2, |
- const MemOperand& dst) { |
- DCHECK(allow_macro_instructions_); |
- stp(rt, rt2, dst); |
-} |
- |
- |
void MacroAssembler::Sxtb(const Register& rd, const Register& rn) { |
DCHECK(allow_macro_instructions_); |
DCHECK(!rd.IsZero()); |