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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 434553002: [arm] Add support for ROR. Refactor operand2 handling. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 55 matching lines...) Expand 10 before | Expand all | Expand 10 after
66 // are encoded into the InstructionCode of the instruction and tell the 66 // are encoded into the InstructionCode of the instruction and tell the
67 // code generator after register allocation which assembler method to call. 67 // code generator after register allocation which assembler method to call.
68 #define TARGET_ADDRESSING_MODE_LIST(V) \ 68 #define TARGET_ADDRESSING_MODE_LIST(V) \
69 V(Offset_RI) /* [%r0 + K] */ \ 69 V(Offset_RI) /* [%r0 + K] */ \
70 V(Offset_RR) /* [%r0 + %r1] */ \ 70 V(Offset_RR) /* [%r0 + %r1] */ \
71 V(Operand2_I) /* K */ \ 71 V(Operand2_I) /* K */ \
72 V(Operand2_R) /* %r0 */ \ 72 V(Operand2_R) /* %r0 */ \
73 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 73 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
74 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ 74 V(Operand2_R_LSL_I) /* %r0 LSL K */ \
75 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ 75 V(Operand2_R_LSR_I) /* %r0 LSR K */ \
76 V(Operand2_R_ROR_I) /* %r0 ROR K */ \
76 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 77 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
77 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 78 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
78 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ 79 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
80 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
79 81
80 } // namespace compiler 82 } // namespace compiler
81 } // namespace internal 83 } // namespace internal
82 } // namespace v8 84 } // namespace v8
83 85
84 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 86 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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