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Side by Side Diff: src/compiler/arm/instruction-selector-arm.cc

Issue 431473004: TF: Add ConvertFloat64ToUint32 and ConvertUint32ToFloat64 machine operators. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/instruction-selector-impl.h" 5 #include "src/compiler/instruction-selector-impl.h"
6 #include "src/compiler/node-matchers.h" 6 #include "src/compiler/node-matchers.h"
7 #include "src/compiler-intrinsics.h" 7 #include "src/compiler-intrinsics.h"
8 8
9 namespace v8 { 9 namespace v8 {
10 namespace internal { 10 namespace internal {
(...skipping 641 matching lines...) Expand 10 before | Expand all | Expand 10 after
652 } 652 }
653 653
654 654
655 void InstructionSelector::VisitConvertInt32ToFloat64(Node* node) { 655 void InstructionSelector::VisitConvertInt32ToFloat64(Node* node) {
656 ArmOperandGenerator g(this); 656 ArmOperandGenerator g(this);
657 Emit(kArmVcvtF64S32, g.DefineAsDoubleRegister(node), 657 Emit(kArmVcvtF64S32, g.DefineAsDoubleRegister(node),
658 g.UseRegister(node->InputAt(0))); 658 g.UseRegister(node->InputAt(0)));
659 } 659 }
660 660
661 661
662 void InstructionSelector::VisitConvertUint32ToFloat64(Node* node) {
663 ArmOperandGenerator g(this);
664 Emit(kArmVcvtF64U32, g.DefineAsDoubleRegister(node),
665 g.UseRegister(node->InputAt(0)));
666 }
667
668
662 void InstructionSelector::VisitConvertFloat64ToInt32(Node* node) { 669 void InstructionSelector::VisitConvertFloat64ToInt32(Node* node) {
663 ArmOperandGenerator g(this); 670 ArmOperandGenerator g(this);
664 Emit(kArmVcvtS32F64, g.DefineAsRegister(node), 671 Emit(kArmVcvtS32F64, g.DefineAsRegister(node),
665 g.UseDoubleRegister(node->InputAt(0))); 672 g.UseDoubleRegister(node->InputAt(0)));
666 } 673 }
667 674
668 675
676 void InstructionSelector::VisitConvertFloat64ToUint32(Node* node) {
677 ArmOperandGenerator g(this);
678 Emit(kArmVcvtU32F64, g.DefineAsRegister(node),
679 g.UseDoubleRegister(node->InputAt(0)));
680 }
681
682
669 void InstructionSelector::VisitFloat64Add(Node* node) { 683 void InstructionSelector::VisitFloat64Add(Node* node) {
670 ArmOperandGenerator g(this); 684 ArmOperandGenerator g(this);
671 Int32BinopMatcher m(node); 685 Int32BinopMatcher m(node);
672 if (m.left().IsFloat64Mul() && CanCover(node, m.left().node())) { 686 if (m.left().IsFloat64Mul() && CanCover(node, m.left().node())) {
673 Int32BinopMatcher mleft(m.left().node()); 687 Int32BinopMatcher mleft(m.left().node());
674 Emit(kArmVmlaF64, g.DefineSameAsFirst(node), 688 Emit(kArmVmlaF64, g.DefineSameAsFirst(node),
675 g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()), 689 g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
676 g.UseRegister(mleft.right().node())); 690 g.UseRegister(mleft.right().node()));
677 return; 691 return;
678 } 692 }
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880 ASSERT(cont->IsSet()); 894 ASSERT(cont->IsSet());
881 Emit(cont->Encode(kArmVcmpF64), g.DefineAsRegister(cont->result()), 895 Emit(cont->Encode(kArmVcmpF64), g.DefineAsRegister(cont->result()),
882 g.UseDoubleRegister(m.left().node()), 896 g.UseDoubleRegister(m.left().node()),
883 g.UseDoubleRegister(m.right().node())); 897 g.UseDoubleRegister(m.right().node()));
884 } 898 }
885 } 899 }
886 900
887 } // namespace compiler 901 } // namespace compiler
888 } // namespace internal 902 } // namespace internal
889 } // namespace v8 903 } // namespace v8
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