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Unified Diff: src/mips64/simulator-mips64.cc

Issue 430503007: Rename ASSERT* to DCHECK*. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: REBASE and fixes Created 6 years, 4 months ago
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Index: src/mips64/simulator-mips64.cc
diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc
index 6c930d51beaa86b86e04bb0a1595824ba52de0bc..c07558465fb71c545fba06dd77a54a138ee63867 100644
--- a/src/mips64/simulator-mips64.cc
+++ b/src/mips64/simulator-mips64.cc
@@ -124,7 +124,7 @@ void MipsDebugger::Stop(Instruction* instr) {
char** msg_address =
reinterpret_cast<char**>(sim_->get_pc() + Instr::kInstrSize);
char* msg = *msg_address;
- ASSERT(msg != NULL);
+ DCHECK(msg != NULL);
// Update this stop description.
if (!watched_stops_[code].desc) {
@@ -770,8 +770,8 @@ void MipsDebugger::Debug() {
static bool ICacheMatch(void* one, void* two) {
- ASSERT((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
- ASSERT((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
+ DCHECK((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
+ DCHECK((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
return one == two;
}
@@ -808,7 +808,7 @@ void Simulator::FlushICache(v8::internal::HashMap* i_cache,
FlushOnePage(i_cache, start, bytes_to_flush);
start += bytes_to_flush;
size -= bytes_to_flush;
- ASSERT_EQ((uint64_t)0, start & CachePage::kPageMask);
+ DCHECK_EQ((uint64_t)0, start & CachePage::kPageMask);
offset = 0;
}
if (size != 0) {
@@ -833,10 +833,10 @@ CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) {
void Simulator::FlushOnePage(v8::internal::HashMap* i_cache,
intptr_t start,
int size) {
- ASSERT(size <= CachePage::kPageSize);
- ASSERT(AllOnOnePage(start, size - 1));
- ASSERT((start & CachePage::kLineMask) == 0);
- ASSERT((size & CachePage::kLineMask) == 0);
+ DCHECK(size <= CachePage::kPageSize);
+ DCHECK(AllOnOnePage(start, size - 1));
+ DCHECK((start & CachePage::kLineMask) == 0);
+ DCHECK((size & CachePage::kLineMask) == 0);
void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
int offset = (start & CachePage::kPageMask);
CachePage* cache_page = GetCachePage(i_cache, page);
@@ -996,8 +996,8 @@ void* Simulator::RedirectExternalReference(void* external_function,
Simulator* Simulator::current(Isolate* isolate) {
v8::internal::Isolate::PerIsolateThreadData* isolate_data =
isolate->FindOrAllocatePerThreadDataForThisThread();
- ASSERT(isolate_data != NULL);
- ASSERT(isolate_data != NULL);
+ DCHECK(isolate_data != NULL);
+ DCHECK(isolate_data != NULL);
Simulator* sim = isolate_data->simulator();
if (sim == NULL) {
@@ -1012,7 +1012,7 @@ Simulator* Simulator::current(Isolate* isolate) {
// Sets the register in the architecture state. It will also deal with updating
// Simulator internal state for special registers such as PC.
void Simulator::set_register(int reg, int64_t value) {
- ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
+ DCHECK((reg >= 0) && (reg < kNumSimuRegisters));
if (reg == pc) {
pc_modified_ = true;
}
@@ -1023,7 +1023,7 @@ void Simulator::set_register(int reg, int64_t value) {
void Simulator::set_dw_register(int reg, const int* dbl) {
- ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
+ DCHECK((reg >= 0) && (reg < kNumSimuRegisters));
registers_[reg] = dbl[1];
registers_[reg] = registers_[reg] << 32;
registers_[reg] += dbl[0];
@@ -1031,7 +1031,7 @@ void Simulator::set_dw_register(int reg, const int* dbl) {
void Simulator::set_fpu_register(int fpureg, int64_t value) {
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
FPUregisters_[fpureg] = value;
}
@@ -1039,7 +1039,7 @@ void Simulator::set_fpu_register(int fpureg, int64_t value) {
void Simulator::set_fpu_register_word(int fpureg, int32_t value) {
// Set ONLY lower 32-bits, leaving upper bits untouched.
// TODO(plind): big endian issue.
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
int32_t *pword = reinterpret_cast<int32_t*>(&FPUregisters_[fpureg]);
*pword = value;
}
@@ -1048,20 +1048,20 @@ void Simulator::set_fpu_register_word(int fpureg, int32_t value) {
void Simulator::set_fpu_register_hi_word(int fpureg, int32_t value) {
// Set ONLY upper 32-bits, leaving lower bits untouched.
// TODO(plind): big endian issue.
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
int32_t *phiword = (reinterpret_cast<int32_t*>(&FPUregisters_[fpureg])) + 1;
*phiword = value;
}
void Simulator::set_fpu_register_float(int fpureg, float value) {
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
*BitCast<float*>(&FPUregisters_[fpureg]) = value;
}
void Simulator::set_fpu_register_double(int fpureg, double value) {
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
*BitCast<double*>(&FPUregisters_[fpureg]) = value;
}
@@ -1069,7 +1069,7 @@ void Simulator::set_fpu_register_double(int fpureg, double value) {
// Get the register from the architecture state. This function does handle
// the special case of accessing the PC register.
int64_t Simulator::get_register(int reg) const {
- ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
+ DCHECK((reg >= 0) && (reg < kNumSimuRegisters));
if (reg == 0)
return 0;
else
@@ -1079,7 +1079,7 @@ int64_t Simulator::get_register(int reg) const {
double Simulator::get_double_from_register_pair(int reg) {
// TODO(plind): bad ABI stuff, refactor or remove.
- ASSERT((reg >= 0) && (reg < kNumSimuRegisters) && ((reg % 2) == 0));
+ DCHECK((reg >= 0) && (reg < kNumSimuRegisters) && ((reg % 2) == 0));
double dm_val = 0.0;
// Read the bits from the unsigned integer register_[] array
@@ -1092,38 +1092,38 @@ double Simulator::get_double_from_register_pair(int reg) {
int64_t Simulator::get_fpu_register(int fpureg) const {
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
return FPUregisters_[fpureg];
}
int32_t Simulator::get_fpu_register_word(int fpureg) const {
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff);
}
int32_t Simulator::get_fpu_register_signed_word(int fpureg) const {
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff);
}
uint32_t Simulator::get_fpu_register_hi_word(int fpureg) const {
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
return static_cast<uint32_t>((FPUregisters_[fpureg] >> 32) & 0xffffffff);
}
float Simulator::get_fpu_register_float(int fpureg) const {
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
return *BitCast<float*>(
const_cast<int64_t*>(&FPUregisters_[fpureg]));
}
double Simulator::get_fpu_register_double(int fpureg) const {
- ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
return *BitCast<double*>(&FPUregisters_[fpureg]);
}
@@ -1856,8 +1856,8 @@ bool Simulator::IsStopInstruction(Instruction* instr) {
bool Simulator::IsEnabledStop(uint64_t code) {
- ASSERT(code <= kMaxStopCode);
- ASSERT(code > kMaxWatchpointCode);
+ DCHECK(code <= kMaxStopCode);
+ DCHECK(code > kMaxWatchpointCode);
return !(watched_stops_[code].count & kStopDisabledBit);
}
@@ -1877,7 +1877,7 @@ void Simulator::DisableStop(uint64_t code) {
void Simulator::IncreaseStopCounter(uint64_t code) {
- ASSERT(code <= kMaxStopCode);
+ DCHECK(code <= kMaxStopCode);
if ((watched_stops_[code].count & ~(1 << 31)) == 0x7fffffff) {
PrintF("Stop counter for code %ld has overflowed.\n"
"Enabling this code and reseting the counter to 0.\n", code);
@@ -1957,7 +1957,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr,
switch (instr->RsFieldRaw()) {
case CFC1:
// At the moment only FCSR is supported.
- ASSERT(fs_reg == kFCSRRegister);
+ DCHECK(fs_reg == kFCSRRegister);
*alu_out = FCSR_;
break;
case MFC1:
@@ -2069,13 +2069,13 @@ void Simulator::ConfigureTypeRegister(Instruction* instr,
break;
case MFHI: // MFHI == CLZ on R6.
if (kArchVariant != kMips64r6) {
- ASSERT(instr->SaValue() == 0);
+ DCHECK(instr->SaValue() == 0);
*alu_out = get_register(HI);
} else {
// MIPS spec: If no bits were set in GPR rs, the result written to
// GPR rd is 32.
// GCC __builtin_clz: If input is 0, the result is undefined.
- ASSERT(instr->SaValue() == 1);
+ DCHECK(instr->SaValue() == 1);
*alu_out =
rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u);
}
@@ -2329,7 +2329,7 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
break;
case CTC1:
// At the moment only FCSR is supported.
- ASSERT(fs_reg == kFCSRRegister);
+ DCHECK(fs_reg == kFCSRRegister);
FCSR_ = registers_[rt_reg];
break;
case MTC1:
@@ -2415,7 +2415,7 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
break;
case CVT_W_D: // Convert double to word.
// Rounding modes are not yet supported.
- ASSERT((FCSR_ & 3) == 0);
+ DCHECK((FCSR_ & 3) == 0);
// In rounding mode 0 it should behave like ROUND.
// No break.
case ROUND_W_D: // Round double to word (round half to even).
@@ -2468,7 +2468,7 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
break;
case CVT_L_D: // Mips64r2: Truncate double to 64-bit long-word.
// Rounding modes are not yet supported.
- ASSERT((FCSR_ & 3) == 0);
+ DCHECK((FCSR_ & 3) == 0);
// In rounding mode 0 it should behave like ROUND.
// No break.
case ROUND_L_D: { // Mips64r2 instruction.
@@ -3356,7 +3356,7 @@ int64_t Simulator::Call(byte* entry, int argument_count, ...) {
// Set up arguments.
// First four arguments passed in registers in both ABI's.
- ASSERT(argument_count >= 4);
+ DCHECK(argument_count >= 4);
set_register(a0, va_arg(parameters, int64_t));
set_register(a1, va_arg(parameters, int64_t));
set_register(a2, va_arg(parameters, int64_t));
@@ -3409,7 +3409,7 @@ double Simulator::CallFP(byte* entry, double d0, double d1) {
set_fpu_register_double(fparg2, d1);
} else {
int buffer[2];
- ASSERT(sizeof(buffer[0]) * 2 == sizeof(d0));
+ DCHECK(sizeof(buffer[0]) * 2 == sizeof(d0));
memcpy(buffer, &d0, sizeof(d0));
set_dw_register(a0, buffer);
memcpy(buffer, &d1, sizeof(d1));
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