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Unified Diff: src/x64/assembler-x64.h

Issue 430503007: Rename ASSERT* to DCHECK*. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: REBASE and fixes Created 6 years, 4 months ago
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Index: src/x64/assembler-x64.h
diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h
index 6f4b7e1a56d1f53bc152e0e6b225af2f2c48617f..06bf8509af279082b1e7be86ac7d1d958e1b62b9 100644
--- a/src/x64/assembler-x64.h
+++ b/src/x64/assembler-x64.h
@@ -84,13 +84,13 @@ struct Register {
}
static Register FromAllocationIndex(int index) {
- ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
+ DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
Register result = { kRegisterCodeByAllocationIndex[index] };
return result;
}
static const char* AllocationIndexToString(int index) {
- ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
+ DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
const char* const names[] = {
"rax",
"rbx",
@@ -116,7 +116,7 @@ struct Register {
// rax, rbx, rcx and rdx are byte registers, the rest are not.
bool is_byte_register() const { return code_ <= 3; }
int code() const {
- ASSERT(is_valid());
+ DCHECK(is_valid());
return code_;
}
int bit() const {
@@ -201,18 +201,18 @@ struct XMMRegister {
}
static int ToAllocationIndex(XMMRegister reg) {
- ASSERT(reg.code() != 0);
+ DCHECK(reg.code() != 0);
return reg.code() - 1;
}
static XMMRegister FromAllocationIndex(int index) {
- ASSERT(0 <= index && index < kMaxNumAllocatableRegisters);
+ DCHECK(0 <= index && index < kMaxNumAllocatableRegisters);
XMMRegister result = { index + 1 };
return result;
}
static const char* AllocationIndexToString(int index) {
- ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
+ DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
const char* const names[] = {
"xmm1",
"xmm2",
@@ -234,15 +234,15 @@ struct XMMRegister {
}
static XMMRegister from_code(int code) {
- ASSERT(code >= 0);
- ASSERT(code < kMaxNumRegisters);
+ DCHECK(code >= 0);
+ DCHECK(code < kMaxNumRegisters);
XMMRegister r = { code };
return r;
}
bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters; }
bool is(XMMRegister reg) const { return code_ == reg.code_; }
int code() const {
- ASSERT(is_valid());
+ DCHECK(is_valid());
return code_;
}
@@ -358,7 +358,7 @@ class Immediate BASE_EMBEDDED {
public:
explicit Immediate(int32_t value) : value_(value) {}
explicit Immediate(Smi* value) {
- ASSERT(SmiValuesAre31Bits()); // Only available for 31-bit SMI.
+ DCHECK(SmiValuesAre31Bits()); // Only available for 31-bit SMI.
value_ = static_cast<int32_t>(reinterpret_cast<intptr_t>(value));
}
@@ -550,7 +550,7 @@ class Assembler : public AssemblerBase {
if (kPointerSize == kInt64Size) {
return RelocInfo::NONE64;
} else {
- ASSERT(kPointerSize == kInt32Size);
+ DCHECK(kPointerSize == kInt32Size);
return RelocInfo::NONE32;
}
}
@@ -1258,7 +1258,7 @@ class Assembler : public AssemblerBase {
if (size == kInt64Size) {
emit_rex_64();
} else {
- ASSERT(size == kInt32Size);
+ DCHECK(size == kInt32Size);
}
}
@@ -1267,7 +1267,7 @@ class Assembler : public AssemblerBase {
if (size == kInt64Size) {
emit_rex_64(p1);
} else {
- ASSERT(size == kInt32Size);
+ DCHECK(size == kInt32Size);
emit_optional_rex_32(p1);
}
}
@@ -1277,7 +1277,7 @@ class Assembler : public AssemblerBase {
if (size == kInt64Size) {
emit_rex_64(p1, p2);
} else {
- ASSERT(size == kInt32Size);
+ DCHECK(size == kInt32Size);
emit_optional_rex_32(p1, p2);
}
}
@@ -1303,7 +1303,7 @@ class Assembler : public AssemblerBase {
// Emit a ModR/M byte with an operation subcode in the reg field and
// a register in the rm_reg field.
void emit_modrm(int code, Register rm_reg) {
- ASSERT(is_uint3(code));
+ DCHECK(is_uint3(code));
emit(0xC0 | code << 3 | rm_reg.low_bits());
}
@@ -1580,7 +1580,7 @@ class EnsureSpace BASE_EMBEDDED {
#ifdef DEBUG
~EnsureSpace() {
int bytes_generated = space_before_ - assembler_->available_space();
- ASSERT(bytes_generated < assembler_->kGap);
+ DCHECK(bytes_generated < assembler_->kGap);
}
#endif
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