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Unified Diff: src/arm/simulator-arm.cc

Issue 430503007: Rename ASSERT* to DCHECK*. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: REBASE and fixes Created 6 years, 4 months ago
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Index: src/arm/simulator-arm.cc
diff --git a/src/arm/simulator-arm.cc b/src/arm/simulator-arm.cc
index 9d1aafacc57ec2d9e9a4c116f34cf96899b82691..ab26e8af13e89663a6d16047dc2df4a852ec28fa 100644
--- a/src/arm/simulator-arm.cc
+++ b/src/arm/simulator-arm.cc
@@ -87,7 +87,7 @@ void ArmDebugger::Stop(Instruction* instr) {
char** msg_address =
reinterpret_cast<char**>(sim_->get_pc() + Instruction::kInstrSize);
char* msg = *msg_address;
- ASSERT(msg != NULL);
+ DCHECK(msg != NULL);
// Update this stop description.
if (isWatchedStop(code) && !watched_stops_[code].desc) {
@@ -608,8 +608,8 @@ void ArmDebugger::Debug() {
static bool ICacheMatch(void* one, void* two) {
- ASSERT((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
- ASSERT((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
+ DCHECK((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
+ DCHECK((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
return one == two;
}
@@ -646,7 +646,7 @@ void Simulator::FlushICache(v8::internal::HashMap* i_cache,
FlushOnePage(i_cache, start, bytes_to_flush);
start += bytes_to_flush;
size -= bytes_to_flush;
- ASSERT_EQ(0, start & CachePage::kPageMask);
+ DCHECK_EQ(0, start & CachePage::kPageMask);
offset = 0;
}
if (size != 0) {
@@ -671,10 +671,10 @@ CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) {
void Simulator::FlushOnePage(v8::internal::HashMap* i_cache,
intptr_t start,
int size) {
- ASSERT(size <= CachePage::kPageSize);
- ASSERT(AllOnOnePage(start, size - 1));
- ASSERT((start & CachePage::kLineMask) == 0);
- ASSERT((size & CachePage::kLineMask) == 0);
+ DCHECK(size <= CachePage::kPageSize);
+ DCHECK(AllOnOnePage(start, size - 1));
+ DCHECK((start & CachePage::kLineMask) == 0);
+ DCHECK((size & CachePage::kLineMask) == 0);
void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
int offset = (start & CachePage::kPageMask);
CachePage* cache_page = GetCachePage(i_cache, page);
@@ -814,7 +814,7 @@ class Redirection {
Redirection* current = isolate->simulator_redirection();
for (; current != NULL; current = current->next_) {
if (current->external_function_ == external_function) {
- ASSERT_EQ(current->type(), type);
+ DCHECK_EQ(current->type(), type);
return current;
}
}
@@ -853,7 +853,7 @@ void* Simulator::RedirectExternalReference(void* external_function,
Simulator* Simulator::current(Isolate* isolate) {
v8::internal::Isolate::PerIsolateThreadData* isolate_data =
isolate->FindOrAllocatePerThreadDataForThisThread();
- ASSERT(isolate_data != NULL);
+ DCHECK(isolate_data != NULL);
Simulator* sim = isolate_data->simulator();
if (sim == NULL) {
@@ -868,7 +868,7 @@ Simulator* Simulator::current(Isolate* isolate) {
// Sets the register in the architecture state. It will also deal with updating
// Simulator internal state for special registers such as PC.
void Simulator::set_register(int reg, int32_t value) {
- ASSERT((reg >= 0) && (reg < num_registers));
+ DCHECK((reg >= 0) && (reg < num_registers));
if (reg == pc) {
pc_modified_ = true;
}
@@ -879,7 +879,7 @@ void Simulator::set_register(int reg, int32_t value) {
// Get the register from the architecture state. This function does handle
// the special case of accessing the PC register.
int32_t Simulator::get_register(int reg) const {
- ASSERT((reg >= 0) && (reg < num_registers));
+ DCHECK((reg >= 0) && (reg < num_registers));
// Stupid code added to avoid bug in GCC.
// See: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43949
if (reg >= num_registers) return 0;
@@ -889,7 +889,7 @@ int32_t Simulator::get_register(int reg) const {
double Simulator::get_double_from_register_pair(int reg) {
- ASSERT((reg >= 0) && (reg < num_registers) && ((reg % 2) == 0));
+ DCHECK((reg >= 0) && (reg < num_registers) && ((reg % 2) == 0));
double dm_val = 0.0;
// Read the bits from the unsigned integer register_[] array
@@ -902,62 +902,62 @@ double Simulator::get_double_from_register_pair(int reg) {
void Simulator::set_register_pair_from_double(int reg, double* value) {
- ASSERT((reg >= 0) && (reg < num_registers) && ((reg % 2) == 0));
+ DCHECK((reg >= 0) && (reg < num_registers) && ((reg % 2) == 0));
memcpy(registers_ + reg, value, sizeof(*value));
}
void Simulator::set_dw_register(int dreg, const int* dbl) {
- ASSERT((dreg >= 0) && (dreg < num_d_registers));
+ DCHECK((dreg >= 0) && (dreg < num_d_registers));
registers_[dreg] = dbl[0];
registers_[dreg + 1] = dbl[1];
}
void Simulator::get_d_register(int dreg, uint64_t* value) {
- ASSERT((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
+ DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value));
}
void Simulator::set_d_register(int dreg, const uint64_t* value) {
- ASSERT((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
+ DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
memcpy(vfp_registers_ + dreg * 2, value, sizeof(*value));
}
void Simulator::get_d_register(int dreg, uint32_t* value) {
- ASSERT((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
+ DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value) * 2);
}
void Simulator::set_d_register(int dreg, const uint32_t* value) {
- ASSERT((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
+ DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
memcpy(vfp_registers_ + dreg * 2, value, sizeof(*value) * 2);
}
void Simulator::get_q_register(int qreg, uint64_t* value) {
- ASSERT((qreg >= 0) && (qreg < num_q_registers));
+ DCHECK((qreg >= 0) && (qreg < num_q_registers));
memcpy(value, vfp_registers_ + qreg * 4, sizeof(*value) * 2);
}
void Simulator::set_q_register(int qreg, const uint64_t* value) {
- ASSERT((qreg >= 0) && (qreg < num_q_registers));
+ DCHECK((qreg >= 0) && (qreg < num_q_registers));
memcpy(vfp_registers_ + qreg * 4, value, sizeof(*value) * 2);
}
void Simulator::get_q_register(int qreg, uint32_t* value) {
- ASSERT((qreg >= 0) && (qreg < num_q_registers));
+ DCHECK((qreg >= 0) && (qreg < num_q_registers));
memcpy(value, vfp_registers_ + qreg * 4, sizeof(*value) * 4);
}
void Simulator::set_q_register(int qreg, const uint32_t* value) {
- ASSERT((qreg >= 0) && (qreg < num_q_registers));
+ DCHECK((qreg >= 0) && (qreg < num_q_registers));
memcpy(vfp_registers_ + qreg * 4, value, sizeof(*value) * 4);
}
@@ -982,22 +982,22 @@ int32_t Simulator::get_pc() const {
// Getting from and setting into VFP registers.
void Simulator::set_s_register(int sreg, unsigned int value) {
- ASSERT((sreg >= 0) && (sreg < num_s_registers));
+ DCHECK((sreg >= 0) && (sreg < num_s_registers));
vfp_registers_[sreg] = value;
}
unsigned int Simulator::get_s_register(int sreg) const {
- ASSERT((sreg >= 0) && (sreg < num_s_registers));
+ DCHECK((sreg >= 0) && (sreg < num_s_registers));
return vfp_registers_[sreg];
}
template<class InputType, int register_size>
void Simulator::SetVFPRegister(int reg_index, const InputType& value) {
- ASSERT(reg_index >= 0);
- if (register_size == 1) ASSERT(reg_index < num_s_registers);
- if (register_size == 2) ASSERT(reg_index < DwVfpRegister::NumRegisters());
+ DCHECK(reg_index >= 0);
+ if (register_size == 1) DCHECK(reg_index < num_s_registers);
+ if (register_size == 2) DCHECK(reg_index < DwVfpRegister::NumRegisters());
char buffer[register_size * sizeof(vfp_registers_[0])];
memcpy(buffer, &value, register_size * sizeof(vfp_registers_[0]));
@@ -1008,9 +1008,9 @@ void Simulator::SetVFPRegister(int reg_index, const InputType& value) {
template<class ReturnType, int register_size>
ReturnType Simulator::GetFromVFPRegister(int reg_index) {
- ASSERT(reg_index >= 0);
- if (register_size == 1) ASSERT(reg_index < num_s_registers);
- if (register_size == 2) ASSERT(reg_index < DwVfpRegister::NumRegisters());
+ DCHECK(reg_index >= 0);
+ if (register_size == 1) DCHECK(reg_index < num_s_registers);
+ if (register_size == 2) DCHECK(reg_index < DwVfpRegister::NumRegisters());
ReturnType value = 0;
char buffer[register_size * sizeof(vfp_registers_[0])];
@@ -1430,7 +1430,7 @@ int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
*carry_out = (result & 1) == 1;
result >>= 1;
} else {
- ASSERT(shift_amount >= 32);
+ DCHECK(shift_amount >= 32);
if (result < 0) {
*carry_out = true;
result = 0xffffffff;
@@ -1453,7 +1453,7 @@ int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
*carry_out = (result & 1) == 1;
result = 0;
} else {
- ASSERT(shift_amount > 32);
+ DCHECK(shift_amount > 32);
*carry_out = false;
result = 0;
}
@@ -1575,7 +1575,7 @@ void Simulator::HandleRList(Instruction* instr, bool load) {
intptr_t* address = reinterpret_cast<intptr_t*>(start_address);
// Catch null pointers a little earlier.
- ASSERT(start_address > 8191 || start_address < 0);
+ DCHECK(start_address > 8191 || start_address < 0);
int reg = 0;
while (rlist != 0) {
if ((rlist & 1) != 0) {
@@ -1589,7 +1589,7 @@ void Simulator::HandleRList(Instruction* instr, bool load) {
reg++;
rlist >>= 1;
}
- ASSERT(end_address == ((intptr_t)address) - 4);
+ DCHECK(end_address == ((intptr_t)address) - 4);
if (instr->HasW()) {
set_register(instr->RnValue(), rn_val);
}
@@ -1648,7 +1648,7 @@ void Simulator::HandleVList(Instruction* instr) {
address += 2;
}
}
- ASSERT(reinterpret_cast<intptr_t>(address) - operand_size == end_address);
+ DCHECK(reinterpret_cast<intptr_t>(address) - operand_size == end_address);
if (instr->HasW()) {
set_register(instr->RnValue(), rn_val);
}
@@ -1853,7 +1853,7 @@ void Simulator::SoftwareInterrupt(Instruction* instr) {
target(arg0, arg1, Redirection::ReverseRedirection(arg2));
} else {
// builtin call.
- ASSERT(redirection->type() == ExternalReference::BUILTIN_CALL);
+ DCHECK(redirection->type() == ExternalReference::BUILTIN_CALL);
SimulatorRuntimeCall target =
reinterpret_cast<SimulatorRuntimeCall>(external);
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
@@ -1929,13 +1929,13 @@ bool Simulator::isStopInstruction(Instruction* instr) {
bool Simulator::isWatchedStop(uint32_t code) {
- ASSERT(code <= kMaxStopCode);
+ DCHECK(code <= kMaxStopCode);
return code < kNumOfWatchedStops;
}
bool Simulator::isEnabledStop(uint32_t code) {
- ASSERT(code <= kMaxStopCode);
+ DCHECK(code <= kMaxStopCode);
// Unwatched stops are always enabled.
return !isWatchedStop(code) ||
!(watched_stops_[code].count & kStopDisabledBit);
@@ -1943,7 +1943,7 @@ bool Simulator::isEnabledStop(uint32_t code) {
void Simulator::EnableStop(uint32_t code) {
- ASSERT(isWatchedStop(code));
+ DCHECK(isWatchedStop(code));
if (!isEnabledStop(code)) {
watched_stops_[code].count &= ~kStopDisabledBit;
}
@@ -1951,7 +1951,7 @@ void Simulator::EnableStop(uint32_t code) {
void Simulator::DisableStop(uint32_t code) {
- ASSERT(isWatchedStop(code));
+ DCHECK(isWatchedStop(code));
if (isEnabledStop(code)) {
watched_stops_[code].count |= kStopDisabledBit;
}
@@ -1959,8 +1959,8 @@ void Simulator::DisableStop(uint32_t code) {
void Simulator::IncreaseStopCounter(uint32_t code) {
- ASSERT(code <= kMaxStopCode);
- ASSERT(isWatchedStop(code));
+ DCHECK(code <= kMaxStopCode);
+ DCHECK(isWatchedStop(code));
if ((watched_stops_[code].count & ~(1 << 31)) == 0x7fffffff) {
PrintF("Stop counter for code %i has overflowed.\n"
"Enabling this code and reseting the counter to 0.\n", code);
@@ -1974,7 +1974,7 @@ void Simulator::IncreaseStopCounter(uint32_t code) {
// Print a stop status.
void Simulator::PrintStopInfo(uint32_t code) {
- ASSERT(code <= kMaxStopCode);
+ DCHECK(code <= kMaxStopCode);
if (!isWatchedStop(code)) {
PrintF("Stop not watched.");
} else {
@@ -2092,7 +2092,7 @@ void Simulator::DecodeType01(Instruction* instr) {
switch (instr->PUField()) {
case da_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
- ASSERT(!instr->HasW());
+ DCHECK(!instr->HasW());
addr = rn_val;
rn_val -= rm_val;
set_register(rn, rn_val);
@@ -2100,7 +2100,7 @@ void Simulator::DecodeType01(Instruction* instr) {
}
case ia_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
- ASSERT(!instr->HasW());
+ DCHECK(!instr->HasW());
addr = rn_val;
rn_val += rm_val;
set_register(rn, rn_val);
@@ -2135,7 +2135,7 @@ void Simulator::DecodeType01(Instruction* instr) {
switch (instr->PUField()) {
case da_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
- ASSERT(!instr->HasW());
+ DCHECK(!instr->HasW());
addr = rn_val;
rn_val -= imm_val;
set_register(rn, rn_val);
@@ -2143,7 +2143,7 @@ void Simulator::DecodeType01(Instruction* instr) {
}
case ia_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
- ASSERT(!instr->HasW());
+ DCHECK(!instr->HasW());
addr = rn_val;
rn_val += imm_val;
set_register(rn, rn_val);
@@ -2175,7 +2175,7 @@ void Simulator::DecodeType01(Instruction* instr) {
}
}
if (((instr->Bits(7, 4) & 0xd) == 0xd) && (instr->Bit(20) == 0)) {
- ASSERT((rd % 2) == 0);
+ DCHECK((rd % 2) == 0);
if (instr->HasH()) {
// The strd instruction.
int32_t value1 = get_register(rd);
@@ -2206,8 +2206,8 @@ void Simulator::DecodeType01(Instruction* instr) {
}
} else {
// signed byte loads
- ASSERT(instr->HasSign());
- ASSERT(instr->HasL());
+ DCHECK(instr->HasSign());
+ DCHECK(instr->HasL());
int8_t val = ReadB(addr);
set_register(rd, val);
}
@@ -2271,7 +2271,7 @@ void Simulator::DecodeType01(Instruction* instr) {
if (type == 0) {
shifter_operand = GetShiftRm(instr, &shifter_carry_out);
} else {
- ASSERT(instr->TypeValue() == 1);
+ DCHECK(instr->TypeValue() == 1);
shifter_operand = GetImm(instr, &shifter_carry_out);
}
int32_t alu_out;
@@ -2494,7 +2494,7 @@ void Simulator::DecodeType2(Instruction* instr) {
switch (instr->PUField()) {
case da_x: {
// Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
- ASSERT(!instr->HasW());
+ DCHECK(!instr->HasW());
addr = rn_val;
rn_val -= im_val;
set_register(rn, rn_val);
@@ -2502,7 +2502,7 @@ void Simulator::DecodeType2(Instruction* instr) {
}
case ia_x: {
// Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
- ASSERT(!instr->HasW());
+ DCHECK(!instr->HasW());
addr = rn_val;
rn_val += im_val;
set_register(rn, rn_val);
@@ -2558,7 +2558,7 @@ void Simulator::DecodeType3(Instruction* instr) {
int32_t addr = 0;
switch (instr->PUField()) {
case da_x: {
- ASSERT(!instr->HasW());
+ DCHECK(!instr->HasW());
Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
UNIMPLEMENTED();
break;
@@ -2720,7 +2720,7 @@ void Simulator::DecodeType3(Instruction* instr) {
int rs = instr->RsValue();
int32_t rs_val = get_register(rs);
int32_t ret_val = 0;
- ASSERT(rs_val != 0);
+ DCHECK(rs_val != 0);
// udiv
if (instr->Bit(21) == 0x1) {
ret_val = static_cast<int32_t>(static_cast<uint32_t>(rm_val) /
@@ -2821,7 +2821,7 @@ void Simulator::DecodeType3(Instruction* instr) {
void Simulator::DecodeType4(Instruction* instr) {
- ASSERT(instr->Bit(22) == 0); // only allowed to be set in privileged mode
+ DCHECK(instr->Bit(22) == 0); // only allowed to be set in privileged mode
if (instr->HasL()) {
// Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
HandleRList(instr, true);
@@ -2875,8 +2875,8 @@ void Simulator::DecodeType7(Instruction* instr) {
// vmrs
// Dd = vsqrt(Dm)
void Simulator::DecodeTypeVFP(Instruction* instr) {
- ASSERT((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
- ASSERT(instr->Bits(11, 9) == 0x5);
+ DCHECK((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
+ DCHECK(instr->Bits(11, 9) == 0x5);
// Obtain double precision register codes.
int vm = instr->VFPMRegValue(kDoublePrecision);
@@ -3091,7 +3091,7 @@ void Simulator::DecodeTypeVFP(Instruction* instr) {
void Simulator::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(
Instruction* instr) {
- ASSERT((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
+ DCHECK((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
(instr->VAValue() == 0x0));
int t = instr->RtValue();
@@ -3109,8 +3109,8 @@ void Simulator::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(
void Simulator::DecodeVCMP(Instruction* instr) {
- ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
- ASSERT(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
+ DCHECK((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
+ DCHECK(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
(instr->Opc3Value() & 0x1));
// Comparison.
@@ -3147,8 +3147,8 @@ void Simulator::DecodeVCMP(Instruction* instr) {
void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
- ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
- ASSERT((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
+ DCHECK((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
+ DCHECK((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
VFPRegPrecision dst_precision = kDoublePrecision;
VFPRegPrecision src_precision = kSinglePrecision;
@@ -3172,7 +3172,7 @@ void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
bool get_inv_op_vfp_flag(VFPRoundingMode mode,
double val,
bool unsigned_) {
- ASSERT((mode == RN) || (mode == RM) || (mode == RZ));
+ DCHECK((mode == RN) || (mode == RM) || (mode == RZ));
double max_uint = static_cast<double>(0xffffffffu);
double max_int = static_cast<double>(kMaxInt);
double min_int = static_cast<double>(kMinInt);
@@ -3225,9 +3225,9 @@ int VFPConversionSaturate(double val, bool unsigned_res) {
void Simulator::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
- ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7) &&
+ DCHECK((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7) &&
(instr->Bits(27, 23) == 0x1D));
- ASSERT(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
+ DCHECK(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
(((instr->Opc2Value() >> 1) == 0x6) && (instr->Opc3Value() & 0x1)));
// Conversion between floating-point and integer.
@@ -3251,7 +3251,7 @@ void Simulator::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
// mode or the default Round to Zero mode.
VFPRoundingMode mode = (instr->Bit(7) != 1) ? FPSCR_rounding_mode_
: RZ;
- ASSERT((mode == RM) || (mode == RZ) || (mode == RN));
+ DCHECK((mode == RM) || (mode == RZ) || (mode == RN));
bool unsigned_integer = (instr->Bit(16) == 0);
bool double_precision = (src_precision == kDoublePrecision);
@@ -3335,7 +3335,7 @@ void Simulator::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
// Ddst = MEM(Rbase + 4*offset).
// MEM(Rbase + 4*offset) = Dsrc.
void Simulator::DecodeType6CoprocessorIns(Instruction* instr) {
- ASSERT((instr->TypeValue() == 6));
+ DCHECK((instr->TypeValue() == 6));
if (instr->CoprocessorValue() == 0xA) {
switch (instr->OpcodeValue()) {
@@ -3756,7 +3756,7 @@ int32_t Simulator::Call(byte* entry, int argument_count, ...) {
// Set up arguments
// First four arguments passed in registers.
- ASSERT(argument_count >= 4);
+ DCHECK(argument_count >= 4);
set_register(r0, va_arg(parameters, int32_t));
set_register(r1, va_arg(parameters, int32_t));
set_register(r2, va_arg(parameters, int32_t));
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