Rename ASSERT* to DCHECK*.

test/cctest/test-assembler-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 40 matching lines @@
 //
 //   TEST(mov_x0_one) {
 //     SETUP();
 //
 //     START();
 //     __ mov(x0, Operand(1));
 //     END();
 //
 //     RUN();
 //
-//     ASSERT_EQUAL_64(1, x0);
+//     CHECK_EQUAL_64(1, x0);
 //
 //     TEARDOWN();
 //   }
 //
 // Within a START ... END block all registers but sp can be modified. sp has to
 // be explicitly saved/restored. The END() macro replaces the function return
 // so it may appear multiple times in a test if the test has multiple exit
 // points.
 //
 // Once the test has been run all integer and floating point registers as well
 // as flags are accessible through a RegisterDump instance, see
 // utils-arm64.cc for more info on RegisterDump.
 //
 // We provide some helper assert to handle common cases:
 //
-//   ASSERT_EQUAL_32(int32_t, int_32t)
-//   ASSERT_EQUAL_FP32(float, float)
-//   ASSERT_EQUAL_32(int32_t, W register)
-//   ASSERT_EQUAL_FP32(float, S register)
-//   ASSERT_EQUAL_64(int64_t, int_64t)
-//   ASSERT_EQUAL_FP64(double, double)
-//   ASSERT_EQUAL_64(int64_t, X register)
-//   ASSERT_EQUAL_64(X register, X register)
-//   ASSERT_EQUAL_FP64(double, D register)
+//   CHECK_EQUAL_32(int32_t, int_32t)
+//   CHECK_EQUAL_FP32(float, float)
+//   CHECK_EQUAL_32(int32_t, W register)
+//   CHECK_EQUAL_FP32(float, S register)
+//   CHECK_EQUAL_64(int64_t, int_64t)
+//   CHECK_EQUAL_FP64(double, double)
+//   CHECK_EQUAL_64(int64_t, X register)
+//   CHECK_EQUAL_64(X register, X register)
+//   CHECK_EQUAL_FP64(double, D register)
 //
-// e.g. ASSERT_EQUAL_64(0.5, d30);
+// e.g. CHECK_EQUAL_64(0.5, d30);
 //
 // If more advance computation is required before the assert then access the
 // RegisterDump named core directly:
 //
-//   ASSERT_EQUAL_64(0x1234, core.xreg(0) & 0xffff);
+//   CHECK_EQUAL_64(0x1234, core.xreg(0) & 0xffff);
 
 
 #if 0  // TODO(all): enable.
 static v8::Persistent<v8::Context> env;
 
 static void InitializeVM() {
   if (env.IsEmpty()) {
     env = v8::Context::New();
   }
 }
 #endif
 
 #define __ masm.
 
 #define BUF_SIZE 8192
 #define SETUP() SETUP_SIZE(BUF_SIZE)
 
 #define INIT_V8()                                                              \
   CcTest::InitializeVM();                                                      \
 
 #ifdef USE_SIMULATOR
 
 // Run tests with the simulator.
 #define SETUP_SIZE(buf_size)                    \
   Isolate* isolate = Isolate::Current();        \
   HandleScope scope(isolate);                   \
-  ASSERT(isolate != NULL);                      \
+  DCHECK(isolate != NULL);                      \
   byte* buf = new byte[buf_size];               \
   MacroAssembler masm(isolate, buf, buf_size);  \
   Decoder<DispatchingDecoderVisitor>* decoder = \
       new Decoder<DispatchingDecoderVisitor>(); \
   Simulator simulator(decoder);                 \
   PrintDisassembler* pdis = NULL;               \
   RegisterDump core;
 
 /*  if (Cctest::trace_sim()) {                                                 \
     pdis = new PrintDisassembler(stdout);                                      \
@@ skipping 33 matching lines @@
 
 #define TEARDOWN()                                                             \
   delete pdis;                                                                 \
   delete[] buf;
 
 #else  // ifdef USE_SIMULATOR.
 // Run the test on real hardware or models.
 #define SETUP_SIZE(buf_size)                                                   \
   Isolate* isolate = Isolate::Current();                                       \
   HandleScope scope(isolate);                                                  \
-  ASSERT(isolate != NULL);                                                     \
+  DCHECK(isolate != NULL);                                                     \
   byte* buf = new byte[buf_size];                                              \
   MacroAssembler masm(isolate, buf, buf_size);                                 \
   RegisterDump core;
 
 #define RESET()                                                                \
   __ Reset();                                                                  \
   /* Reset the machine state (like simulator.ResetState()). */                 \
   __ Msr(NZCV, xzr);                                                           \
   __ Msr(FPCR, xzr);
 
@@ skipping 18 matching lines @@
   core.Dump(&masm);                                                            \
   __ PopCalleeSavedRegisters();                                                \
   __ Ret();                                                                    \
   __ GetCode(NULL);
 
 #define TEARDOWN()                                                             \
   delete[] buf;
 
 #endif  // ifdef USE_SIMULATOR.
 
-#define ASSERT_EQUAL_NZCV(expected)                                            \
+#define CHECK_EQUAL_NZCV(expected)                                            \
   CHECK(EqualNzcv(expected, core.flags_nzcv()))
 
-#define ASSERT_EQUAL_REGISTERS(expected)                                       \
+#define CHECK_EQUAL_REGISTERS(expected)                                       \
   CHECK(EqualRegisters(&expected, &core))
 
-#define ASSERT_EQUAL_32(expected, result)                                      \
+#define CHECK_EQUAL_32(expected, result)                                      \
   CHECK(Equal32(static_cast<uint32_t>(expected), &core, result))
 
-#define ASSERT_EQUAL_FP32(expected, result)                                    \
+#define CHECK_EQUAL_FP32(expected, result)                                    \
   CHECK(EqualFP32(expected, &core, result))
 
-#define ASSERT_EQUAL_64(expected, result)                                      \
+#define CHECK_EQUAL_64(expected, result)                                      \
   CHECK(Equal64(expected, &core, result))
 
-#define ASSERT_EQUAL_FP64(expected, result)                                    \
+#define CHECK_EQUAL_FP64(expected, result)                                    \
   CHECK(EqualFP64(expected, &core, result))
 
 #ifdef DEBUG
-#define ASSERT_LITERAL_POOL_SIZE(expected)                                     \
+#define DCHECK_LITERAL_POOL_SIZE(expected)                                     \
   CHECK((expected) == (__ LiteralPoolSize()))
 #else
-#define ASSERT_LITERAL_POOL_SIZE(expected)                                     \
+#define DCHECK_LITERAL_POOL_SIZE(expected)                                     \
   ((void) 0)
 #endif
 
 
 TEST(stack_ops) {
   INIT_V8();
   SETUP();
 
   START();
   // save csp.
@@ skipping 24 matching lines @@
   // Write csp, and read back wcsp.
   __ Orr(csp, xzr, Operand(0xfffffff8L));
   __ Mov(w5, wcsp);
 
   //  restore csp.
   __ Mov(csp, x29);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1000, x0);
-  ASSERT_EQUAL_64(0x1050, x1);
-  ASSERT_EQUAL_64(0x104f, x2);
-  ASSERT_EQUAL_64(0x1fff, x3);
-  ASSERT_EQUAL_64(0xfffffff8, x4);
-  ASSERT_EQUAL_64(0xfffffff8, x5);
+  CHECK_EQUAL_64(0x1000, x0);
+  CHECK_EQUAL_64(0x1050, x1);
+  CHECK_EQUAL_64(0x104f, x2);
+  CHECK_EQUAL_64(0x1fff, x3);
+  CHECK_EQUAL_64(0xfffffff8, x4);
+  CHECK_EQUAL_64(0xfffffff8, x5);
 
   TEARDOWN();
 }
 
 
 TEST(mvn) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 10 matching lines @@
   __ Mvn(w10, Operand(w2, UXTB));
   __ Mvn(x11, Operand(x2, SXTB, 1));
   __ Mvn(w12, Operand(w2, UXTH, 2));
   __ Mvn(x13, Operand(x2, SXTH, 3));
   __ Mvn(x14, Operand(w2, UXTW, 4));
   __ Mvn(x15, Operand(w2, SXTW, 4));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xfffff000, x0);
-  ASSERT_EQUAL_64(0xfffffffffffff000UL, x1);
-  ASSERT_EQUAL_64(0x00001fff, x2);
-  ASSERT_EQUAL_64(0x0000000000003fffUL, x3);
-  ASSERT_EQUAL_64(0xe00001ff, x4);
-  ASSERT_EQUAL_64(0xf0000000000000ffUL, x5);
-  ASSERT_EQUAL_64(0x00000001, x6);
-  ASSERT_EQUAL_64(0x0, x7);
-  ASSERT_EQUAL_64(0x7ff80000, x8);
-  ASSERT_EQUAL_64(0x3ffc000000000000UL, x9);
-  ASSERT_EQUAL_64(0xffffff00, x10);
-  ASSERT_EQUAL_64(0x0000000000000001UL, x11);
-  ASSERT_EQUAL_64(0xffff8003, x12);
-  ASSERT_EQUAL_64(0xffffffffffff0007UL, x13);
-  ASSERT_EQUAL_64(0xfffffffffffe000fUL, x14);
-  ASSERT_EQUAL_64(0xfffffffffffe000fUL, x15);
+  CHECK_EQUAL_64(0xfffff000, x0);
+  CHECK_EQUAL_64(0xfffffffffffff000UL, x1);
+  CHECK_EQUAL_64(0x00001fff, x2);
+  CHECK_EQUAL_64(0x0000000000003fffUL, x3);
+  CHECK_EQUAL_64(0xe00001ff, x4);
+  CHECK_EQUAL_64(0xf0000000000000ffUL, x5);
+  CHECK_EQUAL_64(0x00000001, x6);
+  CHECK_EQUAL_64(0x0, x7);
+  CHECK_EQUAL_64(0x7ff80000, x8);
+  CHECK_EQUAL_64(0x3ffc000000000000UL, x9);
+  CHECK_EQUAL_64(0xffffff00, x10);
+  CHECK_EQUAL_64(0x0000000000000001UL, x11);
+  CHECK_EQUAL_64(0xffff8003, x12);
+  CHECK_EQUAL_64(0xffffffffffff0007UL, x13);
+  CHECK_EQUAL_64(0xfffffffffffe000fUL, x14);
+  CHECK_EQUAL_64(0xfffffffffffe000fUL, x15);
 
   TEARDOWN();
 }
 
 
 TEST(mov) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 36 matching lines @@
   __ Mov(x22, Operand(x12, ROR, 14));
   __ Mov(w23, Operand(w13, UXTB));
   __ Mov(x24, Operand(x13, SXTB, 1));
   __ Mov(w25, Operand(w13, UXTH, 2));
   __ Mov(x26, Operand(x13, SXTH, 3));
   __ Mov(x27, Operand(w13, UXTW, 4));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x0123456789abcdefL, x0);
-  ASSERT_EQUAL_64(0x00000000abcd0000L, x1);
-  ASSERT_EQUAL_64(0xffffabcdffffffffL, x2);
-  ASSERT_EQUAL_64(0x5432ffffffffffffL, x3);
-  ASSERT_EQUAL_64(x4, x5);
-  ASSERT_EQUAL_32(-1, w6);
-  ASSERT_EQUAL_64(0x0123456789abcdefL, x7);
-  ASSERT_EQUAL_32(0x89abcdefL, w8);
-  ASSERT_EQUAL_64(0x0123456789abcdefL, x9);
-  ASSERT_EQUAL_32(0x89abcdefL, w10);
-  ASSERT_EQUAL_64(0x00000fff, x11);
-  ASSERT_EQUAL_64(0x0000000000000fffUL, x12);
-  ASSERT_EQUAL_64(0x00001ffe, x13);
-  ASSERT_EQUAL_64(0x0000000000003ffcUL, x14);
-  ASSERT_EQUAL_64(0x000001ff, x15);
-  ASSERT_EQUAL_64(0x00000000000000ffUL, x18);
-  ASSERT_EQUAL_64(0x00000001, x19);
-  ASSERT_EQUAL_64(0x0, x20);
-  ASSERT_EQUAL_64(0x7ff80000, x21);
-  ASSERT_EQUAL_64(0x3ffc000000000000UL, x22);
-  ASSERT_EQUAL_64(0x000000fe, x23);
-  ASSERT_EQUAL_64(0xfffffffffffffffcUL, x24);
-  ASSERT_EQUAL_64(0x00007ff8, x25);
-  ASSERT_EQUAL_64(0x000000000000fff0UL, x26);
-  ASSERT_EQUAL_64(0x000000000001ffe0UL, x27);
+  CHECK_EQUAL_64(0x0123456789abcdefL, x0);
+  CHECK_EQUAL_64(0x00000000abcd0000L, x1);
+  CHECK_EQUAL_64(0xffffabcdffffffffL, x2);
+  CHECK_EQUAL_64(0x5432ffffffffffffL, x3);
+  CHECK_EQUAL_64(x4, x5);
+  CHECK_EQUAL_32(-1, w6);
+  CHECK_EQUAL_64(0x0123456789abcdefL, x7);
+  CHECK_EQUAL_32(0x89abcdefL, w8);
+  CHECK_EQUAL_64(0x0123456789abcdefL, x9);
+  CHECK_EQUAL_32(0x89abcdefL, w10);
+  CHECK_EQUAL_64(0x00000fff, x11);
+  CHECK_EQUAL_64(0x0000000000000fffUL, x12);
+  CHECK_EQUAL_64(0x00001ffe, x13);
+  CHECK_EQUAL_64(0x0000000000003ffcUL, x14);
+  CHECK_EQUAL_64(0x000001ff, x15);
+  CHECK_EQUAL_64(0x00000000000000ffUL, x18);
+  CHECK_EQUAL_64(0x00000001, x19);
+  CHECK_EQUAL_64(0x0, x20);
+  CHECK_EQUAL_64(0x7ff80000, x21);
+  CHECK_EQUAL_64(0x3ffc000000000000UL, x22);
+  CHECK_EQUAL_64(0x000000fe, x23);
+  CHECK_EQUAL_64(0xfffffffffffffffcUL, x24);
+  CHECK_EQUAL_64(0x00007ff8, x25);
+  CHECK_EQUAL_64(0x000000000000fff0UL, x26);
+  CHECK_EQUAL_64(0x000000000001ffe0UL, x27);
 
   TEARDOWN();
 }
 
 
 TEST(mov_imm_w) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(w0, 0xffffffffL);
   __ Mov(w1, 0xffff1234L);
   __ Mov(w2, 0x1234ffffL);
   __ Mov(w3, 0x00000000L);
   __ Mov(w4, 0x00001234L);
   __ Mov(w5, 0x12340000L);
   __ Mov(w6, 0x12345678L);
   __ Mov(w7, (int32_t)0x80000000);
   __ Mov(w8, (int32_t)0xffff0000);
   __ Mov(w9, kWMinInt);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffffffL, x0);
-  ASSERT_EQUAL_64(0xffff1234L, x1);
-  ASSERT_EQUAL_64(0x1234ffffL, x2);
-  ASSERT_EQUAL_64(0x00000000L, x3);
-  ASSERT_EQUAL_64(0x00001234L, x4);
-  ASSERT_EQUAL_64(0x12340000L, x5);
-  ASSERT_EQUAL_64(0x12345678L, x6);
-  ASSERT_EQUAL_64(0x80000000L, x7);
-  ASSERT_EQUAL_64(0xffff0000L, x8);
-  ASSERT_EQUAL_32(kWMinInt, w9);
+  CHECK_EQUAL_64(0xffffffffL, x0);
+  CHECK_EQUAL_64(0xffff1234L, x1);
+  CHECK_EQUAL_64(0x1234ffffL, x2);
+  CHECK_EQUAL_64(0x00000000L, x3);
+  CHECK_EQUAL_64(0x00001234L, x4);
+  CHECK_EQUAL_64(0x12340000L, x5);
+  CHECK_EQUAL_64(0x12345678L, x6);
+  CHECK_EQUAL_64(0x80000000L, x7);
+  CHECK_EQUAL_64(0xffff0000L, x8);
+  CHECK_EQUAL_32(kWMinInt, w9);
 
   TEARDOWN();
 }
 
 
 TEST(mov_imm_x) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 21 matching lines @@
   __ Mov(x23, 0x1234567800009abcL);
   __ Mov(x24, 0x1234000056789abcL);
   __ Mov(x25, 0x0000123456789abcL);
   __ Mov(x26, 0x123456789abcdef0L);
   __ Mov(x27, 0xffff000000000001L);
   __ Mov(x28, 0x8000ffff00000000L);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffffffffff1234L, x1);
-  ASSERT_EQUAL_64(0xffffffff12345678L, x2);
-  ASSERT_EQUAL_64(0xffff1234ffff5678L, x3);
-  ASSERT_EQUAL_64(0x1234ffffffff5678L, x4);
-  ASSERT_EQUAL_64(0x1234ffff5678ffffL, x5);
-  ASSERT_EQUAL_64(0x12345678ffffffffL, x6);
-  ASSERT_EQUAL_64(0x1234ffffffffffffL, x7);
-  ASSERT_EQUAL_64(0x123456789abcffffL, x8);
-  ASSERT_EQUAL_64(0x12345678ffff9abcL, x9);
-  ASSERT_EQUAL_64(0x1234ffff56789abcL, x10);
-  ASSERT_EQUAL_64(0xffff123456789abcL, x11);
-  ASSERT_EQUAL_64(0x0000000000000000L, x12);
-  ASSERT_EQUAL_64(0x0000000000001234L, x13);
-  ASSERT_EQUAL_64(0x0000000012345678L, x14);
-  ASSERT_EQUAL_64(0x0000123400005678L, x15);
-  ASSERT_EQUAL_64(0x1234000000005678L, x18);
-  ASSERT_EQUAL_64(0x1234000056780000L, x19);
-  ASSERT_EQUAL_64(0x1234567800000000L, x20);
-  ASSERT_EQUAL_64(0x1234000000000000L, x21);
-  ASSERT_EQUAL_64(0x123456789abc0000L, x22);
-  ASSERT_EQUAL_64(0x1234567800009abcL, x23);
-  ASSERT_EQUAL_64(0x1234000056789abcL, x24);
-  ASSERT_EQUAL_64(0x0000123456789abcL, x25);
-  ASSERT_EQUAL_64(0x123456789abcdef0L, x26);
-  ASSERT_EQUAL_64(0xffff000000000001L, x27);
-  ASSERT_EQUAL_64(0x8000ffff00000000L, x28);
+  CHECK_EQUAL_64(0xffffffffffff1234L, x1);
+  CHECK_EQUAL_64(0xffffffff12345678L, x2);
+  CHECK_EQUAL_64(0xffff1234ffff5678L, x3);
+  CHECK_EQUAL_64(0x1234ffffffff5678L, x4);
+  CHECK_EQUAL_64(0x1234ffff5678ffffL, x5);
+  CHECK_EQUAL_64(0x12345678ffffffffL, x6);
+  CHECK_EQUAL_64(0x1234ffffffffffffL, x7);
+  CHECK_EQUAL_64(0x123456789abcffffL, x8);
+  CHECK_EQUAL_64(0x12345678ffff9abcL, x9);
+  CHECK_EQUAL_64(0x1234ffff56789abcL, x10);
+  CHECK_EQUAL_64(0xffff123456789abcL, x11);
+  CHECK_EQUAL_64(0x0000000000000000L, x12);
+  CHECK_EQUAL_64(0x0000000000001234L, x13);
+  CHECK_EQUAL_64(0x0000000012345678L, x14);
+  CHECK_EQUAL_64(0x0000123400005678L, x15);
+  CHECK_EQUAL_64(0x1234000000005678L, x18);
+  CHECK_EQUAL_64(0x1234000056780000L, x19);
+  CHECK_EQUAL_64(0x1234567800000000L, x20);
+  CHECK_EQUAL_64(0x1234000000000000L, x21);
+  CHECK_EQUAL_64(0x123456789abc0000L, x22);
+  CHECK_EQUAL_64(0x1234567800009abcL, x23);
+  CHECK_EQUAL_64(0x1234000056789abcL, x24);
+  CHECK_EQUAL_64(0x0000123456789abcL, x25);
+  CHECK_EQUAL_64(0x123456789abcdef0L, x26);
+  CHECK_EQUAL_64(0xffff000000000001L, x27);
+  CHECK_EQUAL_64(0x8000ffff00000000L, x28);
 
   TEARDOWN();
 }
 
 
 TEST(orr) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0xf0f0);
   __ Mov(x1, 0xf00000ff);
 
   __ Orr(x2, x0, Operand(x1));
   __ Orr(w3, w0, Operand(w1, LSL, 28));
   __ Orr(x4, x0, Operand(x1, LSL, 32));
   __ Orr(x5, x0, Operand(x1, LSR, 4));
   __ Orr(w6, w0, Operand(w1, ASR, 4));
   __ Orr(x7, x0, Operand(x1, ASR, 4));
   __ Orr(w8, w0, Operand(w1, ROR, 12));
   __ Orr(x9, x0, Operand(x1, ROR, 12));
   __ Orr(w10, w0, Operand(0xf));
   __ Orr(x11, x0, Operand(0xf0000000f0000000L));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xf000f0ff, x2);
-  ASSERT_EQUAL_64(0xf000f0f0, x3);
-  ASSERT_EQUAL_64(0xf00000ff0000f0f0L, x4);
-  ASSERT_EQUAL_64(0x0f00f0ff, x5);
-  ASSERT_EQUAL_64(0xff00f0ff, x6);
-  ASSERT_EQUAL_64(0x0f00f0ff, x7);
-  ASSERT_EQUAL_64(0x0ffff0f0, x8);
-  ASSERT_EQUAL_64(0x0ff00000000ff0f0L, x9);
-  ASSERT_EQUAL_64(0xf0ff, x10);
-  ASSERT_EQUAL_64(0xf0000000f000f0f0L, x11);
+  CHECK_EQUAL_64(0xf000f0ff, x2);
+  CHECK_EQUAL_64(0xf000f0f0, x3);
+  CHECK_EQUAL_64(0xf00000ff0000f0f0L, x4);
+  CHECK_EQUAL_64(0x0f00f0ff, x5);
+  CHECK_EQUAL_64(0xff00f0ff, x6);
+  CHECK_EQUAL_64(0x0f00f0ff, x7);
+  CHECK_EQUAL_64(0x0ffff0f0, x8);
+  CHECK_EQUAL_64(0x0ff00000000ff0f0L, x9);
+  CHECK_EQUAL_64(0xf0ff, x10);
+  CHECK_EQUAL_64(0xf0000000f000f0f0L, x11);
 
   TEARDOWN();
 }
 
 
 TEST(orr_extend) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 1);
   __ Mov(x1, 0x8000000080008080UL);
   __ Orr(w6, w0, Operand(w1, UXTB));
   __ Orr(x7, x0, Operand(x1, UXTH, 1));
   __ Orr(w8, w0, Operand(w1, UXTW, 2));
   __ Orr(x9, x0, Operand(x1, UXTX, 3));
   __ Orr(w10, w0, Operand(w1, SXTB));
   __ Orr(x11, x0, Operand(x1, SXTH, 1));
   __ Orr(x12, x0, Operand(x1, SXTW, 2));
   __ Orr(x13, x0, Operand(x1, SXTX, 3));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x00000081, x6);
-  ASSERT_EQUAL_64(0x00010101, x7);
-  ASSERT_EQUAL_64(0x00020201, x8);
-  ASSERT_EQUAL_64(0x0000000400040401UL, x9);
-  ASSERT_EQUAL_64(0x00000000ffffff81UL, x10);
-  ASSERT_EQUAL_64(0xffffffffffff0101UL, x11);
-  ASSERT_EQUAL_64(0xfffffffe00020201UL, x12);
-  ASSERT_EQUAL_64(0x0000000400040401UL, x13);
+  CHECK_EQUAL_64(0x00000081, x6);
+  CHECK_EQUAL_64(0x00010101, x7);
+  CHECK_EQUAL_64(0x00020201, x8);
+  CHECK_EQUAL_64(0x0000000400040401UL, x9);
+  CHECK_EQUAL_64(0x00000000ffffff81UL, x10);
+  CHECK_EQUAL_64(0xffffffffffff0101UL, x11);
+  CHECK_EQUAL_64(0xfffffffe00020201UL, x12);
+  CHECK_EQUAL_64(0x0000000400040401UL, x13);
 
   TEARDOWN();
 }
 
 
 TEST(bitwise_wide_imm) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0);
   __ Mov(x1, 0xf0f0f0f0f0f0f0f0UL);
 
   __ Orr(x10, x0, Operand(0x1234567890abcdefUL));
   __ Orr(w11, w1, Operand(0x90abcdef));
 
   __ Orr(w12, w0, kWMinInt);
   __ Eor(w13, w0, kWMinInt);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0, x0);
-  ASSERT_EQUAL_64(0xf0f0f0f0f0f0f0f0UL, x1);
-  ASSERT_EQUAL_64(0x1234567890abcdefUL, x10);
-  ASSERT_EQUAL_64(0xf0fbfdffUL, x11);
-  ASSERT_EQUAL_32(kWMinInt, w12);
-  ASSERT_EQUAL_32(kWMinInt, w13);
+  CHECK_EQUAL_64(0, x0);
+  CHECK_EQUAL_64(0xf0f0f0f0f0f0f0f0UL, x1);
+  CHECK_EQUAL_64(0x1234567890abcdefUL, x10);
+  CHECK_EQUAL_64(0xf0fbfdffUL, x11);
+  CHECK_EQUAL_32(kWMinInt, w12);
+  CHECK_EQUAL_32(kWMinInt, w13);
 
   TEARDOWN();
 }
 
 
 TEST(orn) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0xf0f0);
   __ Mov(x1, 0xf00000ff);
 
   __ Orn(x2, x0, Operand(x1));
   __ Orn(w3, w0, Operand(w1, LSL, 4));
   __ Orn(x4, x0, Operand(x1, LSL, 4));
   __ Orn(x5, x0, Operand(x1, LSR, 1));
   __ Orn(w6, w0, Operand(w1, ASR, 1));
   __ Orn(x7, x0, Operand(x1, ASR, 1));
   __ Orn(w8, w0, Operand(w1, ROR, 16));
   __ Orn(x9, x0, Operand(x1, ROR, 16));
   __ Orn(w10, w0, Operand(0xffff));
   __ Orn(x11, x0, Operand(0xffff0000ffffL));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffffff0ffffff0L, x2);
-  ASSERT_EQUAL_64(0xfffff0ff, x3);
-  ASSERT_EQUAL_64(0xfffffff0fffff0ffL, x4);
-  ASSERT_EQUAL_64(0xffffffff87fffff0L, x5);
-  ASSERT_EQUAL_64(0x07fffff0, x6);
-  ASSERT_EQUAL_64(0xffffffff87fffff0L, x7);
-  ASSERT_EQUAL_64(0xff00ffff, x8);
-  ASSERT_EQUAL_64(0xff00ffffffffffffL, x9);
-  ASSERT_EQUAL_64(0xfffff0f0, x10);
-  ASSERT_EQUAL_64(0xffff0000fffff0f0L, x11);
+  CHECK_EQUAL_64(0xffffffff0ffffff0L, x2);
+  CHECK_EQUAL_64(0xfffff0ff, x3);
+  CHECK_EQUAL_64(0xfffffff0fffff0ffL, x4);
+  CHECK_EQUAL_64(0xffffffff87fffff0L, x5);
+  CHECK_EQUAL_64(0x07fffff0, x6);
+  CHECK_EQUAL_64(0xffffffff87fffff0L, x7);
+  CHECK_EQUAL_64(0xff00ffff, x8);
+  CHECK_EQUAL_64(0xff00ffffffffffffL, x9);
+  CHECK_EQUAL_64(0xfffff0f0, x10);
+  CHECK_EQUAL_64(0xffff0000fffff0f0L, x11);
 
   TEARDOWN();
 }
 
 
 TEST(orn_extend) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 1);
   __ Mov(x1, 0x8000000080008081UL);
   __ Orn(w6, w0, Operand(w1, UXTB));
   __ Orn(x7, x0, Operand(x1, UXTH, 1));
   __ Orn(w8, w0, Operand(w1, UXTW, 2));
   __ Orn(x9, x0, Operand(x1, UXTX, 3));
   __ Orn(w10, w0, Operand(w1, SXTB));
   __ Orn(x11, x0, Operand(x1, SXTH, 1));
   __ Orn(x12, x0, Operand(x1, SXTW, 2));
   __ Orn(x13, x0, Operand(x1, SXTX, 3));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffff7f, x6);
-  ASSERT_EQUAL_64(0xfffffffffffefefdUL, x7);
-  ASSERT_EQUAL_64(0xfffdfdfb, x8);
-  ASSERT_EQUAL_64(0xfffffffbfffbfbf7UL, x9);
-  ASSERT_EQUAL_64(0x0000007f, x10);
-  ASSERT_EQUAL_64(0x0000fefd, x11);
-  ASSERT_EQUAL_64(0x00000001fffdfdfbUL, x12);
-  ASSERT_EQUAL_64(0xfffffffbfffbfbf7UL, x13);
+  CHECK_EQUAL_64(0xffffff7f, x6);
+  CHECK_EQUAL_64(0xfffffffffffefefdUL, x7);
+  CHECK_EQUAL_64(0xfffdfdfb, x8);
+  CHECK_EQUAL_64(0xfffffffbfffbfbf7UL, x9);
+  CHECK_EQUAL_64(0x0000007f, x10);
+  CHECK_EQUAL_64(0x0000fefd, x11);
+  CHECK_EQUAL_64(0x00000001fffdfdfbUL, x12);
+  CHECK_EQUAL_64(0xfffffffbfffbfbf7UL, x13);
 
   TEARDOWN();
 }
 
 
 TEST(and_) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0xfff0);
   __ Mov(x1, 0xf00000ff);
 
   __ And(x2, x0, Operand(x1));
   __ And(w3, w0, Operand(w1, LSL, 4));
   __ And(x4, x0, Operand(x1, LSL, 4));
   __ And(x5, x0, Operand(x1, LSR, 1));
   __ And(w6, w0, Operand(w1, ASR, 20));
   __ And(x7, x0, Operand(x1, ASR, 20));
   __ And(w8, w0, Operand(w1, ROR, 28));
   __ And(x9, x0, Operand(x1, ROR, 28));
   __ And(w10, w0, Operand(0xff00));
   __ And(x11, x0, Operand(0xff));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x000000f0, x2);
-  ASSERT_EQUAL_64(0x00000ff0, x3);
-  ASSERT_EQUAL_64(0x00000ff0, x4);
-  ASSERT_EQUAL_64(0x00000070, x5);
-  ASSERT_EQUAL_64(0x0000ff00, x6);
-  ASSERT_EQUAL_64(0x00000f00, x7);
-  ASSERT_EQUAL_64(0x00000ff0, x8);
-  ASSERT_EQUAL_64(0x00000000, x9);
-  ASSERT_EQUAL_64(0x0000ff00, x10);
-  ASSERT_EQUAL_64(0x000000f0, x11);
+  CHECK_EQUAL_64(0x000000f0, x2);
+  CHECK_EQUAL_64(0x00000ff0, x3);
+  CHECK_EQUAL_64(0x00000ff0, x4);
+  CHECK_EQUAL_64(0x00000070, x5);
+  CHECK_EQUAL_64(0x0000ff00, x6);
+  CHECK_EQUAL_64(0x00000f00, x7);
+  CHECK_EQUAL_64(0x00000ff0, x8);
+  CHECK_EQUAL_64(0x00000000, x9);
+  CHECK_EQUAL_64(0x0000ff00, x10);
+  CHECK_EQUAL_64(0x000000f0, x11);
 
   TEARDOWN();
 }
 
 
 TEST(and_extend) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0xffffffffffffffffUL);
   __ Mov(x1, 0x8000000080008081UL);
   __ And(w6, w0, Operand(w1, UXTB));
   __ And(x7, x0, Operand(x1, UXTH, 1));
   __ And(w8, w0, Operand(w1, UXTW, 2));
   __ And(x9, x0, Operand(x1, UXTX, 3));
   __ And(w10, w0, Operand(w1, SXTB));
   __ And(x11, x0, Operand(x1, SXTH, 1));
   __ And(x12, x0, Operand(x1, SXTW, 2));
   __ And(x13, x0, Operand(x1, SXTX, 3));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x00000081, x6);
-  ASSERT_EQUAL_64(0x00010102, x7);
-  ASSERT_EQUAL_64(0x00020204, x8);
-  ASSERT_EQUAL_64(0x0000000400040408UL, x9);
-  ASSERT_EQUAL_64(0xffffff81, x10);
-  ASSERT_EQUAL_64(0xffffffffffff0102UL, x11);
-  ASSERT_EQUAL_64(0xfffffffe00020204UL, x12);
-  ASSERT_EQUAL_64(0x0000000400040408UL, x13);
+  CHECK_EQUAL_64(0x00000081, x6);
+  CHECK_EQUAL_64(0x00010102, x7);
+  CHECK_EQUAL_64(0x00020204, x8);
+  CHECK_EQUAL_64(0x0000000400040408UL, x9);
+  CHECK_EQUAL_64(0xffffff81, x10);
+  CHECK_EQUAL_64(0xffffffffffff0102UL, x11);
+  CHECK_EQUAL_64(0xfffffffe00020204UL, x12);
+  CHECK_EQUAL_64(0x0000000400040408UL, x13);
 
   TEARDOWN();
 }
 
 
 TEST(ands) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x1, 0xf00000ff);
   __ Ands(w0, w1, Operand(w1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0xf00000ff, x0);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0xf00000ff, x0);
 
   START();
   __ Mov(x0, 0xfff0);
   __ Mov(x1, 0xf00000ff);
   __ Ands(w0, w0, Operand(w1, LSR, 4));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZFlag);
-  ASSERT_EQUAL_64(0x00000000, x0);
+  CHECK_EQUAL_NZCV(ZFlag);
+  CHECK_EQUAL_64(0x00000000, x0);
 
   START();
   __ Mov(x0, 0x8000000000000000L);
   __ Mov(x1, 0x00000001);
   __ Ands(x0, x0, Operand(x1, ROR, 1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0x8000000000000000L, x0);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0x8000000000000000L, x0);
 
   START();
   __ Mov(x0, 0xfff0);
   __ Ands(w0, w0, Operand(0xf));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZFlag);
-  ASSERT_EQUAL_64(0x00000000, x0);
+  CHECK_EQUAL_NZCV(ZFlag);
+  CHECK_EQUAL_64(0x00000000, x0);
 
   START();
   __ Mov(x0, 0xff000000);
   __ Ands(w0, w0, Operand(0x80000000));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0x80000000, x0);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0x80000000, x0);
 
   TEARDOWN();
 }
 
 
 TEST(bic) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 17 matching lines @@
   // test infrastructure requires that csp be restored to its original value.
   __ Mov(x20, csp);
   __ Mov(x0, 0xffffff);
   __ Bic(csp, x0, Operand(0xabcdef));
   __ Mov(x21, csp);
   __ Mov(csp, x20);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x0000ff00, x2);
-  ASSERT_EQUAL_64(0x0000f000, x3);
-  ASSERT_EQUAL_64(0x0000f000, x4);
-  ASSERT_EQUAL_64(0x0000ff80, x5);
-  ASSERT_EQUAL_64(0x000000f0, x6);
-  ASSERT_EQUAL_64(0x0000f0f0, x7);
-  ASSERT_EQUAL_64(0x0000f000, x8);
-  ASSERT_EQUAL_64(0x0000ff00, x9);
-  ASSERT_EQUAL_64(0x0000ffe0, x10);
-  ASSERT_EQUAL_64(0x0000fef0, x11);
+  CHECK_EQUAL_64(0x0000ff00, x2);
+  CHECK_EQUAL_64(0x0000f000, x3);
+  CHECK_EQUAL_64(0x0000f000, x4);
+  CHECK_EQUAL_64(0x0000ff80, x5);
+  CHECK_EQUAL_64(0x000000f0, x6);
+  CHECK_EQUAL_64(0x0000f0f0, x7);
+  CHECK_EQUAL_64(0x0000f000, x8);
+  CHECK_EQUAL_64(0x0000ff00, x9);
+  CHECK_EQUAL_64(0x0000ffe0, x10);
+  CHECK_EQUAL_64(0x0000fef0, x11);
 
-  ASSERT_EQUAL_64(0x543210, x21);
+  CHECK_EQUAL_64(0x543210, x21);
 
   TEARDOWN();
 }
 
 
 TEST(bic_extend) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0xffffffffffffffffUL);
   __ Mov(x1, 0x8000000080008081UL);
   __ Bic(w6, w0, Operand(w1, UXTB));
   __ Bic(x7, x0, Operand(x1, UXTH, 1));
   __ Bic(w8, w0, Operand(w1, UXTW, 2));
   __ Bic(x9, x0, Operand(x1, UXTX, 3));
   __ Bic(w10, w0, Operand(w1, SXTB));
   __ Bic(x11, x0, Operand(x1, SXTH, 1));
   __ Bic(x12, x0, Operand(x1, SXTW, 2));
   __ Bic(x13, x0, Operand(x1, SXTX, 3));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffff7e, x6);
-  ASSERT_EQUAL_64(0xfffffffffffefefdUL, x7);
-  ASSERT_EQUAL_64(0xfffdfdfb, x8);
-  ASSERT_EQUAL_64(0xfffffffbfffbfbf7UL, x9);
-  ASSERT_EQUAL_64(0x0000007e, x10);
-  ASSERT_EQUAL_64(0x0000fefd, x11);
-  ASSERT_EQUAL_64(0x00000001fffdfdfbUL, x12);
-  ASSERT_EQUAL_64(0xfffffffbfffbfbf7UL, x13);
+  CHECK_EQUAL_64(0xffffff7e, x6);
+  CHECK_EQUAL_64(0xfffffffffffefefdUL, x7);
+  CHECK_EQUAL_64(0xfffdfdfb, x8);
+  CHECK_EQUAL_64(0xfffffffbfffbfbf7UL, x9);
+  CHECK_EQUAL_64(0x0000007e, x10);
+  CHECK_EQUAL_64(0x0000fefd, x11);
+  CHECK_EQUAL_64(0x00000001fffdfdfbUL, x12);
+  CHECK_EQUAL_64(0xfffffffbfffbfbf7UL, x13);
 
   TEARDOWN();
 }
 
 
 TEST(bics) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x1, 0xffff);
   __ Bics(w0, w1, Operand(w1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZFlag);
-  ASSERT_EQUAL_64(0x00000000, x0);
+  CHECK_EQUAL_NZCV(ZFlag);
+  CHECK_EQUAL_64(0x00000000, x0);
 
   START();
   __ Mov(x0, 0xffffffff);
   __ Bics(w0, w0, Operand(w0, LSR, 1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0x80000000, x0);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0x80000000, x0);
 
   START();
   __ Mov(x0, 0x8000000000000000L);
   __ Mov(x1, 0x00000001);
   __ Bics(x0, x0, Operand(x1, ROR, 1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZFlag);
-  ASSERT_EQUAL_64(0x00000000, x0);
+  CHECK_EQUAL_NZCV(ZFlag);
+  CHECK_EQUAL_64(0x00000000, x0);
 
   START();
   __ Mov(x0, 0xffffffffffffffffL);
   __ Bics(x0, x0, Operand(0x7fffffffffffffffL));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0x8000000000000000L, x0);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0x8000000000000000L, x0);
 
   START();
   __ Mov(w0, 0xffff0000);
   __ Bics(w0, w0, Operand(0xfffffff0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZFlag);
-  ASSERT_EQUAL_64(0x00000000, x0);
+  CHECK_EQUAL_NZCV(ZFlag);
+  CHECK_EQUAL_64(0x00000000, x0);
 
   TEARDOWN();
 }
 
 
 TEST(eor) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0xfff0);
   __ Mov(x1, 0xf00000ff);
 
   __ Eor(x2, x0, Operand(x1));
   __ Eor(w3, w0, Operand(w1, LSL, 4));
   __ Eor(x4, x0, Operand(x1, LSL, 4));
   __ Eor(x5, x0, Operand(x1, LSR, 1));
   __ Eor(w6, w0, Operand(w1, ASR, 20));
   __ Eor(x7, x0, Operand(x1, ASR, 20));
   __ Eor(w8, w0, Operand(w1, ROR, 28));
   __ Eor(x9, x0, Operand(x1, ROR, 28));
   __ Eor(w10, w0, Operand(0xff00ff00));
   __ Eor(x11, x0, Operand(0xff00ff00ff00ff00L));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xf000ff0f, x2);
-  ASSERT_EQUAL_64(0x0000f000, x3);
-  ASSERT_EQUAL_64(0x0000000f0000f000L, x4);
-  ASSERT_EQUAL_64(0x7800ff8f, x5);
-  ASSERT_EQUAL_64(0xffff00f0, x6);
-  ASSERT_EQUAL_64(0x0000f0f0, x7);
-  ASSERT_EQUAL_64(0x0000f00f, x8);
-  ASSERT_EQUAL_64(0x00000ff00000ffffL, x9);
-  ASSERT_EQUAL_64(0xff0000f0, x10);
-  ASSERT_EQUAL_64(0xff00ff00ff0000f0L, x11);
+  CHECK_EQUAL_64(0xf000ff0f, x2);
+  CHECK_EQUAL_64(0x0000f000, x3);
+  CHECK_EQUAL_64(0x0000000f0000f000L, x4);
+  CHECK_EQUAL_64(0x7800ff8f, x5);
+  CHECK_EQUAL_64(0xffff00f0, x6);
+  CHECK_EQUAL_64(0x0000f0f0, x7);
+  CHECK_EQUAL_64(0x0000f00f, x8);
+  CHECK_EQUAL_64(0x00000ff00000ffffL, x9);
+  CHECK_EQUAL_64(0xff0000f0, x10);
+  CHECK_EQUAL_64(0xff00ff00ff0000f0L, x11);
 
   TEARDOWN();
 }
 
 
 TEST(eor_extend) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0x1111111111111111UL);
   __ Mov(x1, 0x8000000080008081UL);
   __ Eor(w6, w0, Operand(w1, UXTB));
   __ Eor(x7, x0, Operand(x1, UXTH, 1));
   __ Eor(w8, w0, Operand(w1, UXTW, 2));
   __ Eor(x9, x0, Operand(x1, UXTX, 3));
   __ Eor(w10, w0, Operand(w1, SXTB));
   __ Eor(x11, x0, Operand(x1, SXTH, 1));
   __ Eor(x12, x0, Operand(x1, SXTW, 2));
   __ Eor(x13, x0, Operand(x1, SXTX, 3));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x11111190, x6);
-  ASSERT_EQUAL_64(0x1111111111101013UL, x7);
-  ASSERT_EQUAL_64(0x11131315, x8);
-  ASSERT_EQUAL_64(0x1111111511151519UL, x9);
-  ASSERT_EQUAL_64(0xeeeeee90, x10);
-  ASSERT_EQUAL_64(0xeeeeeeeeeeee1013UL, x11);
-  ASSERT_EQUAL_64(0xeeeeeeef11131315UL, x12);
-  ASSERT_EQUAL_64(0x1111111511151519UL, x13);
+  CHECK_EQUAL_64(0x11111190, x6);
+  CHECK_EQUAL_64(0x1111111111101013UL, x7);
+  CHECK_EQUAL_64(0x11131315, x8);
+  CHECK_EQUAL_64(0x1111111511151519UL, x9);
+  CHECK_EQUAL_64(0xeeeeee90, x10);
+  CHECK_EQUAL_64(0xeeeeeeeeeeee1013UL, x11);
+  CHECK_EQUAL_64(0xeeeeeeef11131315UL, x12);
+  CHECK_EQUAL_64(0x1111111511151519UL, x13);
 
   TEARDOWN();
 }
 
 
 TEST(eon) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0xfff0);
   __ Mov(x1, 0xf00000ff);
 
   __ Eon(x2, x0, Operand(x1));
   __ Eon(w3, w0, Operand(w1, LSL, 4));
   __ Eon(x4, x0, Operand(x1, LSL, 4));
   __ Eon(x5, x0, Operand(x1, LSR, 1));
   __ Eon(w6, w0, Operand(w1, ASR, 20));
   __ Eon(x7, x0, Operand(x1, ASR, 20));
   __ Eon(w8, w0, Operand(w1, ROR, 28));
   __ Eon(x9, x0, Operand(x1, ROR, 28));
   __ Eon(w10, w0, Operand(0x03c003c0));
   __ Eon(x11, x0, Operand(0x0000100000001000L));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffffff0fff00f0L, x2);
-  ASSERT_EQUAL_64(0xffff0fff, x3);
-  ASSERT_EQUAL_64(0xfffffff0ffff0fffL, x4);
-  ASSERT_EQUAL_64(0xffffffff87ff0070L, x5);
-  ASSERT_EQUAL_64(0x0000ff0f, x6);
-  ASSERT_EQUAL_64(0xffffffffffff0f0fL, x7);
-  ASSERT_EQUAL_64(0xffff0ff0, x8);
-  ASSERT_EQUAL_64(0xfffff00fffff0000L, x9);
-  ASSERT_EQUAL_64(0xfc3f03cf, x10);
-  ASSERT_EQUAL_64(0xffffefffffff100fL, x11);
+  CHECK_EQUAL_64(0xffffffff0fff00f0L, x2);
+  CHECK_EQUAL_64(0xffff0fff, x3);
+  CHECK_EQUAL_64(0xfffffff0ffff0fffL, x4);
+  CHECK_EQUAL_64(0xffffffff87ff0070L, x5);
+  CHECK_EQUAL_64(0x0000ff0f, x6);
+  CHECK_EQUAL_64(0xffffffffffff0f0fL, x7);
+  CHECK_EQUAL_64(0xffff0ff0, x8);
+  CHECK_EQUAL_64(0xfffff00fffff0000L, x9);
+  CHECK_EQUAL_64(0xfc3f03cf, x10);
+  CHECK_EQUAL_64(0xffffefffffff100fL, x11);
 
   TEARDOWN();
 }
 
 
 TEST(eon_extend) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0x1111111111111111UL);
   __ Mov(x1, 0x8000000080008081UL);
   __ Eon(w6, w0, Operand(w1, UXTB));
   __ Eon(x7, x0, Operand(x1, UXTH, 1));
   __ Eon(w8, w0, Operand(w1, UXTW, 2));
   __ Eon(x9, x0, Operand(x1, UXTX, 3));
   __ Eon(w10, w0, Operand(w1, SXTB));
   __ Eon(x11, x0, Operand(x1, SXTH, 1));
   __ Eon(x12, x0, Operand(x1, SXTW, 2));
   __ Eon(x13, x0, Operand(x1, SXTX, 3));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xeeeeee6f, x6);
-  ASSERT_EQUAL_64(0xeeeeeeeeeeefefecUL, x7);
-  ASSERT_EQUAL_64(0xeeececea, x8);
-  ASSERT_EQUAL_64(0xeeeeeeeaeeeaeae6UL, x9);
-  ASSERT_EQUAL_64(0x1111116f, x10);
-  ASSERT_EQUAL_64(0x111111111111efecUL, x11);
-  ASSERT_EQUAL_64(0x11111110eeececeaUL, x12);
-  ASSERT_EQUAL_64(0xeeeeeeeaeeeaeae6UL, x13);
+  CHECK_EQUAL_64(0xeeeeee6f, x6);
+  CHECK_EQUAL_64(0xeeeeeeeeeeefefecUL, x7);
+  CHECK_EQUAL_64(0xeeececea, x8);
+  CHECK_EQUAL_64(0xeeeeeeeaeeeaeae6UL, x9);
+  CHECK_EQUAL_64(0x1111116f, x10);
+  CHECK_EQUAL_64(0x111111111111efecUL, x11);
+  CHECK_EQUAL_64(0x11111110eeececeaUL, x12);
+  CHECK_EQUAL_64(0xeeeeeeeaeeeaeae6UL, x13);
 
   TEARDOWN();
 }
 
 
 TEST(mul) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 18 matching lines @@
   __ Mneg(w13, w17, w18);
   __ Mneg(w14, w18, w19);
   __ Mneg(x20, x16, x16);
   __ Mneg(x21, x17, x18);
   __ Mneg(x22, x18, x19);
   __ Mneg(x23, x19, x19);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0, x0);
-  ASSERT_EQUAL_64(0, x1);
-  ASSERT_EQUAL_64(0xffffffff, x2);
-  ASSERT_EQUAL_64(1, x3);
-  ASSERT_EQUAL_64(0, x4);
-  ASSERT_EQUAL_64(0xffffffff, x5);
-  ASSERT_EQUAL_64(0xffffffff00000001UL, x6);
-  ASSERT_EQUAL_64(1, x7);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x8);
-  ASSERT_EQUAL_64(1, x9);
-  ASSERT_EQUAL_64(1, x10);
-  ASSERT_EQUAL_64(0, x11);
-  ASSERT_EQUAL_64(0, x12);
-  ASSERT_EQUAL_64(1, x13);
-  ASSERT_EQUAL_64(0xffffffff, x14);
-  ASSERT_EQUAL_64(0, x20);
-  ASSERT_EQUAL_64(0xffffffff00000001UL, x21);
-  ASSERT_EQUAL_64(0xffffffff, x22);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x23);
+  CHECK_EQUAL_64(0, x0);
+  CHECK_EQUAL_64(0, x1);
+  CHECK_EQUAL_64(0xffffffff, x2);
+  CHECK_EQUAL_64(1, x3);
+  CHECK_EQUAL_64(0, x4);
+  CHECK_EQUAL_64(0xffffffff, x5);
+  CHECK_EQUAL_64(0xffffffff00000001UL, x6);
+  CHECK_EQUAL_64(1, x7);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x8);
+  CHECK_EQUAL_64(1, x9);
+  CHECK_EQUAL_64(1, x10);
+  CHECK_EQUAL_64(0, x11);
+  CHECK_EQUAL_64(0, x12);
+  CHECK_EQUAL_64(1, x13);
+  CHECK_EQUAL_64(0xffffffff, x14);
+  CHECK_EQUAL_64(0, x20);
+  CHECK_EQUAL_64(0xffffffff00000001UL, x21);
+  CHECK_EQUAL_64(0xffffffff, x22);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x23);
 
   TEARDOWN();
 }
 
 
 static void SmullHelper(int64_t expected, int64_t a, int64_t b) {
   SETUP();
   START();
   __ Mov(w0, a);
   __ Mov(w1, b);
   __ Smull(x2, w0, w1);
   END();
   RUN();
-  ASSERT_EQUAL_64(expected, x2);
+  CHECK_EQUAL_64(expected, x2);
   TEARDOWN();
 }
 
 
 TEST(smull) {
   INIT_V8();
   SmullHelper(0, 0, 0);
   SmullHelper(1, 1, 1);
   SmullHelper(-1, -1, 1);
   SmullHelper(1, -1, -1);
@@ skipping 35 matching lines @@
   __ Madd(x23, x17, x18, x16);
   __ Madd(x24, x17, x18, x18);
   __ Madd(x25, x18, x18, x17);
   __ Madd(x26, x18, x19, x18);
   __ Madd(x27, x19, x19, x19);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(0xffffffff, x2);
-  ASSERT_EQUAL_64(0xffffffff, x3);
-  ASSERT_EQUAL_64(1, x4);
-  ASSERT_EQUAL_64(0, x5);
-  ASSERT_EQUAL_64(0, x6);
-  ASSERT_EQUAL_64(0xffffffff, x7);
-  ASSERT_EQUAL_64(0xfffffffe, x8);
-  ASSERT_EQUAL_64(2, x9);
-  ASSERT_EQUAL_64(0, x10);
-  ASSERT_EQUAL_64(0, x11);
+  CHECK_EQUAL_64(0, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(0xffffffff, x2);
+  CHECK_EQUAL_64(0xffffffff, x3);
+  CHECK_EQUAL_64(1, x4);
+  CHECK_EQUAL_64(0, x5);
+  CHECK_EQUAL_64(0, x6);
+  CHECK_EQUAL_64(0xffffffff, x7);
+  CHECK_EQUAL_64(0xfffffffe, x8);
+  CHECK_EQUAL_64(2, x9);
+  CHECK_EQUAL_64(0, x10);
+  CHECK_EQUAL_64(0, x11);
 
-  ASSERT_EQUAL_64(0, x12);
-  ASSERT_EQUAL_64(1, x13);
-  ASSERT_EQUAL_64(0xffffffff, x14);
-  ASSERT_EQUAL_64(0xffffffffffffffff, x15);
-  ASSERT_EQUAL_64(1, x20);
-  ASSERT_EQUAL_64(0x100000000UL, x21);
-  ASSERT_EQUAL_64(0, x22);
-  ASSERT_EQUAL_64(0xffffffff, x23);
-  ASSERT_EQUAL_64(0x1fffffffe, x24);
-  ASSERT_EQUAL_64(0xfffffffe00000002UL, x25);
-  ASSERT_EQUAL_64(0, x26);
-  ASSERT_EQUAL_64(0, x27);
+  CHECK_EQUAL_64(0, x12);
+  CHECK_EQUAL_64(1, x13);
+  CHECK_EQUAL_64(0xffffffff, x14);
+  CHECK_EQUAL_64(0xffffffffffffffff, x15);
+  CHECK_EQUAL_64(1, x20);
+  CHECK_EQUAL_64(0x100000000UL, x21);
+  CHECK_EQUAL_64(0, x22);
+  CHECK_EQUAL_64(0xffffffff, x23);
+  CHECK_EQUAL_64(0x1fffffffe, x24);
+  CHECK_EQUAL_64(0xfffffffe00000002UL, x25);
+  CHECK_EQUAL_64(0, x26);
+  CHECK_EQUAL_64(0, x27);
 
   TEARDOWN();
 }
 
 
 TEST(msub) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 25 matching lines @@
   __ Msub(x23, x17, x18, x16);
   __ Msub(x24, x17, x18, x18);
   __ Msub(x25, x18, x18, x17);
   __ Msub(x26, x18, x19, x18);
   __ Msub(x27, x19, x19, x19);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(0xffffffff, x2);
-  ASSERT_EQUAL_64(0xffffffff, x3);
-  ASSERT_EQUAL_64(1, x4);
-  ASSERT_EQUAL_64(0xfffffffe, x5);
-  ASSERT_EQUAL_64(0xfffffffe, x6);
-  ASSERT_EQUAL_64(1, x7);
-  ASSERT_EQUAL_64(0, x8);
-  ASSERT_EQUAL_64(0, x9);
-  ASSERT_EQUAL_64(0xfffffffe, x10);
-  ASSERT_EQUAL_64(0xfffffffe, x11);
+  CHECK_EQUAL_64(0, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(0xffffffff, x2);
+  CHECK_EQUAL_64(0xffffffff, x3);
+  CHECK_EQUAL_64(1, x4);
+  CHECK_EQUAL_64(0xfffffffe, x5);
+  CHECK_EQUAL_64(0xfffffffe, x6);
+  CHECK_EQUAL_64(1, x7);
+  CHECK_EQUAL_64(0, x8);
+  CHECK_EQUAL_64(0, x9);
+  CHECK_EQUAL_64(0xfffffffe, x10);
+  CHECK_EQUAL_64(0xfffffffe, x11);
 
-  ASSERT_EQUAL_64(0, x12);
-  ASSERT_EQUAL_64(1, x13);
-  ASSERT_EQUAL_64(0xffffffff, x14);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x15);
-  ASSERT_EQUAL_64(1, x20);
-  ASSERT_EQUAL_64(0xfffffffeUL, x21);
-  ASSERT_EQUAL_64(0xfffffffffffffffeUL, x22);
-  ASSERT_EQUAL_64(0xffffffff00000001UL, x23);
-  ASSERT_EQUAL_64(0, x24);
-  ASSERT_EQUAL_64(0x200000000UL, x25);
-  ASSERT_EQUAL_64(0x1fffffffeUL, x26);
-  ASSERT_EQUAL_64(0xfffffffffffffffeUL, x27);
+  CHECK_EQUAL_64(0, x12);
+  CHECK_EQUAL_64(1, x13);
+  CHECK_EQUAL_64(0xffffffff, x14);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x15);
+  CHECK_EQUAL_64(1, x20);
+  CHECK_EQUAL_64(0xfffffffeUL, x21);
+  CHECK_EQUAL_64(0xfffffffffffffffeUL, x22);
+  CHECK_EQUAL_64(0xffffffff00000001UL, x23);
+  CHECK_EQUAL_64(0, x24);
+  CHECK_EQUAL_64(0x200000000UL, x25);
+  CHECK_EQUAL_64(0x1fffffffeUL, x26);
+  CHECK_EQUAL_64(0xfffffffffffffffeUL, x27);
 
   TEARDOWN();
 }
 
 
 TEST(smulh) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 17 matching lines @@
   __ Smulh(x6, x26, x26);
   __ Smulh(x7, x26, x27);
   __ Smulh(x8, x27, x27);
   __ Smulh(x9, x28, x28);
   __ Smulh(x10, x28, x29);
   __ Smulh(x11, x29, x29);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0, x0);
-  ASSERT_EQUAL_64(0, x1);
-  ASSERT_EQUAL_64(0, x2);
-  ASSERT_EQUAL_64(0x01234567, x3);
-  ASSERT_EQUAL_64(0x02468acf, x4);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x5);
-  ASSERT_EQUAL_64(0x4000000000000000UL, x6);
-  ASSERT_EQUAL_64(0, x7);
-  ASSERT_EQUAL_64(0, x8);
-  ASSERT_EQUAL_64(0x1c71c71c71c71c71UL, x9);
-  ASSERT_EQUAL_64(0xe38e38e38e38e38eUL, x10);
-  ASSERT_EQUAL_64(0x1c71c71c71c71c72UL, x11);
+  CHECK_EQUAL_64(0, x0);
+  CHECK_EQUAL_64(0, x1);
+  CHECK_EQUAL_64(0, x2);
+  CHECK_EQUAL_64(0x01234567, x3);
+  CHECK_EQUAL_64(0x02468acf, x4);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x5);
+  CHECK_EQUAL_64(0x4000000000000000UL, x6);
+  CHECK_EQUAL_64(0, x7);
+  CHECK_EQUAL_64(0, x8);
+  CHECK_EQUAL_64(0x1c71c71c71c71c71UL, x9);
+  CHECK_EQUAL_64(0xe38e38e38e38e38eUL, x10);
+  CHECK_EQUAL_64(0x1c71c71c71c71c72UL, x11);
 
   TEARDOWN();
 }
 
 
 TEST(smaddl_umaddl) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x17, 1);
   __ Mov(x18, 0xffffffff);
   __ Mov(x19, 0xffffffffffffffffUL);
   __ Mov(x20, 4);
   __ Mov(x21, 0x200000000UL);
 
   __ Smaddl(x9, w17, w18, x20);
   __ Smaddl(x10, w18, w18, x20);
   __ Smaddl(x11, w19, w19, x20);
   __ Smaddl(x12, w19, w19, x21);
   __ Umaddl(x13, w17, w18, x20);
   __ Umaddl(x14, w18, w18, x20);
   __ Umaddl(x15, w19, w19, x20);
   __ Umaddl(x22, w19, w19, x21);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(3, x9);
-  ASSERT_EQUAL_64(5, x10);
-  ASSERT_EQUAL_64(5, x11);
-  ASSERT_EQUAL_64(0x200000001UL, x12);
-  ASSERT_EQUAL_64(0x100000003UL, x13);
-  ASSERT_EQUAL_64(0xfffffffe00000005UL, x14);
-  ASSERT_EQUAL_64(0xfffffffe00000005UL, x15);
-  ASSERT_EQUAL_64(0x1, x22);
+  CHECK_EQUAL_64(3, x9);
+  CHECK_EQUAL_64(5, x10);
+  CHECK_EQUAL_64(5, x11);
+  CHECK_EQUAL_64(0x200000001UL, x12);
+  CHECK_EQUAL_64(0x100000003UL, x13);
+  CHECK_EQUAL_64(0xfffffffe00000005UL, x14);
+  CHECK_EQUAL_64(0xfffffffe00000005UL, x15);
+  CHECK_EQUAL_64(0x1, x22);
 
   TEARDOWN();
 }
 
 
 TEST(smsubl_umsubl) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x17, 1);
   __ Mov(x18, 0xffffffff);
   __ Mov(x19, 0xffffffffffffffffUL);
   __ Mov(x20, 4);
   __ Mov(x21, 0x200000000UL);
 
   __ Smsubl(x9, w17, w18, x20);
   __ Smsubl(x10, w18, w18, x20);
   __ Smsubl(x11, w19, w19, x20);
   __ Smsubl(x12, w19, w19, x21);
   __ Umsubl(x13, w17, w18, x20);
   __ Umsubl(x14, w18, w18, x20);
   __ Umsubl(x15, w19, w19, x20);
   __ Umsubl(x22, w19, w19, x21);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(5, x9);
-  ASSERT_EQUAL_64(3, x10);
-  ASSERT_EQUAL_64(3, x11);
-  ASSERT_EQUAL_64(0x1ffffffffUL, x12);
-  ASSERT_EQUAL_64(0xffffffff00000005UL, x13);
-  ASSERT_EQUAL_64(0x200000003UL, x14);
-  ASSERT_EQUAL_64(0x200000003UL, x15);
-  ASSERT_EQUAL_64(0x3ffffffffUL, x22);
+  CHECK_EQUAL_64(5, x9);
+  CHECK_EQUAL_64(3, x10);
+  CHECK_EQUAL_64(3, x11);
+  CHECK_EQUAL_64(0x1ffffffffUL, x12);
+  CHECK_EQUAL_64(0xffffffff00000005UL, x13);
+  CHECK_EQUAL_64(0x200000003UL, x14);
+  CHECK_EQUAL_64(0x200000003UL, x15);
+  CHECK_EQUAL_64(0x3ffffffffUL, x22);
 
   TEARDOWN();
 }
 
 
 TEST(div) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 35 matching lines @@
 
   __ Mov(x17, 0);
   __ Udiv(w18, w16, w17);
   __ Sdiv(w19, w16, w17);
   __ Udiv(x20, x16, x17);
   __ Sdiv(x21, x16, x17);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(0xffffffff, x1);
-  ASSERT_EQUAL_64(1, x2);
-  ASSERT_EQUAL_64(0xffffffff, x3);
-  ASSERT_EQUAL_64(1, x4);
-  ASSERT_EQUAL_64(1, x5);
-  ASSERT_EQUAL_64(0, x6);
-  ASSERT_EQUAL_64(1, x7);
-  ASSERT_EQUAL_64(0, x8);
-  ASSERT_EQUAL_64(0xffffffff00000001UL, x9);
-  ASSERT_EQUAL_64(0x40000000, x10);
-  ASSERT_EQUAL_64(0xC0000000, x11);
-  ASSERT_EQUAL_64(0x40000000, x12);
-  ASSERT_EQUAL_64(0x40000000, x13);
-  ASSERT_EQUAL_64(0x4000000000000000UL, x14);
-  ASSERT_EQUAL_64(0xC000000000000000UL, x15);
-  ASSERT_EQUAL_64(0, x22);
-  ASSERT_EQUAL_64(0x80000000, x23);
-  ASSERT_EQUAL_64(0, x24);
-  ASSERT_EQUAL_64(0x8000000000000000UL, x25);
-  ASSERT_EQUAL_64(0, x26);
-  ASSERT_EQUAL_64(0, x27);
-  ASSERT_EQUAL_64(0x7fffffffffffffffUL, x28);
-  ASSERT_EQUAL_64(0, x29);
-  ASSERT_EQUAL_64(0, x18);
-  ASSERT_EQUAL_64(0, x19);
-  ASSERT_EQUAL_64(0, x20);
-  ASSERT_EQUAL_64(0, x21);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(0xffffffff, x1);
+  CHECK_EQUAL_64(1, x2);
+  CHECK_EQUAL_64(0xffffffff, x3);
+  CHECK_EQUAL_64(1, x4);
+  CHECK_EQUAL_64(1, x5);
+  CHECK_EQUAL_64(0, x6);
+  CHECK_EQUAL_64(1, x7);
+  CHECK_EQUAL_64(0, x8);
+  CHECK_EQUAL_64(0xffffffff00000001UL, x9);
+  CHECK_EQUAL_64(0x40000000, x10);
+  CHECK_EQUAL_64(0xC0000000, x11);
+  CHECK_EQUAL_64(0x40000000, x12);
+  CHECK_EQUAL_64(0x40000000, x13);
+  CHECK_EQUAL_64(0x4000000000000000UL, x14);
+  CHECK_EQUAL_64(0xC000000000000000UL, x15);
+  CHECK_EQUAL_64(0, x22);
+  CHECK_EQUAL_64(0x80000000, x23);
+  CHECK_EQUAL_64(0, x24);
+  CHECK_EQUAL_64(0x8000000000000000UL, x25);
+  CHECK_EQUAL_64(0, x26);
+  CHECK_EQUAL_64(0, x27);
+  CHECK_EQUAL_64(0x7fffffffffffffffUL, x28);
+  CHECK_EQUAL_64(0, x29);
+  CHECK_EQUAL_64(0, x18);
+  CHECK_EQUAL_64(0, x19);
+  CHECK_EQUAL_64(0, x20);
+  CHECK_EQUAL_64(0, x21);
 
   TEARDOWN();
 }
 
 
 TEST(rbit_rev) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x24, 0xfedcba9876543210UL);
   __ Rbit(w0, w24);
   __ Rbit(x1, x24);
   __ Rev16(w2, w24);
   __ Rev16(x3, x24);
   __ Rev(w4, w24);
   __ Rev32(x5, x24);
   __ Rev(x6, x24);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x084c2a6e, x0);
-  ASSERT_EQUAL_64(0x084c2a6e195d3b7fUL, x1);
-  ASSERT_EQUAL_64(0x54761032, x2);
-  ASSERT_EQUAL_64(0xdcfe98ba54761032UL, x3);
-  ASSERT_EQUAL_64(0x10325476, x4);
-  ASSERT_EQUAL_64(0x98badcfe10325476UL, x5);
-  ASSERT_EQUAL_64(0x1032547698badcfeUL, x6);
+  CHECK_EQUAL_64(0x084c2a6e, x0);
+  CHECK_EQUAL_64(0x084c2a6e195d3b7fUL, x1);
+  CHECK_EQUAL_64(0x54761032, x2);
+  CHECK_EQUAL_64(0xdcfe98ba54761032UL, x3);
+  CHECK_EQUAL_64(0x10325476, x4);
+  CHECK_EQUAL_64(0x98badcfe10325476UL, x5);
+  CHECK_EQUAL_64(0x1032547698badcfeUL, x6);
 
   TEARDOWN();
 }
 
 
 TEST(clz_cls) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x24, 0x0008000000800000UL);
   __ Mov(x25, 0xff800000fff80000UL);
   __ Mov(x26, 0);
   __ Clz(w0, w24);
   __ Clz(x1, x24);
   __ Clz(w2, w25);
   __ Clz(x3, x25);
   __ Clz(w4, w26);
   __ Clz(x5, x26);
   __ Cls(w6, w24);
   __ Cls(x7, x24);
   __ Cls(w8, w25);
   __ Cls(x9, x25);
   __ Cls(w10, w26);
   __ Cls(x11, x26);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(8, x0);
-  ASSERT_EQUAL_64(12, x1);
-  ASSERT_EQUAL_64(0, x2);
-  ASSERT_EQUAL_64(0, x3);
-  ASSERT_EQUAL_64(32, x4);
-  ASSERT_EQUAL_64(64, x5);
-  ASSERT_EQUAL_64(7, x6);
-  ASSERT_EQUAL_64(11, x7);
-  ASSERT_EQUAL_64(12, x8);
-  ASSERT_EQUAL_64(8, x9);
-  ASSERT_EQUAL_64(31, x10);
-  ASSERT_EQUAL_64(63, x11);
+  CHECK_EQUAL_64(8, x0);
+  CHECK_EQUAL_64(12, x1);
+  CHECK_EQUAL_64(0, x2);
+  CHECK_EQUAL_64(0, x3);
+  CHECK_EQUAL_64(32, x4);
+  CHECK_EQUAL_64(64, x5);
+  CHECK_EQUAL_64(7, x6);
+  CHECK_EQUAL_64(11, x7);
+  CHECK_EQUAL_64(12, x8);
+  CHECK_EQUAL_64(8, x9);
+  CHECK_EQUAL_64(31, x10);
+  CHECK_EQUAL_64(63, x11);
 
   TEARDOWN();
 }
 
 
 TEST(label) {
   INIT_V8();
   SETUP();
 
   Label label_1, label_2, label_3, label_4;
@@ skipping 17 matching lines @@
   __ Bl(&label_4);
   END();
 
   __ Bind(&label_4);
   __ Mov(x1, 0x1);
   __ Mov(lr, x22);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1, x0);
-  ASSERT_EQUAL_64(0x1, x1);
+  CHECK_EQUAL_64(0x1, x0);
+  CHECK_EQUAL_64(0x1, x1);
 
   TEARDOWN();
 }
 
 
 TEST(branch_at_start) {
   INIT_V8();
   SETUP();
 
   Label good, exit;
@@ skipping 12 matching lines @@
   START_AFTER_RESET();
   __ Mov(x0, 0x1);
   END();
 
   __ Bind(&good);
   __ B(&exit);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1, x0);
+  CHECK_EQUAL_64(0x1, x0);
   TEARDOWN();
 }
 
 
 TEST(adr) {
   INIT_V8();
   SETUP();
 
   Label label_1, label_2, label_3, label_4;
 
@@ skipping 23 matching lines @@
   __ Adr(x3, &label_3);
   __ Adr(x4, &label_3);
   __ Adr(x5, &label_2);   // Simple reverse reference.
   __ Br(x5);  // label_2
 
   __ Bind(&label_4);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x0, x0);
-  ASSERT_EQUAL_64(0x0, x1);
+  CHECK_EQUAL_64(0x0, x0);
+  CHECK_EQUAL_64(0x0, x1);
 
   TEARDOWN();
 }
 
 
 TEST(adr_far) {
   INIT_V8();
 
   int max_range = 1 << (Instruction::ImmPCRelRangeBitwidth - 1);
   SETUP_SIZE(max_range + 1000 * kInstructionSize);
@@ skipping 44 matching lines @@
 
   __ B(&done);
   __ Bind(&fail);
   __ Orr(x0, x0, 1 << 4);
   __ Bind(&done);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xf, x0);
+  CHECK_EQUAL_64(0xf, x0);
 
   TEARDOWN();
 }
 
 
 TEST(branch_cond) {
   INIT_V8();
   SETUP();
 
   Label wrong;
@@ skipping 69 matching lines @@
   __ Bind(&ok_6);
 
   END();
 
   __ Bind(&wrong);
   __ Mov(x0, 0x0);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1, x0);
+  CHECK_EQUAL_64(0x1, x0);
 
   TEARDOWN();
 }
 
 
 TEST(branch_to_reg) {
   INIT_V8();
   SETUP();
 
   // Test br.
@@ skipping 26 matching lines @@
 
   __ Bind(&after_fn2);
   __ Bl(&fn2);
   __ Mov(x3, lr);
 
   __ Mov(lr, x29);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(core.xreg(3) + kInstructionSize, x0);
-  ASSERT_EQUAL_64(42, x1);
-  ASSERT_EQUAL_64(84, x2);
+  CHECK_EQUAL_64(core.xreg(3) + kInstructionSize, x0);
+  CHECK_EQUAL_64(42, x1);
+  CHECK_EQUAL_64(84, x2);
 
   TEARDOWN();
 }
 
 
 TEST(compare_branch) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 47 matching lines @@
   __ Cbnz(w18, &b);
   __ B(&b_end);
   __ Bind(&b);
   __ Mov(x5, 1);
   __ Bind(&b_end);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(0, x1);
-  ASSERT_EQUAL_64(1, x2);
-  ASSERT_EQUAL_64(0, x3);
-  ASSERT_EQUAL_64(1, x4);
-  ASSERT_EQUAL_64(0, x5);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(0, x1);
+  CHECK_EQUAL_64(1, x2);
+  CHECK_EQUAL_64(0, x3);
+  CHECK_EQUAL_64(1, x4);
+  CHECK_EQUAL_64(0, x5);
 
   TEARDOWN();
 }
 
 
 TEST(test_branch) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 27 matching lines @@
   Label nbo, nbo_end;
   __ Tbnz(w16, 2, &nbo);
   __ B(&nbo_end);
   __ Bind(&nbo);
   __ Mov(x3, 1);
   __ Bind(&nbo_end);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(0, x1);
-  ASSERT_EQUAL_64(1, x2);
-  ASSERT_EQUAL_64(0, x3);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(0, x1);
+  CHECK_EQUAL_64(1, x2);
+  CHECK_EQUAL_64(0, x3);
 
   TEARDOWN();
 }
 
 
 TEST(far_branch_backward) {
   INIT_V8();
 
   // Test that the MacroAssembler correctly resolves backward branches to labels
   // that are outside the immediate range of branch instructions.
@@ skipping 52 matching lines @@
   CHECK_GE(7 * kInstructionSize, __ SizeOfCodeGeneratedSince(&test_tbz));
 
   __ Bind(&fail);
   __ Mov(x1, 0);
   __ Bind(&done);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x7, x0);
-  ASSERT_EQUAL_64(0x1, x1);
+  CHECK_EQUAL_64(0x7, x0);
+  CHECK_EQUAL_64(0x1, x1);
 
   TEARDOWN();
 }
 
 
 TEST(far_branch_simple_veneer) {
   INIT_V8();
 
   // Test that the MacroAssembler correctly emits veneers for forward branches
   // to labels that are outside the immediate range of branch instructions.
@@ skipping 48 matching lines @@
 
   __ B(&done);
   __ Bind(&fail);
   __ Mov(x1, 0);
   __ Bind(&done);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x7, x0);
-  ASSERT_EQUAL_64(0x1, x1);
+  CHECK_EQUAL_64(0x7, x0);
+  CHECK_EQUAL_64(0x1, x1);
 
   TEARDOWN();
 }
 
 
 TEST(far_branch_veneer_link_chain) {
   INIT_V8();
 
   // Test that the MacroAssembler correctly emits veneers for forward branches
   // that target out-of-range labels and are part of multiple instructions
@@ skipping 73 matching lines @@
 
   __ B(&done);
   __ Bind(&fail);
   __ Mov(x1, 0);
   __ Bind(&done);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x7, x0);
-  ASSERT_EQUAL_64(0x1, x1);
+  CHECK_EQUAL_64(0x7, x0);
+  CHECK_EQUAL_64(0x1, x1);
 
   TEARDOWN();
 }
 
 
 TEST(far_branch_veneer_broken_link_chain) {
   INIT_V8();
 
   // Check that the MacroAssembler correctly handles the situation when removing
   // a branch from the link chain of a label and the two links on each side of
@@ skipping 68 matching lines @@
 
   __ B(&done);
   __ Bind(&fail);
   __ Mov(x1, 0);
   __ Bind(&done);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x3, x0);
-  ASSERT_EQUAL_64(0x1, x1);
+  CHECK_EQUAL_64(0x3, x0);
+  CHECK_EQUAL_64(0x1, x1);
 
   TEARDOWN();
 }
 
 
 TEST(branch_type) {
   INIT_V8();
 
   SETUP();
 
@@ skipping 36 matching lines @@
 
   __ Bind(&fail);
   __ Mov(x0, 0x1);
 
   __ Bind(&done);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x0, x0);
+  CHECK_EQUAL_64(0x0, x0);
 
   TEARDOWN();
 }
 
 
 TEST(ldr_str_offset) {
   INIT_V8();
   SETUP();
 
   uint64_t src[2] = {0xfedcba9876543210UL, 0x0123456789abcdefUL};
@@ skipping 11 matching lines @@
   __ Ldr(x2, MemOperand(x17, 8));
   __ Str(x2, MemOperand(x18, 16));
   __ Ldrb(w3, MemOperand(x17, 1));
   __ Strb(w3, MemOperand(x18, 25));
   __ Ldrh(w4, MemOperand(x17, 2));
   __ Strh(w4, MemOperand(x18, 33));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x76543210, x0);
-  ASSERT_EQUAL_64(0x76543210, dst[0]);
-  ASSERT_EQUAL_64(0xfedcba98, x1);
-  ASSERT_EQUAL_64(0xfedcba9800000000UL, dst[1]);
-  ASSERT_EQUAL_64(0x0123456789abcdefUL, x2);
-  ASSERT_EQUAL_64(0x0123456789abcdefUL, dst[2]);
-  ASSERT_EQUAL_64(0x32, x3);
-  ASSERT_EQUAL_64(0x3200, dst[3]);
-  ASSERT_EQUAL_64(0x7654, x4);
-  ASSERT_EQUAL_64(0x765400, dst[4]);
-  ASSERT_EQUAL_64(src_base, x17);
-  ASSERT_EQUAL_64(dst_base, x18);
+  CHECK_EQUAL_64(0x76543210, x0);
+  CHECK_EQUAL_64(0x76543210, dst[0]);
+  CHECK_EQUAL_64(0xfedcba98, x1);
+  CHECK_EQUAL_64(0xfedcba9800000000UL, dst[1]);
+  CHECK_EQUAL_64(0x0123456789abcdefUL, x2);
+  CHECK_EQUAL_64(0x0123456789abcdefUL, dst[2]);
+  CHECK_EQUAL_64(0x32, x3);
+  CHECK_EQUAL_64(0x3200, dst[3]);
+  CHECK_EQUAL_64(0x7654, x4);
+  CHECK_EQUAL_64(0x765400, dst[4]);
+  CHECK_EQUAL_64(src_base, x17);
+  CHECK_EQUAL_64(dst_base, x18);
 
   TEARDOWN();
 }
 
 
 TEST(ldr_str_wide) {
   INIT_V8();
   SETUP();
 
   uint32_t src[8192];
@@ skipping 17 matching lines @@
   __ Ldr(w0, MemOperand(x22, 8191 * sizeof(src[0])));
   __ Str(w0, MemOperand(x23, 8191 * sizeof(dst[0])));
   __ Ldr(w1, MemOperand(x24, 4096 * sizeof(src[0]), PostIndex));
   __ Str(w1, MemOperand(x25, 4096 * sizeof(dst[0]), PostIndex));
   __ Ldr(w2, MemOperand(x26, 6144 * sizeof(src[0]), PreIndex));
   __ Str(w2, MemOperand(x27, 6144 * sizeof(dst[0]), PreIndex));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(8191, w0);
-  ASSERT_EQUAL_32(8191, dst[8191]);
-  ASSERT_EQUAL_64(src_base, x22);
-  ASSERT_EQUAL_64(dst_base, x23);
-  ASSERT_EQUAL_32(0, w1);
-  ASSERT_EQUAL_32(0, dst[0]);
-  ASSERT_EQUAL_64(src_base + 4096 * sizeof(src[0]), x24);
-  ASSERT_EQUAL_64(dst_base + 4096 * sizeof(dst[0]), x25);
-  ASSERT_EQUAL_32(6144, w2);
-  ASSERT_EQUAL_32(6144, dst[6144]);
-  ASSERT_EQUAL_64(src_base + 6144 * sizeof(src[0]), x26);
-  ASSERT_EQUAL_64(dst_base + 6144 * sizeof(dst[0]), x27);
+  CHECK_EQUAL_32(8191, w0);
+  CHECK_EQUAL_32(8191, dst[8191]);
+  CHECK_EQUAL_64(src_base, x22);
+  CHECK_EQUAL_64(dst_base, x23);
+  CHECK_EQUAL_32(0, w1);
+  CHECK_EQUAL_32(0, dst[0]);
+  CHECK_EQUAL_64(src_base + 4096 * sizeof(src[0]), x24);
+  CHECK_EQUAL_64(dst_base + 4096 * sizeof(dst[0]), x25);
+  CHECK_EQUAL_32(6144, w2);
+  CHECK_EQUAL_32(6144, dst[6144]);
+  CHECK_EQUAL_64(src_base + 6144 * sizeof(src[0]), x26);
+  CHECK_EQUAL_64(dst_base + 6144 * sizeof(dst[0]), x27);
 
   TEARDOWN();
 }
 
 
 TEST(ldr_str_preindex) {
   INIT_V8();
   SETUP();
 
   uint64_t src[2] = {0xfedcba9876543210UL, 0x0123456789abcdefUL};
@@ skipping 19 matching lines @@
   __ Ldr(w2, MemOperand(x21, -4, PreIndex));
   __ Str(w2, MemOperand(x22, -4, PreIndex));
   __ Ldrb(w3, MemOperand(x23, 1, PreIndex));
   __ Strb(w3, MemOperand(x24, 25, PreIndex));
   __ Ldrh(w4, MemOperand(x25, 3, PreIndex));
   __ Strh(w4, MemOperand(x26, 41, PreIndex));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xfedcba98, x0);
-  ASSERT_EQUAL_64(0xfedcba9800000000UL, dst[1]);
-  ASSERT_EQUAL_64(0x0123456789abcdefUL, x1);
-  ASSERT_EQUAL_64(0x0123456789abcdefUL, dst[2]);
-  ASSERT_EQUAL_64(0x01234567, x2);
-  ASSERT_EQUAL_64(0x0123456700000000UL, dst[4]);
-  ASSERT_EQUAL_64(0x32, x3);
-  ASSERT_EQUAL_64(0x3200, dst[3]);
-  ASSERT_EQUAL_64(0x9876, x4);
-  ASSERT_EQUAL_64(0x987600, dst[5]);
-  ASSERT_EQUAL_64(src_base + 4, x17);
-  ASSERT_EQUAL_64(dst_base + 12, x18);
-  ASSERT_EQUAL_64(src_base + 8, x19);
-  ASSERT_EQUAL_64(dst_base + 16, x20);
-  ASSERT_EQUAL_64(src_base + 12, x21);
-  ASSERT_EQUAL_64(dst_base + 36, x22);
-  ASSERT_EQUAL_64(src_base + 1, x23);
-  ASSERT_EQUAL_64(dst_base + 25, x24);
-  ASSERT_EQUAL_64(src_base + 3, x25);
-  ASSERT_EQUAL_64(dst_base + 41, x26);
+  CHECK_EQUAL_64(0xfedcba98, x0);
+  CHECK_EQUAL_64(0xfedcba9800000000UL, dst[1]);
+  CHECK_EQUAL_64(0x0123456789abcdefUL, x1);
+  CHECK_EQUAL_64(0x0123456789abcdefUL, dst[2]);
+  CHECK_EQUAL_64(0x01234567, x2);
+  CHECK_EQUAL_64(0x0123456700000000UL, dst[4]);
+  CHECK_EQUAL_64(0x32, x3);
+  CHECK_EQUAL_64(0x3200, dst[3]);
+  CHECK_EQUAL_64(0x9876, x4);
+  CHECK_EQUAL_64(0x987600, dst[5]);
+  CHECK_EQUAL_64(src_base + 4, x17);
+  CHECK_EQUAL_64(dst_base + 12, x18);
+  CHECK_EQUAL_64(src_base + 8, x19);
+  CHECK_EQUAL_64(dst_base + 16, x20);
+  CHECK_EQUAL_64(src_base + 12, x21);
+  CHECK_EQUAL_64(dst_base + 36, x22);
+  CHECK_EQUAL_64(src_base + 1, x23);
+  CHECK_EQUAL_64(dst_base + 25, x24);
+  CHECK_EQUAL_64(src_base + 3, x25);
+  CHECK_EQUAL_64(dst_base + 41, x26);
 
   TEARDOWN();
 }
 
 
 TEST(ldr_str_postindex) {
   INIT_V8();
   SETUP();
 
   uint64_t src[2] = {0xfedcba9876543210UL, 0x0123456789abcdefUL};
@@ skipping 19 matching lines @@
   __ Ldr(x2, MemOperand(x21, -8, PostIndex));
   __ Str(x2, MemOperand(x22, -32, PostIndex));
   __ Ldrb(w3, MemOperand(x23, 1, PostIndex));
   __ Strb(w3, MemOperand(x24, 5, PostIndex));
   __ Ldrh(w4, MemOperand(x25, -3, PostIndex));
   __ Strh(w4, MemOperand(x26, -41, PostIndex));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xfedcba98, x0);
-  ASSERT_EQUAL_64(0xfedcba9800000000UL, dst[1]);
-  ASSERT_EQUAL_64(0x0123456789abcdefUL, x1);
-  ASSERT_EQUAL_64(0x0123456789abcdefUL, dst[2]);
-  ASSERT_EQUAL_64(0x0123456789abcdefUL, x2);
-  ASSERT_EQUAL_64(0x0123456789abcdefUL, dst[4]);
-  ASSERT_EQUAL_64(0x32, x3);
-  ASSERT_EQUAL_64(0x3200, dst[3]);
-  ASSERT_EQUAL_64(0x9876, x4);
-  ASSERT_EQUAL_64(0x987600, dst[5]);
-  ASSERT_EQUAL_64(src_base + 8, x17);
-  ASSERT_EQUAL_64(dst_base + 24, x18);
-  ASSERT_EQUAL_64(src_base + 16, x19);
-  ASSERT_EQUAL_64(dst_base + 32, x20);
-  ASSERT_EQUAL_64(src_base, x21);
-  ASSERT_EQUAL_64(dst_base, x22);
-  ASSERT_EQUAL_64(src_base + 2, x23);
-  ASSERT_EQUAL_64(dst_base + 30, x24);
-  ASSERT_EQUAL_64(src_base, x25);
-  ASSERT_EQUAL_64(dst_base, x26);
+  CHECK_EQUAL_64(0xfedcba98, x0);
+  CHECK_EQUAL_64(0xfedcba9800000000UL, dst[1]);
+  CHECK_EQUAL_64(0x0123456789abcdefUL, x1);
+  CHECK_EQUAL_64(0x0123456789abcdefUL, dst[2]);
+  CHECK_EQUAL_64(0x0123456789abcdefUL, x2);
+  CHECK_EQUAL_64(0x0123456789abcdefUL, dst[4]);
+  CHECK_EQUAL_64(0x32, x3);
+  CHECK_EQUAL_64(0x3200, dst[3]);
+  CHECK_EQUAL_64(0x9876, x4);
+  CHECK_EQUAL_64(0x987600, dst[5]);
+  CHECK_EQUAL_64(src_base + 8, x17);
+  CHECK_EQUAL_64(dst_base + 24, x18);
+  CHECK_EQUAL_64(src_base + 16, x19);
+  CHECK_EQUAL_64(dst_base + 32, x20);
+  CHECK_EQUAL_64(src_base, x21);
+  CHECK_EQUAL_64(dst_base, x22);
+  CHECK_EQUAL_64(src_base + 2, x23);
+  CHECK_EQUAL_64(dst_base + 30, x24);
+  CHECK_EQUAL_64(src_base, x25);
+  CHECK_EQUAL_64(dst_base, x26);
 
   TEARDOWN();
 }
 
 
 TEST(load_signed) {
   INIT_V8();
   SETUP();
 
   uint32_t src[2] = {0x80008080, 0x7fff7f7f};
   uintptr_t src_base = reinterpret_cast<uintptr_t>(src);
 
   START();
   __ Mov(x24, src_base);
   __ Ldrsb(w0, MemOperand(x24));
   __ Ldrsb(w1, MemOperand(x24, 4));
   __ Ldrsh(w2, MemOperand(x24));
   __ Ldrsh(w3, MemOperand(x24, 4));
   __ Ldrsb(x4, MemOperand(x24));
   __ Ldrsb(x5, MemOperand(x24, 4));
   __ Ldrsh(x6, MemOperand(x24));
   __ Ldrsh(x7, MemOperand(x24, 4));
   __ Ldrsw(x8, MemOperand(x24));
   __ Ldrsw(x9, MemOperand(x24, 4));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffff80, x0);
-  ASSERT_EQUAL_64(0x0000007f, x1);
-  ASSERT_EQUAL_64(0xffff8080, x2);
-  ASSERT_EQUAL_64(0x00007f7f, x3);
-  ASSERT_EQUAL_64(0xffffffffffffff80UL, x4);
-  ASSERT_EQUAL_64(0x000000000000007fUL, x5);
-  ASSERT_EQUAL_64(0xffffffffffff8080UL, x6);
-  ASSERT_EQUAL_64(0x0000000000007f7fUL, x7);
-  ASSERT_EQUAL_64(0xffffffff80008080UL, x8);
-  ASSERT_EQUAL_64(0x000000007fff7f7fUL, x9);
+  CHECK_EQUAL_64(0xffffff80, x0);
+  CHECK_EQUAL_64(0x0000007f, x1);
+  CHECK_EQUAL_64(0xffff8080, x2);
+  CHECK_EQUAL_64(0x00007f7f, x3);
+  CHECK_EQUAL_64(0xffffffffffffff80UL, x4);
+  CHECK_EQUAL_64(0x000000000000007fUL, x5);
+  CHECK_EQUAL_64(0xffffffffffff8080UL, x6);
+  CHECK_EQUAL_64(0x0000000000007f7fUL, x7);
+  CHECK_EQUAL_64(0xffffffff80008080UL, x8);
+  CHECK_EQUAL_64(0x000000007fff7f7fUL, x9);
 
   TEARDOWN();
 }
 
 
 TEST(load_store_regoffset) {
   INIT_V8();
   SETUP();
 
   uint32_t src[3] = {1, 2, 3};
@@ skipping 19 matching lines @@
   __ Ldr(w2, MemOperand(x18, x26));
   __ Ldr(w3, MemOperand(x18, x27, SXTW));
   __ Ldr(w4, MemOperand(x18, x28, SXTW, 2));
   __ Str(w0, MemOperand(x17, x24));
   __ Str(x1, MemOperand(x17, x25));
   __ Str(w2, MemOperand(x20, x29, SXTW, 2));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(0x0000000300000002UL, x1);
-  ASSERT_EQUAL_64(3, x2);
-  ASSERT_EQUAL_64(3, x3);
-  ASSERT_EQUAL_64(2, x4);
-  ASSERT_EQUAL_32(1, dst[0]);
-  ASSERT_EQUAL_32(2, dst[1]);
-  ASSERT_EQUAL_32(3, dst[2]);
-  ASSERT_EQUAL_32(3, dst[3]);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(0x0000000300000002UL, x1);
+  CHECK_EQUAL_64(3, x2);
+  CHECK_EQUAL_64(3, x3);
+  CHECK_EQUAL_64(2, x4);
+  CHECK_EQUAL_32(1, dst[0]);
+  CHECK_EQUAL_32(2, dst[1]);
+  CHECK_EQUAL_32(3, dst[2]);
+  CHECK_EQUAL_32(3, dst[3]);
 
   TEARDOWN();
 }
 
 
 TEST(load_store_float) {
   INIT_V8();
   SETUP();
 
   float src[3] = {1.0, 2.0, 3.0};
@@ skipping 11 matching lines @@
   __ Ldr(s0, MemOperand(x17, sizeof(src[0])));
   __ Str(s0, MemOperand(x18, sizeof(dst[0]), PostIndex));
   __ Ldr(s1, MemOperand(x19, sizeof(src[0]), PostIndex));
   __ Str(s1, MemOperand(x20, 2 * sizeof(dst[0]), PreIndex));
   __ Ldr(s2, MemOperand(x21, 2 * sizeof(src[0]), PreIndex));
   __ Str(s2, MemOperand(x22, sizeof(dst[0])));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(2.0, s0);
-  ASSERT_EQUAL_FP32(2.0, dst[0]);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(1.0, dst[2]);
-  ASSERT_EQUAL_FP32(3.0, s2);
-  ASSERT_EQUAL_FP32(3.0, dst[1]);
-  ASSERT_EQUAL_64(src_base, x17);
-  ASSERT_EQUAL_64(dst_base + sizeof(dst[0]), x18);
-  ASSERT_EQUAL_64(src_base + sizeof(src[0]), x19);
-  ASSERT_EQUAL_64(dst_base + 2 * sizeof(dst[0]), x20);
-  ASSERT_EQUAL_64(src_base + 2 * sizeof(src[0]), x21);
-  ASSERT_EQUAL_64(dst_base, x22);
+  CHECK_EQUAL_FP32(2.0, s0);
+  CHECK_EQUAL_FP32(2.0, dst[0]);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(1.0, dst[2]);
+  CHECK_EQUAL_FP32(3.0, s2);
+  CHECK_EQUAL_FP32(3.0, dst[1]);
+  CHECK_EQUAL_64(src_base, x17);
+  CHECK_EQUAL_64(dst_base + sizeof(dst[0]), x18);
+  CHECK_EQUAL_64(src_base + sizeof(src[0]), x19);
+  CHECK_EQUAL_64(dst_base + 2 * sizeof(dst[0]), x20);
+  CHECK_EQUAL_64(src_base + 2 * sizeof(src[0]), x21);
+  CHECK_EQUAL_64(dst_base, x22);
 
   TEARDOWN();
 }
 
 
 TEST(load_store_double) {
   INIT_V8();
   SETUP();
 
   double src[3] = {1.0, 2.0, 3.0};
@@ skipping 11 matching lines @@
   __ Ldr(d0, MemOperand(x17, sizeof(src[0])));
   __ Str(d0, MemOperand(x18, sizeof(dst[0]), PostIndex));
   __ Ldr(d1, MemOperand(x19, sizeof(src[0]), PostIndex));
   __ Str(d1, MemOperand(x20, 2 * sizeof(dst[0]), PreIndex));
   __ Ldr(d2, MemOperand(x21, 2 * sizeof(src[0]), PreIndex));
   __ Str(d2, MemOperand(x22, sizeof(dst[0])));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP64(2.0, d0);
-  ASSERT_EQUAL_FP64(2.0, dst[0]);
-  ASSERT_EQUAL_FP64(1.0, d1);
-  ASSERT_EQUAL_FP64(1.0, dst[2]);
-  ASSERT_EQUAL_FP64(3.0, d2);
-  ASSERT_EQUAL_FP64(3.0, dst[1]);
-  ASSERT_EQUAL_64(src_base, x17);
-  ASSERT_EQUAL_64(dst_base + sizeof(dst[0]), x18);
-  ASSERT_EQUAL_64(src_base + sizeof(src[0]), x19);
-  ASSERT_EQUAL_64(dst_base + 2 * sizeof(dst[0]), x20);
-  ASSERT_EQUAL_64(src_base + 2 * sizeof(src[0]), x21);
-  ASSERT_EQUAL_64(dst_base, x22);
+  CHECK_EQUAL_FP64(2.0, d0);
+  CHECK_EQUAL_FP64(2.0, dst[0]);
+  CHECK_EQUAL_FP64(1.0, d1);
+  CHECK_EQUAL_FP64(1.0, dst[2]);
+  CHECK_EQUAL_FP64(3.0, d2);
+  CHECK_EQUAL_FP64(3.0, dst[1]);
+  CHECK_EQUAL_64(src_base, x17);
+  CHECK_EQUAL_64(dst_base + sizeof(dst[0]), x18);
+  CHECK_EQUAL_64(src_base + sizeof(src[0]), x19);
+  CHECK_EQUAL_64(dst_base + 2 * sizeof(dst[0]), x20);
+  CHECK_EQUAL_64(src_base + 2 * sizeof(src[0]), x21);
+  CHECK_EQUAL_64(dst_base, x22);
 
   TEARDOWN();
 }
 
 
 TEST(ldp_stp_float) {
   INIT_V8();
   SETUP();
 
   float src[2] = {1.0, 2.0};
   float dst[3] = {0.0, 0.0, 0.0};
   uintptr_t src_base = reinterpret_cast<uintptr_t>(src);
   uintptr_t dst_base = reinterpret_cast<uintptr_t>(dst);
 
   START();
   __ Mov(x16, src_base);
   __ Mov(x17, dst_base);
   __ Ldp(s31, s0, MemOperand(x16, 2 * sizeof(src[0]), PostIndex));
   __ Stp(s0, s31, MemOperand(x17, sizeof(dst[1]), PreIndex));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(1.0, s31);
-  ASSERT_EQUAL_FP32(2.0, s0);
-  ASSERT_EQUAL_FP32(0.0, dst[0]);
-  ASSERT_EQUAL_FP32(2.0, dst[1]);
-  ASSERT_EQUAL_FP32(1.0, dst[2]);
-  ASSERT_EQUAL_64(src_base + 2 * sizeof(src[0]), x16);
-  ASSERT_EQUAL_64(dst_base + sizeof(dst[1]), x17);
+  CHECK_EQUAL_FP32(1.0, s31);
+  CHECK_EQUAL_FP32(2.0, s0);
+  CHECK_EQUAL_FP32(0.0, dst[0]);
+  CHECK_EQUAL_FP32(2.0, dst[1]);
+  CHECK_EQUAL_FP32(1.0, dst[2]);
+  CHECK_EQUAL_64(src_base + 2 * sizeof(src[0]), x16);
+  CHECK_EQUAL_64(dst_base + sizeof(dst[1]), x17);
 
   TEARDOWN();
 }
 
 
 TEST(ldp_stp_double) {
   INIT_V8();
   SETUP();
 
   double src[2] = {1.0, 2.0};
   double dst[3] = {0.0, 0.0, 0.0};
   uintptr_t src_base = reinterpret_cast<uintptr_t>(src);
   uintptr_t dst_base = reinterpret_cast<uintptr_t>(dst);
 
   START();
   __ Mov(x16, src_base);
   __ Mov(x17, dst_base);
   __ Ldp(d31, d0, MemOperand(x16, 2 * sizeof(src[0]), PostIndex));
   __ Stp(d0, d31, MemOperand(x17, sizeof(dst[1]), PreIndex));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP64(1.0, d31);
-  ASSERT_EQUAL_FP64(2.0, d0);
-  ASSERT_EQUAL_FP64(0.0, dst[0]);
-  ASSERT_EQUAL_FP64(2.0, dst[1]);
-  ASSERT_EQUAL_FP64(1.0, dst[2]);
-  ASSERT_EQUAL_64(src_base + 2 * sizeof(src[0]), x16);
-  ASSERT_EQUAL_64(dst_base + sizeof(dst[1]), x17);
+  CHECK_EQUAL_FP64(1.0, d31);
+  CHECK_EQUAL_FP64(2.0, d0);
+  CHECK_EQUAL_FP64(0.0, dst[0]);
+  CHECK_EQUAL_FP64(2.0, dst[1]);
+  CHECK_EQUAL_FP64(1.0, dst[2]);
+  CHECK_EQUAL_64(src_base + 2 * sizeof(src[0]), x16);
+  CHECK_EQUAL_64(dst_base + sizeof(dst[1]), x17);
 
   TEARDOWN();
 }
 
 
 TEST(ldp_stp_offset) {
   INIT_V8();
   SETUP();
 
   uint64_t src[3] = {0x0011223344556677UL, 0x8899aabbccddeeffUL,
@@ skipping 14 matching lines @@
   __ Ldp(x8, x9, MemOperand(x18, -16));
   __ Stp(w0, w1, MemOperand(x17));
   __ Stp(w2, w3, MemOperand(x17, 8));
   __ Stp(x4, x5, MemOperand(x17, 16));
   __ Stp(w6, w7, MemOperand(x19, -24));
   __ Stp(x8, x9, MemOperand(x19, -16));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x44556677, x0);
-  ASSERT_EQUAL_64(0x00112233, x1);
-  ASSERT_EQUAL_64(0x0011223344556677UL, dst[0]);
-  ASSERT_EQUAL_64(0x00112233, x2);
-  ASSERT_EQUAL_64(0xccddeeff, x3);
-  ASSERT_EQUAL_64(0xccddeeff00112233UL, dst[1]);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, x4);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, dst[2]);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, x5);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, dst[3]);
-  ASSERT_EQUAL_64(0x8899aabb, x6);
-  ASSERT_EQUAL_64(0xbbaa9988, x7);
-  ASSERT_EQUAL_64(0xbbaa99888899aabbUL, dst[4]);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, x8);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, dst[5]);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, x9);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, dst[6]);
-  ASSERT_EQUAL_64(src_base, x16);
-  ASSERT_EQUAL_64(dst_base, x17);
-  ASSERT_EQUAL_64(src_base + 24, x18);
-  ASSERT_EQUAL_64(dst_base + 56, x19);
+  CHECK_EQUAL_64(0x44556677, x0);
+  CHECK_EQUAL_64(0x00112233, x1);
+  CHECK_EQUAL_64(0x0011223344556677UL, dst[0]);
+  CHECK_EQUAL_64(0x00112233, x2);
+  CHECK_EQUAL_64(0xccddeeff, x3);
+  CHECK_EQUAL_64(0xccddeeff00112233UL, dst[1]);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, x4);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, dst[2]);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, x5);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, dst[3]);
+  CHECK_EQUAL_64(0x8899aabb, x6);
+  CHECK_EQUAL_64(0xbbaa9988, x7);
+  CHECK_EQUAL_64(0xbbaa99888899aabbUL, dst[4]);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, x8);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, dst[5]);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, x9);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, dst[6]);
+  CHECK_EQUAL_64(src_base, x16);
+  CHECK_EQUAL_64(dst_base, x17);
+  CHECK_EQUAL_64(src_base + 24, x18);
+  CHECK_EQUAL_64(dst_base + 56, x19);
 
   TEARDOWN();
 }
 
 
 TEST(ldnp_stnp_offset) {
   INIT_V8();
   SETUP();
 
   uint64_t src[3] = {0x0011223344556677UL, 0x8899aabbccddeeffUL,
@@ skipping 14 matching lines @@
   __ Ldnp(x8, x9, MemOperand(x18, -16));
   __ Stnp(w0, w1, MemOperand(x17));
   __ Stnp(w2, w3, MemOperand(x17, 8));
   __ Stnp(x4, x5, MemOperand(x17, 16));
   __ Stnp(w6, w7, MemOperand(x19, -24));
   __ Stnp(x8, x9, MemOperand(x19, -16));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x44556677, x0);
-  ASSERT_EQUAL_64(0x00112233, x1);
-  ASSERT_EQUAL_64(0x0011223344556677UL, dst[0]);
-  ASSERT_EQUAL_64(0x00112233, x2);
-  ASSERT_EQUAL_64(0xccddeeff, x3);
-  ASSERT_EQUAL_64(0xccddeeff00112233UL, dst[1]);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, x4);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, dst[2]);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, x5);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, dst[3]);
-  ASSERT_EQUAL_64(0x8899aabb, x6);
-  ASSERT_EQUAL_64(0xbbaa9988, x7);
-  ASSERT_EQUAL_64(0xbbaa99888899aabbUL, dst[4]);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, x8);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, dst[5]);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, x9);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, dst[6]);
-  ASSERT_EQUAL_64(src_base, x16);
-  ASSERT_EQUAL_64(dst_base, x17);
-  ASSERT_EQUAL_64(src_base + 24, x18);
-  ASSERT_EQUAL_64(dst_base + 56, x19);
+  CHECK_EQUAL_64(0x44556677, x0);
+  CHECK_EQUAL_64(0x00112233, x1);
+  CHECK_EQUAL_64(0x0011223344556677UL, dst[0]);
+  CHECK_EQUAL_64(0x00112233, x2);
+  CHECK_EQUAL_64(0xccddeeff, x3);
+  CHECK_EQUAL_64(0xccddeeff00112233UL, dst[1]);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, x4);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, dst[2]);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, x5);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, dst[3]);
+  CHECK_EQUAL_64(0x8899aabb, x6);
+  CHECK_EQUAL_64(0xbbaa9988, x7);
+  CHECK_EQUAL_64(0xbbaa99888899aabbUL, dst[4]);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, x8);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, dst[5]);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, x9);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, dst[6]);
+  CHECK_EQUAL_64(src_base, x16);
+  CHECK_EQUAL_64(dst_base, x17);
+  CHECK_EQUAL_64(src_base + 24, x18);
+  CHECK_EQUAL_64(dst_base + 56, x19);
 
   TEARDOWN();
 }
 
 
 TEST(ldp_stp_preindex) {
   INIT_V8();
   SETUP();
 
   uint64_t src[3] = {0x0011223344556677UL, 0x8899aabbccddeeffUL,
@@ skipping 15 matching lines @@
   __ Ldp(x4, x5, MemOperand(x16, 8, PreIndex));
   __ Mov(x21, x16);
   __ Ldp(x6, x7, MemOperand(x16, -8, PreIndex));
   __ Stp(x7, x6, MemOperand(x18, 8, PreIndex));
   __ Mov(x22, x18);
   __ Stp(x5, x4, MemOperand(x18, -8, PreIndex));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x00112233, x0);
-  ASSERT_EQUAL_64(0xccddeeff, x1);
-  ASSERT_EQUAL_64(0x44556677, x2);
-  ASSERT_EQUAL_64(0x00112233, x3);
-  ASSERT_EQUAL_64(0xccddeeff00112233UL, dst[0]);
-  ASSERT_EQUAL_64(0x0000000000112233UL, dst[1]);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, x4);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, x5);
-  ASSERT_EQUAL_64(0x0011223344556677UL, x6);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, x7);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, dst[2]);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, dst[3]);
-  ASSERT_EQUAL_64(0x0011223344556677UL, dst[4]);
-  ASSERT_EQUAL_64(src_base, x16);
-  ASSERT_EQUAL_64(dst_base, x17);
-  ASSERT_EQUAL_64(dst_base + 16, x18);
-  ASSERT_EQUAL_64(src_base + 4, x19);
-  ASSERT_EQUAL_64(dst_base + 4, x20);
-  ASSERT_EQUAL_64(src_base + 8, x21);
-  ASSERT_EQUAL_64(dst_base + 24, x22);
+  CHECK_EQUAL_64(0x00112233, x0);
+  CHECK_EQUAL_64(0xccddeeff, x1);
+  CHECK_EQUAL_64(0x44556677, x2);
+  CHECK_EQUAL_64(0x00112233, x3);
+  CHECK_EQUAL_64(0xccddeeff00112233UL, dst[0]);
+  CHECK_EQUAL_64(0x0000000000112233UL, dst[1]);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, x4);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, x5);
+  CHECK_EQUAL_64(0x0011223344556677UL, x6);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, x7);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, dst[2]);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, dst[3]);
+  CHECK_EQUAL_64(0x0011223344556677UL, dst[4]);
+  CHECK_EQUAL_64(src_base, x16);
+  CHECK_EQUAL_64(dst_base, x17);
+  CHECK_EQUAL_64(dst_base + 16, x18);
+  CHECK_EQUAL_64(src_base + 4, x19);
+  CHECK_EQUAL_64(dst_base + 4, x20);
+  CHECK_EQUAL_64(src_base + 8, x21);
+  CHECK_EQUAL_64(dst_base + 24, x22);
 
   TEARDOWN();
 }
 
 
 TEST(ldp_stp_postindex) {
   INIT_V8();
   SETUP();
 
   uint64_t src[4] = {0x0011223344556677UL, 0x8899aabbccddeeffUL,
@@ skipping 15 matching lines @@
   __ Ldp(x4, x5, MemOperand(x16, 8, PostIndex));
   __ Mov(x21, x16);
   __ Ldp(x6, x7, MemOperand(x16, -8, PostIndex));
   __ Stp(x7, x6, MemOperand(x18, 8, PostIndex));
   __ Mov(x22, x18);
   __ Stp(x5, x4, MemOperand(x18, -8, PostIndex));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x44556677, x0);
-  ASSERT_EQUAL_64(0x00112233, x1);
-  ASSERT_EQUAL_64(0x00112233, x2);
-  ASSERT_EQUAL_64(0xccddeeff, x3);
-  ASSERT_EQUAL_64(0x4455667700112233UL, dst[0]);
-  ASSERT_EQUAL_64(0x0000000000112233UL, dst[1]);
-  ASSERT_EQUAL_64(0x0011223344556677UL, x4);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, x5);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, x6);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, x7);
-  ASSERT_EQUAL_64(0xffeeddccbbaa9988UL, dst[2]);
-  ASSERT_EQUAL_64(0x8899aabbccddeeffUL, dst[3]);
-  ASSERT_EQUAL_64(0x0011223344556677UL, dst[4]);
-  ASSERT_EQUAL_64(src_base, x16);
-  ASSERT_EQUAL_64(dst_base, x17);
-  ASSERT_EQUAL_64(dst_base + 16, x18);
-  ASSERT_EQUAL_64(src_base + 4, x19);
-  ASSERT_EQUAL_64(dst_base + 4, x20);
-  ASSERT_EQUAL_64(src_base + 8, x21);
-  ASSERT_EQUAL_64(dst_base + 24, x22);
+  CHECK_EQUAL_64(0x44556677, x0);
+  CHECK_EQUAL_64(0x00112233, x1);
+  CHECK_EQUAL_64(0x00112233, x2);
+  CHECK_EQUAL_64(0xccddeeff, x3);
+  CHECK_EQUAL_64(0x4455667700112233UL, dst[0]);
+  CHECK_EQUAL_64(0x0000000000112233UL, dst[1]);
+  CHECK_EQUAL_64(0x0011223344556677UL, x4);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, x5);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, x6);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, x7);
+  CHECK_EQUAL_64(0xffeeddccbbaa9988UL, dst[2]);
+  CHECK_EQUAL_64(0x8899aabbccddeeffUL, dst[3]);
+  CHECK_EQUAL_64(0x0011223344556677UL, dst[4]);
+  CHECK_EQUAL_64(src_base, x16);
+  CHECK_EQUAL_64(dst_base, x17);
+  CHECK_EQUAL_64(dst_base + 16, x18);
+  CHECK_EQUAL_64(src_base + 4, x19);
+  CHECK_EQUAL_64(dst_base + 4, x20);
+  CHECK_EQUAL_64(src_base + 8, x21);
+  CHECK_EQUAL_64(dst_base + 24, x22);
 
   TEARDOWN();
 }
 
 
 TEST(ldp_sign_extend) {
   INIT_V8();
   SETUP();
 
   uint32_t src[2] = {0x80000000, 0x7fffffff};
   uintptr_t src_base = reinterpret_cast<uintptr_t>(src);
 
   START();
   __ Mov(x24, src_base);
   __ Ldpsw(x0, x1, MemOperand(x24));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffffff80000000UL, x0);
-  ASSERT_EQUAL_64(0x000000007fffffffUL, x1);
+  CHECK_EQUAL_64(0xffffffff80000000UL, x0);
+  CHECK_EQUAL_64(0x000000007fffffffUL, x1);
 
   TEARDOWN();
 }
 
 
 TEST(ldur_stur) {
   INIT_V8();
   SETUP();
 
   int64_t src[2] = {0x0123456789abcdefUL, 0x0123456789abcdefUL};
@@ skipping 12 matching lines @@
   __ Ldr(x1, MemOperand(x17, 3));
   __ Str(x1, MemOperand(x18, 9));
   __ Ldr(w2, MemOperand(x19, -9));
   __ Str(w2, MemOperand(x20, -5));
   __ Ldrb(w3, MemOperand(x19, -1));
   __ Strb(w3, MemOperand(x21, -1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x6789abcd, x0);
-  ASSERT_EQUAL_64(0x6789abcd0000L, dst[0]);
-  ASSERT_EQUAL_64(0xabcdef0123456789L, x1);
-  ASSERT_EQUAL_64(0xcdef012345678900L, dst[1]);
-  ASSERT_EQUAL_64(0x000000ab, dst[2]);
-  ASSERT_EQUAL_64(0xabcdef01, x2);
-  ASSERT_EQUAL_64(0x00abcdef01000000L, dst[3]);
-  ASSERT_EQUAL_64(0x00000001, x3);
-  ASSERT_EQUAL_64(0x0100000000000000L, dst[4]);
-  ASSERT_EQUAL_64(src_base, x17);
-  ASSERT_EQUAL_64(dst_base, x18);
-  ASSERT_EQUAL_64(src_base + 16, x19);
-  ASSERT_EQUAL_64(dst_base + 32, x20);
+  CHECK_EQUAL_64(0x6789abcd, x0);
+  CHECK_EQUAL_64(0x6789abcd0000L, dst[0]);
+  CHECK_EQUAL_64(0xabcdef0123456789L, x1);
+  CHECK_EQUAL_64(0xcdef012345678900L, dst[1]);
+  CHECK_EQUAL_64(0x000000ab, dst[2]);
+  CHECK_EQUAL_64(0xabcdef01, x2);
+  CHECK_EQUAL_64(0x00abcdef01000000L, dst[3]);
+  CHECK_EQUAL_64(0x00000001, x3);
+  CHECK_EQUAL_64(0x0100000000000000L, dst[4]);
+  CHECK_EQUAL_64(src_base, x17);
+  CHECK_EQUAL_64(dst_base, x18);
+  CHECK_EQUAL_64(src_base + 16, x19);
+  CHECK_EQUAL_64(dst_base + 32, x20);
 
   TEARDOWN();
 }
 
 
 #if 0  // TODO(all) enable.
 // TODO(rodolph): Adapt w16 Literal tests for RelocInfo.
 TEST(ldr_literal) {
   INIT_V8();
   SETUP();
 
   START();
   __ Ldr(x2, 0x1234567890abcdefUL);
   __ Ldr(w3, 0xfedcba09);
   __ Ldr(d13, 1.234);
   __ Ldr(s25, 2.5);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1234567890abcdefUL, x2);
-  ASSERT_EQUAL_64(0xfedcba09, x3);
-  ASSERT_EQUAL_FP64(1.234, d13);
-  ASSERT_EQUAL_FP32(2.5, s25);
+  CHECK_EQUAL_64(0x1234567890abcdefUL, x2);
+  CHECK_EQUAL_64(0xfedcba09, x3);
+  CHECK_EQUAL_FP64(1.234, d13);
+  CHECK_EQUAL_FP32(2.5, s25);
 
   TEARDOWN();
 }
 
 
 static void LdrLiteralRangeHelper(ptrdiff_t range_,
                                   LiteralPoolEmitOption option,
                                   bool expect_dump) {
-  ASSERT(range_ > 0);
+  DCHECK(range_ > 0);
   SETUP_SIZE(range_ + 1024);
 
   Label label_1, label_2;
 
   size_t range = static_cast<size_t>(range_);
   size_t code_size = 0;
   size_t pool_guard_size;
 
   if (option == NoJumpRequired) {
     // Space for an explicit branch.
     pool_guard_size = sizeof(Instr);
   } else {
     pool_guard_size = 0;
   }
 
   START();
   // Force a pool dump so the pool starts off empty.
   __ EmitLiteralPool(JumpRequired);
-  ASSERT_LITERAL_POOL_SIZE(0);
+  DCHECK_LITERAL_POOL_SIZE(0);
 
   __ Ldr(x0, 0x1234567890abcdefUL);
   __ Ldr(w1, 0xfedcba09);
   __ Ldr(d0, 1.234);
   __ Ldr(s1, 2.5);
-  ASSERT_LITERAL_POOL_SIZE(4);
+  DCHECK_LITERAL_POOL_SIZE(4);
 
   code_size += 4 * sizeof(Instr);
 
   // Check that the requested range (allowing space for a branch over the pool)
   // can be handled by this test.
-  ASSERT((code_size + pool_guard_size) <= range);
+  DCHECK((code_size + pool_guard_size) <= range);
 
   // Emit NOPs up to 'range', leaving space for the pool guard.
   while ((code_size + pool_guard_size) < range) {
     __ Nop();
     code_size += sizeof(Instr);
   }
 
   // Emit the guard sequence before the literal pool.
   if (option == NoJumpRequired) {
     __ B(&label_1);
     code_size += sizeof(Instr);
   }
 
-  ASSERT(code_size == range);
-  ASSERT_LITERAL_POOL_SIZE(4);
+  DCHECK(code_size == range);
+  DCHECK_LITERAL_POOL_SIZE(4);
 
   // Possibly generate a literal pool.
   __ CheckLiteralPool(option);
   __ Bind(&label_1);
   if (expect_dump) {
-    ASSERT_LITERAL_POOL_SIZE(0);
+    DCHECK_LITERAL_POOL_SIZE(0);
   } else {
-    ASSERT_LITERAL_POOL_SIZE(4);
+    DCHECK_LITERAL_POOL_SIZE(4);
   }
 
   // Force a pool flush to check that a second pool functions correctly.
   __ EmitLiteralPool(JumpRequired);
-  ASSERT_LITERAL_POOL_SIZE(0);
+  DCHECK_LITERAL_POOL_SIZE(0);
 
   // These loads should be after the pool (and will require a new one).
   __ Ldr(x4, 0x34567890abcdef12UL);
   __ Ldr(w5, 0xdcba09fe);
   __ Ldr(d4, 123.4);
   __ Ldr(s5, 250.0);
-  ASSERT_LITERAL_POOL_SIZE(4);
+  DCHECK_LITERAL_POOL_SIZE(4);
   END();
 
   RUN();
 
   // Check that the literals loaded correctly.
-  ASSERT_EQUAL_64(0x1234567890abcdefUL, x0);
-  ASSERT_EQUAL_64(0xfedcba09, x1);
-  ASSERT_EQUAL_FP64(1.234, d0);
-  ASSERT_EQUAL_FP32(2.5, s1);
-  ASSERT_EQUAL_64(0x34567890abcdef12UL, x4);
-  ASSERT_EQUAL_64(0xdcba09fe, x5);
-  ASSERT_EQUAL_FP64(123.4, d4);
-  ASSERT_EQUAL_FP32(250.0, s5);
+  CHECK_EQUAL_64(0x1234567890abcdefUL, x0);
+  CHECK_EQUAL_64(0xfedcba09, x1);
+  CHECK_EQUAL_FP64(1.234, d0);
+  CHECK_EQUAL_FP32(2.5, s1);
+  CHECK_EQUAL_64(0x34567890abcdef12UL, x4);
+  CHECK_EQUAL_64(0xdcba09fe, x5);
+  CHECK_EQUAL_FP64(123.4, d4);
+  CHECK_EQUAL_FP32(250.0, s5);
 
   TEARDOWN();
 }
 
 
 TEST(ldr_literal_range_1) {
   INIT_V8();
   LdrLiteralRangeHelper(kRecommendedLiteralPoolRange,
                         NoJumpRequired,
                         true);
@@ skipping 66 matching lines @@
   __ Sub(x23, x3, Operand(1));
 
   __ Sub(w24, w0, Operand(0x1));
   __ Sub(w25, w1, Operand(0x111));
   __ Sub(w26, w1, Operand(0x1 << 12));
   __ Sub(w27, w3, Operand(1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x123, x10);
-  ASSERT_EQUAL_64(0x123111, x11);
-  ASSERT_EQUAL_64(0xabc000, x12);
-  ASSERT_EQUAL_64(0x0, x13);
+  CHECK_EQUAL_64(0x123, x10);
+  CHECK_EQUAL_64(0x123111, x11);
+  CHECK_EQUAL_64(0xabc000, x12);
+  CHECK_EQUAL_64(0x0, x13);
 
-  ASSERT_EQUAL_32(0x123, w14);
-  ASSERT_EQUAL_32(0x123111, w15);
-  ASSERT_EQUAL_32(0xabc000, w16);
-  ASSERT_EQUAL_32(0x0, w17);
+  CHECK_EQUAL_32(0x123, w14);
+  CHECK_EQUAL_32(0x123111, w15);
+  CHECK_EQUAL_32(0xabc000, w16);
+  CHECK_EQUAL_32(0x0, w17);
 
-  ASSERT_EQUAL_64(0xffffffffffffffffL, x20);
-  ASSERT_EQUAL_64(0x1000, x21);
-  ASSERT_EQUAL_64(0x111, x22);
-  ASSERT_EQUAL_64(0x7fffffffffffffffL, x23);
+  CHECK_EQUAL_64(0xffffffffffffffffL, x20);
+  CHECK_EQUAL_64(0x1000, x21);
+  CHECK_EQUAL_64(0x111, x22);
+  CHECK_EQUAL_64(0x7fffffffffffffffL, x23);
 
-  ASSERT_EQUAL_32(0xffffffff, w24);
-  ASSERT_EQUAL_32(0x1000, w25);
-  ASSERT_EQUAL_32(0x111, w26);
-  ASSERT_EQUAL_32(0xffffffff, w27);
+  CHECK_EQUAL_32(0xffffffff, w24);
+  CHECK_EQUAL_32(0x1000, w25);
+  CHECK_EQUAL_32(0x111, w26);
+  CHECK_EQUAL_32(0xffffffff, w27);
 
   TEARDOWN();
 }
 
 
 TEST(add_sub_wide_imm) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0x0);
   __ Mov(x1, 0x1);
 
   __ Add(x10, x0, Operand(0x1234567890abcdefUL));
   __ Add(x11, x1, Operand(0xffffffff));
 
   __ Add(w12, w0, Operand(0x12345678));
   __ Add(w13, w1, Operand(0xffffffff));
 
   __ Add(w18, w0, Operand(kWMinInt));
   __ Sub(w19, w0, Operand(kWMinInt));
 
   __ Sub(x20, x0, Operand(0x1234567890abcdefUL));
   __ Sub(w21, w0, Operand(0x12345678));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1234567890abcdefUL, x10);
-  ASSERT_EQUAL_64(0x100000000UL, x11);
+  CHECK_EQUAL_64(0x1234567890abcdefUL, x10);
+  CHECK_EQUAL_64(0x100000000UL, x11);
 
-  ASSERT_EQUAL_32(0x12345678, w12);
-  ASSERT_EQUAL_64(0x0, x13);
+  CHECK_EQUAL_32(0x12345678, w12);
+  CHECK_EQUAL_64(0x0, x13);
 
-  ASSERT_EQUAL_32(kWMinInt, w18);
-  ASSERT_EQUAL_32(kWMinInt, w19);
+  CHECK_EQUAL_32(kWMinInt, w18);
+  CHECK_EQUAL_32(kWMinInt, w19);
 
-  ASSERT_EQUAL_64(-0x1234567890abcdefUL, x20);
-  ASSERT_EQUAL_32(-0x12345678, w21);
+  CHECK_EQUAL_64(-0x1234567890abcdefUL, x20);
+  CHECK_EQUAL_32(-0x12345678, w21);
 
   TEARDOWN();
 }
 
 
 TEST(add_sub_shifted) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 16 matching lines @@
   __ Sub(x22, x3, Operand(x1, LSR, 8));
   __ Sub(x23, x3, Operand(x1, ASR, 8));
   __ Sub(x24, x3, Operand(x2, ASR, 8));
   __ Sub(w25, w3, Operand(w1, ASR, 8));
   __ Sub(w26, w3, Operand(w1, ROR, 8));
   __ Sub(x27, x3, Operand(x1, ROR, 8));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffffffffffffffL, x10);
-  ASSERT_EQUAL_64(0x23456789abcdef00L, x11);
-  ASSERT_EQUAL_64(0x000123456789abcdL, x12);
-  ASSERT_EQUAL_64(0x000123456789abcdL, x13);
-  ASSERT_EQUAL_64(0xfffedcba98765432L, x14);
-  ASSERT_EQUAL_64(0xff89abcd, x15);
-  ASSERT_EQUAL_64(0xef89abcc, x18);
-  ASSERT_EQUAL_64(0xef0123456789abccL, x19);
+  CHECK_EQUAL_64(0xffffffffffffffffL, x10);
+  CHECK_EQUAL_64(0x23456789abcdef00L, x11);
+  CHECK_EQUAL_64(0x000123456789abcdL, x12);
+  CHECK_EQUAL_64(0x000123456789abcdL, x13);
+  CHECK_EQUAL_64(0xfffedcba98765432L, x14);
+  CHECK_EQUAL_64(0xff89abcd, x15);
+  CHECK_EQUAL_64(0xef89abcc, x18);
+  CHECK_EQUAL_64(0xef0123456789abccL, x19);
 
-  ASSERT_EQUAL_64(0x0123456789abcdefL, x20);
-  ASSERT_EQUAL_64(0xdcba9876543210ffL, x21);
-  ASSERT_EQUAL_64(0xfffedcba98765432L, x22);
-  ASSERT_EQUAL_64(0xfffedcba98765432L, x23);
-  ASSERT_EQUAL_64(0x000123456789abcdL, x24);
-  ASSERT_EQUAL_64(0x00765432, x25);
-  ASSERT_EQUAL_64(0x10765432, x26);
-  ASSERT_EQUAL_64(0x10fedcba98765432L, x27);
+  CHECK_EQUAL_64(0x0123456789abcdefL, x20);
+  CHECK_EQUAL_64(0xdcba9876543210ffL, x21);
+  CHECK_EQUAL_64(0xfffedcba98765432L, x22);
+  CHECK_EQUAL_64(0xfffedcba98765432L, x23);
+  CHECK_EQUAL_64(0x000123456789abcdL, x24);
+  CHECK_EQUAL_64(0x00765432, x25);
+  CHECK_EQUAL_64(0x10765432, x26);
+  CHECK_EQUAL_64(0x10fedcba98765432L, x27);
 
   TEARDOWN();
 }
 
 
 TEST(add_sub_extended) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 25 matching lines @@
   __ Add(w27, w2, Operand(w1, SXTW, 3));
 
   __ Add(w28, w0, Operand(w1, SXTW, 3));
   __ Add(x29, x0, Operand(w1, SXTW, 3));
 
   __ Sub(x30, x0, Operand(w3, SXTB, 1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xefL, x10);
-  ASSERT_EQUAL_64(0x1deL, x11);
-  ASSERT_EQUAL_64(0x337bcL, x12);
-  ASSERT_EQUAL_64(0x89abcdef0L, x13);
+  CHECK_EQUAL_64(0xefL, x10);
+  CHECK_EQUAL_64(0x1deL, x11);
+  CHECK_EQUAL_64(0x337bcL, x12);
+  CHECK_EQUAL_64(0x89abcdef0L, x13);
 
-  ASSERT_EQUAL_64(0xffffffffffffffefL, x14);
-  ASSERT_EQUAL_64(0xffffffffffffffdeL, x15);
-  ASSERT_EQUAL_64(0xffffffffffff37bcL, x16);
-  ASSERT_EQUAL_64(0xfffffffc4d5e6f78L, x17);
-  ASSERT_EQUAL_64(0x10L, x18);
-  ASSERT_EQUAL_64(0x20L, x19);
-  ASSERT_EQUAL_64(0xc840L, x20);
-  ASSERT_EQUAL_64(0x3b2a19080L, x21);
+  CHECK_EQUAL_64(0xffffffffffffffefL, x14);
+  CHECK_EQUAL_64(0xffffffffffffffdeL, x15);
+  CHECK_EQUAL_64(0xffffffffffff37bcL, x16);
+  CHECK_EQUAL_64(0xfffffffc4d5e6f78L, x17);
+  CHECK_EQUAL_64(0x10L, x18);
+  CHECK_EQUAL_64(0x20L, x19);
+  CHECK_EQUAL_64(0xc840L, x20);
+  CHECK_EQUAL_64(0x3b2a19080L, x21);
 
-  ASSERT_EQUAL_64(0x0123456789abce0fL, x22);
-  ASSERT_EQUAL_64(0x0123456789abcdcfL, x23);
+  CHECK_EQUAL_64(0x0123456789abce0fL, x22);
+  CHECK_EQUAL_64(0x0123456789abcdcfL, x23);
 
-  ASSERT_EQUAL_32(0x89abce2f, w24);
-  ASSERT_EQUAL_32(0xffffffef, w25);
-  ASSERT_EQUAL_32(0xffffffde, w26);
-  ASSERT_EQUAL_32(0xc3b2a188, w27);
+  CHECK_EQUAL_32(0x89abce2f, w24);
+  CHECK_EQUAL_32(0xffffffef, w25);
+  CHECK_EQUAL_32(0xffffffde, w26);
+  CHECK_EQUAL_32(0xc3b2a188, w27);
 
-  ASSERT_EQUAL_32(0x4d5e6f78, w28);
-  ASSERT_EQUAL_64(0xfffffffc4d5e6f78L, x29);
+  CHECK_EQUAL_32(0x4d5e6f78, w28);
+  CHECK_EQUAL_64(0xfffffffc4d5e6f78L, x29);
 
-  ASSERT_EQUAL_64(256, x30);
+  CHECK_EQUAL_64(256, x30);
 
   TEARDOWN();
 }
 
 
 TEST(add_sub_negative) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 13 matching lines @@
 
   __ Add(w19, w3, -0x344);
   __ Add(w20, w4, -2000);
 
   __ Sub(w21, w3, -0xbc);
   __ Sub(w22, w4, -2000);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(-42, x10);
-  ASSERT_EQUAL_64(4000, x11);
-  ASSERT_EQUAL_64(0x1122334455667700, x12);
+  CHECK_EQUAL_64(-42, x10);
+  CHECK_EQUAL_64(4000, x11);
+  CHECK_EQUAL_64(0x1122334455667700, x12);
 
-  ASSERT_EQUAL_64(600, x13);
-  ASSERT_EQUAL_64(5000, x14);
-  ASSERT_EQUAL_64(0x1122334455667cdd, x15);
+  CHECK_EQUAL_64(600, x13);
+  CHECK_EQUAL_64(5000, x14);
+  CHECK_EQUAL_64(0x1122334455667cdd, x15);
 
-  ASSERT_EQUAL_32(0x11223000, w19);
-  ASSERT_EQUAL_32(398000, w20);
+  CHECK_EQUAL_32(0x11223000, w19);
+  CHECK_EQUAL_32(398000, w20);
 
-  ASSERT_EQUAL_32(0x11223400, w21);
-  ASSERT_EQUAL_32(402000, w22);
+  CHECK_EQUAL_32(0x11223400, w21);
+  CHECK_EQUAL_32(402000, w22);
 
   TEARDOWN();
 }
 
 
 TEST(add_sub_zero) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 15 matching lines @@
 
   Label blob3;
   __ Bind(&blob3);
   __ Sub(w3, w3, wzr);
   CHECK_NE(0, __ SizeOfCodeGeneratedSince(&blob3));
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0, x0);
-  ASSERT_EQUAL_64(0, x1);
-  ASSERT_EQUAL_64(0, x2);
+  CHECK_EQUAL_64(0, x0);
+  CHECK_EQUAL_64(0, x1);
+  CHECK_EQUAL_64(0, x2);
 
   TEARDOWN();
 }
 
 
 TEST(claim_drop_zero) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 45 matching lines @@
   __ Neg(w9, Operand(w0, UXTB));
   __ Neg(x10, Operand(x0, SXTB, 1));
   __ Neg(w11, Operand(w0, UXTH, 2));
   __ Neg(x12, Operand(x0, SXTH, 3));
   __ Neg(w13, Operand(w0, UXTW, 4));
   __ Neg(x14, Operand(x0, SXTW, 4));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xfffffffffffffeddUL, x1);
-  ASSERT_EQUAL_64(0xfffffedd, x2);
-  ASSERT_EQUAL_64(0x1db97530eca86422UL, x3);
-  ASSERT_EQUAL_64(0xd950c844, x4);
-  ASSERT_EQUAL_64(0xe1db97530eca8643UL, x5);
-  ASSERT_EQUAL_64(0xf7654322, x6);
-  ASSERT_EQUAL_64(0x0076e5d4c3b2a191UL, x7);
-  ASSERT_EQUAL_64(0x01d950c9, x8);
-  ASSERT_EQUAL_64(0xffffff11, x9);
-  ASSERT_EQUAL_64(0x0000000000000022UL, x10);
-  ASSERT_EQUAL_64(0xfffcc844, x11);
-  ASSERT_EQUAL_64(0x0000000000019088UL, x12);
-  ASSERT_EQUAL_64(0x65432110, x13);
-  ASSERT_EQUAL_64(0x0000000765432110UL, x14);
+  CHECK_EQUAL_64(0xfffffffffffffeddUL, x1);
+  CHECK_EQUAL_64(0xfffffedd, x2);
+  CHECK_EQUAL_64(0x1db97530eca86422UL, x3);
+  CHECK_EQUAL_64(0xd950c844, x4);
+  CHECK_EQUAL_64(0xe1db97530eca8643UL, x5);
+  CHECK_EQUAL_64(0xf7654322, x6);
+  CHECK_EQUAL_64(0x0076e5d4c3b2a191UL, x7);
+  CHECK_EQUAL_64(0x01d950c9, x8);
+  CHECK_EQUAL_64(0xffffff11, x9);
+  CHECK_EQUAL_64(0x0000000000000022UL, x10);
+  CHECK_EQUAL_64(0xfffcc844, x11);
+  CHECK_EQUAL_64(0x0000000000019088UL, x12);
+  CHECK_EQUAL_64(0x65432110, x13);
+  CHECK_EQUAL_64(0x0000000765432110UL, x14);
 
   TEARDOWN();
 }
 
 
 TEST(adc_sbc_shift) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 29 matching lines @@
 
   __ Adc(w23, w2, Operand(w3));
   __ Adc(w24, w0, Operand(w1, LSL, 30));
   __ Sbc(w25, w4, Operand(w3, LSR, 4));
   __ Adc(w26, w2, Operand(w3, ASR, 4));
   __ Adc(w27, w2, Operand(w3, ROR, 8));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xffffffffffffffffL, x5);
-  ASSERT_EQUAL_64(1L << 60, x6);
-  ASSERT_EQUAL_64(0xf0123456789abcddL, x7);
-  ASSERT_EQUAL_64(0x0111111111111110L, x8);
-  ASSERT_EQUAL_64(0x1222222222222221L, x9);
+  CHECK_EQUAL_64(0xffffffffffffffffL, x5);
+  CHECK_EQUAL_64(1L << 60, x6);
+  CHECK_EQUAL_64(0xf0123456789abcddL, x7);
+  CHECK_EQUAL_64(0x0111111111111110L, x8);
+  CHECK_EQUAL_64(0x1222222222222221L, x9);
 
-  ASSERT_EQUAL_32(0xffffffff, w10);
-  ASSERT_EQUAL_32(1 << 30, w11);
-  ASSERT_EQUAL_32(0xf89abcdd, w12);
-  ASSERT_EQUAL_32(0x91111110, w13);
-  ASSERT_EQUAL_32(0x9a222221, w14);
+  CHECK_EQUAL_32(0xffffffff, w10);
+  CHECK_EQUAL_32(1 << 30, w11);
+  CHECK_EQUAL_32(0xf89abcdd, w12);
+  CHECK_EQUAL_32(0x91111110, w13);
+  CHECK_EQUAL_32(0x9a222221, w14);
 
-  ASSERT_EQUAL_64(0xffffffffffffffffL + 1, x18);
-  ASSERT_EQUAL_64((1L << 60) + 1, x19);
-  ASSERT_EQUAL_64(0xf0123456789abcddL + 1, x20);
-  ASSERT_EQUAL_64(0x0111111111111110L + 1, x21);
-  ASSERT_EQUAL_64(0x1222222222222221L + 1, x22);
+  CHECK_EQUAL_64(0xffffffffffffffffL + 1, x18);
+  CHECK_EQUAL_64((1L << 60) + 1, x19);
+  CHECK_EQUAL_64(0xf0123456789abcddL + 1, x20);
+  CHECK_EQUAL_64(0x0111111111111110L + 1, x21);
+  CHECK_EQUAL_64(0x1222222222222221L + 1, x22);
 
-  ASSERT_EQUAL_32(0xffffffff + 1, w23);
-  ASSERT_EQUAL_32((1 << 30) + 1, w24);
-  ASSERT_EQUAL_32(0xf89abcdd + 1, w25);
-  ASSERT_EQUAL_32(0x91111110 + 1, w26);
-  ASSERT_EQUAL_32(0x9a222221 + 1, w27);
+  CHECK_EQUAL_32(0xffffffff + 1, w23);
+  CHECK_EQUAL_32((1 << 30) + 1, w24);
+  CHECK_EQUAL_32(0xf89abcdd + 1, w25);
+  CHECK_EQUAL_32(0x91111110 + 1, w26);
+  CHECK_EQUAL_32(0x9a222221 + 1, w27);
 
   // Check that adc correctly sets the condition flags.
   START();
   __ Mov(x0, 1);
   __ Mov(x1, 0xffffffffffffffffL);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Adcs(x10, x0, Operand(x1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZCFlag);
-  ASSERT_EQUAL_64(0, x10);
+  CHECK_EQUAL_NZCV(ZCFlag);
+  CHECK_EQUAL_64(0, x10);
 
   START();
   __ Mov(x0, 1);
   __ Mov(x1, 0x8000000000000000L);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Adcs(x10, x0, Operand(x1, ASR, 63));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZCFlag);
-  ASSERT_EQUAL_64(0, x10);
+  CHECK_EQUAL_NZCV(ZCFlag);
+  CHECK_EQUAL_64(0, x10);
 
   START();
   __ Mov(x0, 0x10);
   __ Mov(x1, 0x07ffffffffffffffL);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Adcs(x10, x0, Operand(x1, LSL, 4));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NVFlag);
-  ASSERT_EQUAL_64(0x8000000000000000L, x10);
+  CHECK_EQUAL_NZCV(NVFlag);
+  CHECK_EQUAL_64(0x8000000000000000L, x10);
 
   // Check that sbc correctly sets the condition flags.
   START();
   __ Mov(x0, 0);
   __ Mov(x1, 0xffffffffffffffffL);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Sbcs(x10, x0, Operand(x1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZFlag);
-  ASSERT_EQUAL_64(0, x10);
+  CHECK_EQUAL_NZCV(ZFlag);
+  CHECK_EQUAL_64(0, x10);
 
   START();
   __ Mov(x0, 1);
   __ Mov(x1, 0xffffffffffffffffL);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Sbcs(x10, x0, Operand(x1, LSR, 1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0x8000000000000001L, x10);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0x8000000000000001L, x10);
 
   START();
   __ Mov(x0, 0);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Sbcs(x10, x0, Operand(0xffffffffffffffffL));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZFlag);
-  ASSERT_EQUAL_64(0, x10);
+  CHECK_EQUAL_NZCV(ZFlag);
+  CHECK_EQUAL_64(0, x10);
 
   START()
   __ Mov(w0, 0x7fffffff);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Ngcs(w10, w0);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0x80000000, x10);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0x80000000, x10);
 
   START();
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Ngcs(x10, 0x7fffffffffffffffL);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0x8000000000000000L, x10);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0x8000000000000000L, x10);
 
   START()
   __ Mov(x0, 0);
   // Set the C flag.
   __ Cmp(x0, Operand(x0));
   __ Sbcs(x10, x0, Operand(1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0xffffffffffffffffL, x10);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0xffffffffffffffffL, x10);
 
   START()
   __ Mov(x0, 0);
   // Set the C flag.
   __ Cmp(x0, Operand(x0));
   __ Ngcs(x10, 0x7fffffffffffffffL);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
-  ASSERT_EQUAL_64(0x8000000000000001L, x10);
+  CHECK_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_64(0x8000000000000001L, x10);
 
   TEARDOWN();
 }
 
 
 TEST(adc_sbc_extend) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 21 matching lines @@
   __ Sbc(x22, x1, Operand(w2, UXTW, 4));
   __ Adc(x23, x1, Operand(x2, UXTX, 4));
 
   __ Adc(w24, w1, Operand(w2, UXTB, 1));
   __ Adc(w25, w1, Operand(w2, SXTH, 2));
   __ Adc(w26, w1, Operand(w2, UXTW, 4));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1df, x10);
-  ASSERT_EQUAL_64(0xffffffffffff37bdL, x11);
-  ASSERT_EQUAL_64(0xfffffff765432110L, x12);
-  ASSERT_EQUAL_64(0x123456789abcdef1L, x13);
+  CHECK_EQUAL_64(0x1df, x10);
+  CHECK_EQUAL_64(0xffffffffffff37bdL, x11);
+  CHECK_EQUAL_64(0xfffffff765432110L, x12);
+  CHECK_EQUAL_64(0x123456789abcdef1L, x13);
 
-  ASSERT_EQUAL_32(0x1df, w14);
-  ASSERT_EQUAL_32(0xffff37bd, w15);
-  ASSERT_EQUAL_32(0x9abcdef1, w9);
+  CHECK_EQUAL_32(0x1df, w14);
+  CHECK_EQUAL_32(0xffff37bd, w15);
+  CHECK_EQUAL_32(0x9abcdef1, w9);
 
-  ASSERT_EQUAL_64(0x1df + 1, x20);
-  ASSERT_EQUAL_64(0xffffffffffff37bdL + 1, x21);
-  ASSERT_EQUAL_64(0xfffffff765432110L + 1, x22);
-  ASSERT_EQUAL_64(0x123456789abcdef1L + 1, x23);
+  CHECK_EQUAL_64(0x1df + 1, x20);
+  CHECK_EQUAL_64(0xffffffffffff37bdL + 1, x21);
+  CHECK_EQUAL_64(0xfffffff765432110L + 1, x22);
+  CHECK_EQUAL_64(0x123456789abcdef1L + 1, x23);
 
-  ASSERT_EQUAL_32(0x1df + 1, w24);
-  ASSERT_EQUAL_32(0xffff37bd + 1, w25);
-  ASSERT_EQUAL_32(0x9abcdef1 + 1, w26);
+  CHECK_EQUAL_32(0x1df + 1, w24);
+  CHECK_EQUAL_32(0xffff37bd + 1, w25);
+  CHECK_EQUAL_32(0x9abcdef1 + 1, w26);
 
   // Check that adc correctly sets the condition flags.
   START();
   __ Mov(x0, 0xff);
   __ Mov(x1, 0xffffffffffffffffL);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Adcs(x10, x0, Operand(x1, SXTX, 1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(CFlag);
+  CHECK_EQUAL_NZCV(CFlag);
 
   START();
   __ Mov(x0, 0x7fffffffffffffffL);
   __ Mov(x1, 1);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Adcs(x10, x0, Operand(x1, UXTB, 2));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NVFlag);
+  CHECK_EQUAL_NZCV(NVFlag);
 
   START();
   __ Mov(x0, 0x7fffffffffffffffL);
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Adcs(x10, x0, Operand(1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NVFlag);
+  CHECK_EQUAL_NZCV(NVFlag);
 
   TEARDOWN();
 }
 
 
 TEST(adc_sbc_wide_imm) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 15 matching lines @@
   __ Adc(x18, x0, Operand(0x1234567890abcdefUL));
   __ Adc(w19, w0, Operand(0xffffffff));
   __ Sbc(x20, x0, Operand(0x1234567890abcdefUL));
   __ Sbc(w21, w0, Operand(0xffffffff));
   __ Ngc(x22, Operand(0xffffffff00000000UL));
   __ Ngc(w23, Operand(0xffff0000));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1234567890abcdefUL, x7);
-  ASSERT_EQUAL_64(0xffffffff, x8);
-  ASSERT_EQUAL_64(0xedcba9876f543210UL, x9);
-  ASSERT_EQUAL_64(0, x10);
-  ASSERT_EQUAL_64(0xffffffff, x11);
-  ASSERT_EQUAL_64(0xffff, x12);
+  CHECK_EQUAL_64(0x1234567890abcdefUL, x7);
+  CHECK_EQUAL_64(0xffffffff, x8);
+  CHECK_EQUAL_64(0xedcba9876f543210UL, x9);
+  CHECK_EQUAL_64(0, x10);
+  CHECK_EQUAL_64(0xffffffff, x11);
+  CHECK_EQUAL_64(0xffff, x12);
 
-  ASSERT_EQUAL_64(0x1234567890abcdefUL + 1, x18);
-  ASSERT_EQUAL_64(0, x19);
-  ASSERT_EQUAL_64(0xedcba9876f543211UL, x20);
-  ASSERT_EQUAL_64(1, x21);
-  ASSERT_EQUAL_64(0x100000000UL, x22);
-  ASSERT_EQUAL_64(0x10000, x23);
+  CHECK_EQUAL_64(0x1234567890abcdefUL + 1, x18);
+  CHECK_EQUAL_64(0, x19);
+  CHECK_EQUAL_64(0xedcba9876f543211UL, x20);
+  CHECK_EQUAL_64(1, x21);
+  CHECK_EQUAL_64(0x100000000UL, x22);
+  CHECK_EQUAL_64(0x10000, x23);
 
   TEARDOWN();
 }
 
 
 TEST(flags) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x0, 0);
   __ Mov(x1, 0x1111111111111111L);
   __ Neg(x10, Operand(x0));
   __ Neg(x11, Operand(x1));
   __ Neg(w12, Operand(w1));
   // Clear the C flag.
   __ Adds(x0, x0, Operand(0));
   __ Ngc(x13, Operand(x0));
   // Set the C flag.
   __ Cmp(x0, Operand(x0));
   __ Ngc(w14, Operand(w0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0, x10);
-  ASSERT_EQUAL_64(-0x1111111111111111L, x11);
-  ASSERT_EQUAL_32(-0x11111111, w12);
-  ASSERT_EQUAL_64(-1L, x13);
-  ASSERT_EQUAL_32(0, w14);
+  CHECK_EQUAL_64(0, x10);
+  CHECK_EQUAL_64(-0x1111111111111111L, x11);
+  CHECK_EQUAL_32(-0x11111111, w12);
+  CHECK_EQUAL_64(-1L, x13);
+  CHECK_EQUAL_32(0, w14);
 
   START();
   __ Mov(x0, 0);
   __ Cmp(x0, Operand(x0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZCFlag);
+  CHECK_EQUAL_NZCV(ZCFlag);
 
   START();
   __ Mov(w0, 0);
   __ Cmp(w0, Operand(w0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZCFlag);
+  CHECK_EQUAL_NZCV(ZCFlag);
 
   START();
   __ Mov(x0, 0);
   __ Mov(x1, 0x1111111111111111L);
   __ Cmp(x0, Operand(x1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_NZCV(NFlag);
 
   START();
   __ Mov(w0, 0);
   __ Mov(w1, 0x11111111);
   __ Cmp(w0, Operand(w1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_NZCV(NFlag);
 
   START();
   __ Mov(x1, 0x1111111111111111L);
   __ Cmp(x1, Operand(0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(CFlag);
+  CHECK_EQUAL_NZCV(CFlag);
 
   START();
   __ Mov(w1, 0x11111111);
   __ Cmp(w1, Operand(0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(CFlag);
+  CHECK_EQUAL_NZCV(CFlag);
 
   START();
   __ Mov(x0, 1);
   __ Mov(x1, 0x7fffffffffffffffL);
   __ Cmn(x1, Operand(x0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NVFlag);
+  CHECK_EQUAL_NZCV(NVFlag);
 
   START();
   __ Mov(w0, 1);
   __ Mov(w1, 0x7fffffff);
   __ Cmn(w1, Operand(w0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NVFlag);
+  CHECK_EQUAL_NZCV(NVFlag);
 
   START();
   __ Mov(x0, 1);
   __ Mov(x1, 0xffffffffffffffffL);
   __ Cmn(x1, Operand(x0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZCFlag);
+  CHECK_EQUAL_NZCV(ZCFlag);
 
   START();
   __ Mov(w0, 1);
   __ Mov(w1, 0xffffffff);
   __ Cmn(w1, Operand(w0));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZCFlag);
+  CHECK_EQUAL_NZCV(ZCFlag);
 
   START();
   __ Mov(w0, 0);
   __ Mov(w1, 1);
   // Clear the C flag.
   __ Adds(w0, w0, Operand(0));
   __ Ngcs(w0, Operand(w1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(NFlag);
+  CHECK_EQUAL_NZCV(NFlag);
 
   START();
   __ Mov(w0, 0);
   __ Mov(w1, 0);
   // Set the C flag.
   __ Cmp(w0, Operand(w0));
   __ Ngcs(w0, Operand(w1));
   END();
 
   RUN();
 
-  ASSERT_EQUAL_NZCV(ZCFlag);
+  CHECK_EQUAL_NZCV(ZCFlag);
 
   TEARDOWN();
 }
 
 
 TEST(cmp_shift) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 28 matching lines @@
 
   __ Cmp(w27, Operand(w22, ROR, 28));
   __ Mrs(x6, NZCV);
 
   __ Cmp(x20, Operand(x21, ROR, 31));
   __ Mrs(x7, NZCV);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(ZCFlag, w0);
-  ASSERT_EQUAL_32(ZCFlag, w1);
-  ASSERT_EQUAL_32(ZCFlag, w2);
-  ASSERT_EQUAL_32(ZCFlag, w3);
-  ASSERT_EQUAL_32(ZCFlag, w4);
-  ASSERT_EQUAL_32(ZCFlag, w5);
-  ASSERT_EQUAL_32(ZCFlag, w6);
-  ASSERT_EQUAL_32(ZCFlag, w7);
+  CHECK_EQUAL_32(ZCFlag, w0);
+  CHECK_EQUAL_32(ZCFlag, w1);
+  CHECK_EQUAL_32(ZCFlag, w2);
+  CHECK_EQUAL_32(ZCFlag, w3);
+  CHECK_EQUAL_32(ZCFlag, w4);
+  CHECK_EQUAL_32(ZCFlag, w5);
+  CHECK_EQUAL_32(ZCFlag, w6);
+  CHECK_EQUAL_32(ZCFlag, w7);
 
   TEARDOWN();
 }
 
 
 TEST(cmp_extend) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 25 matching lines @@
 
   __ Cmp(x22, Operand(x26, UXTW));
   __ Mrs(x6, NZCV);
 
   __ Cmp(x24, Operand(x26, SXTW, 1));
   __ Mrs(x7, NZCV);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(ZCFlag, w0);
-  ASSERT_EQUAL_32(ZCFlag, w1);
-  ASSERT_EQUAL_32(ZCFlag, w2);
-  ASSERT_EQUAL_32(NCFlag, w3);
-  ASSERT_EQUAL_32(NCFlag, w4);
-  ASSERT_EQUAL_32(ZCFlag, w5);
-  ASSERT_EQUAL_32(NCFlag, w6);
-  ASSERT_EQUAL_32(ZCFlag, w7);
+  CHECK_EQUAL_32(ZCFlag, w0);
+  CHECK_EQUAL_32(ZCFlag, w1);
+  CHECK_EQUAL_32(ZCFlag, w2);
+  CHECK_EQUAL_32(NCFlag, w3);
+  CHECK_EQUAL_32(NCFlag, w4);
+  CHECK_EQUAL_32(ZCFlag, w5);
+  CHECK_EQUAL_32(NCFlag, w6);
+  CHECK_EQUAL_32(ZCFlag, w7);
 
   TEARDOWN();
 }
 
 
 TEST(ccmp) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 18 matching lines @@
   __ ccmp(x16, x16, NZCVFlag, al);
   __ Mrs(x4, NZCV);
 
   __ ccmp(x16, x16, NZCVFlag, nv);
   __ Mrs(x5, NZCV);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(NFlag, w0);
-  ASSERT_EQUAL_32(NCFlag, w1);
-  ASSERT_EQUAL_32(NoFlag, w2);
-  ASSERT_EQUAL_32(NZCVFlag, w3);
-  ASSERT_EQUAL_32(ZCFlag, w4);
-  ASSERT_EQUAL_32(ZCFlag, w5);
+  CHECK_EQUAL_32(NFlag, w0);
+  CHECK_EQUAL_32(NCFlag, w1);
+  CHECK_EQUAL_32(NoFlag, w2);
+  CHECK_EQUAL_32(NZCVFlag, w3);
+  CHECK_EQUAL_32(ZCFlag, w4);
+  CHECK_EQUAL_32(ZCFlag, w5);
 
   TEARDOWN();
 }
 
 
 TEST(ccmp_wide_imm) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(w20, 0);
 
   __ Cmp(w20, Operand(w20));
   __ Ccmp(w20, Operand(0x12345678), NZCVFlag, eq);
   __ Mrs(x0, NZCV);
 
   __ Cmp(w20, Operand(w20));
   __ Ccmp(x20, Operand(0xffffffffffffffffUL), NZCVFlag, eq);
   __ Mrs(x1, NZCV);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(NFlag, w0);
-  ASSERT_EQUAL_32(NoFlag, w1);
+  CHECK_EQUAL_32(NFlag, w0);
+  CHECK_EQUAL_32(NoFlag, w1);
 
   TEARDOWN();
 }
 
 
 TEST(ccmp_shift_extend) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 19 matching lines @@
   __ Ccmp(x24, Operand(x23, UXTB, 1), NZCVFlag, eq);
   __ Mrs(x3, NZCV);
 
   __ Cmp(w20, Operand(w20));
   __ Ccmp(x24, Operand(x23, UXTB, 1), NZCVFlag, ne);
   __ Mrs(x4, NZCV);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(ZCFlag, w0);
-  ASSERT_EQUAL_32(ZCFlag, w1);
-  ASSERT_EQUAL_32(ZCFlag, w2);
-  ASSERT_EQUAL_32(NCFlag, w3);
-  ASSERT_EQUAL_32(NZCVFlag, w4);
+  CHECK_EQUAL_32(ZCFlag, w0);
+  CHECK_EQUAL_32(ZCFlag, w1);
+  CHECK_EQUAL_32(ZCFlag, w2);
+  CHECK_EQUAL_32(NCFlag, w3);
+  CHECK_EQUAL_32(NZCVFlag, w4);
 
   TEARDOWN();
 }
 
 
 TEST(csel) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 29 matching lines @@
 
   __ CzeroX(x24, ne);
   __ CzeroX(x25, eq);
 
   __ CmovX(x26, x25, ne);
   __ CmovX(x27, x25, eq);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x0000000f, x0);
-  ASSERT_EQUAL_64(0x0000001f, x1);
-  ASSERT_EQUAL_64(0x00000020, x2);
-  ASSERT_EQUAL_64(0x0000000f, x3);
-  ASSERT_EQUAL_64(0xffffffe0ffffffe0UL, x4);
-  ASSERT_EQUAL_64(0x0000000f0000000fUL, x5);
-  ASSERT_EQUAL_64(0xffffffe0ffffffe1UL, x6);
-  ASSERT_EQUAL_64(0x0000000f0000000fUL, x7);
-  ASSERT_EQUAL_64(0x00000001, x8);
-  ASSERT_EQUAL_64(0xffffffff, x9);
-  ASSERT_EQUAL_64(0x0000001f00000020UL, x10);
-  ASSERT_EQUAL_64(0xfffffff0fffffff0UL, x11);
-  ASSERT_EQUAL_64(0xfffffff0fffffff1UL, x12);
-  ASSERT_EQUAL_64(0x0000000f, x13);
-  ASSERT_EQUAL_64(0x0000000f0000000fUL, x14);
-  ASSERT_EQUAL_64(0x0000000f, x15);
-  ASSERT_EQUAL_64(0x0000000f0000000fUL, x18);
-  ASSERT_EQUAL_64(0, x24);
-  ASSERT_EQUAL_64(0x0000001f0000001fUL, x25);
-  ASSERT_EQUAL_64(0x0000001f0000001fUL, x26);
-  ASSERT_EQUAL_64(0, x27);
+  CHECK_EQUAL_64(0x0000000f, x0);
+  CHECK_EQUAL_64(0x0000001f, x1);
+  CHECK_EQUAL_64(0x00000020, x2);
+  CHECK_EQUAL_64(0x0000000f, x3);
+  CHECK_EQUAL_64(0xffffffe0ffffffe0UL, x4);
+  CHECK_EQUAL_64(0x0000000f0000000fUL, x5);
+  CHECK_EQUAL_64(0xffffffe0ffffffe1UL, x6);
+  CHECK_EQUAL_64(0x0000000f0000000fUL, x7);
+  CHECK_EQUAL_64(0x00000001, x8);
+  CHECK_EQUAL_64(0xffffffff, x9);
+  CHECK_EQUAL_64(0x0000001f00000020UL, x10);
+  CHECK_EQUAL_64(0xfffffff0fffffff0UL, x11);
+  CHECK_EQUAL_64(0xfffffff0fffffff1UL, x12);
+  CHECK_EQUAL_64(0x0000000f, x13);
+  CHECK_EQUAL_64(0x0000000f0000000fUL, x14);
+  CHECK_EQUAL_64(0x0000000f, x15);
+  CHECK_EQUAL_64(0x0000000f0000000fUL, x18);
+  CHECK_EQUAL_64(0, x24);
+  CHECK_EQUAL_64(0x0000001f0000001fUL, x25);
+  CHECK_EQUAL_64(0x0000001f0000001fUL, x26);
+  CHECK_EQUAL_64(0, x27);
 
   TEARDOWN();
 }
 
 
 TEST(csel_imm) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 17 matching lines @@
   __ Csel(x11, x20, 1, ne);
   __ Csel(x12, x20, 2, ne);
   __ Csel(x13, x20, Operand(x20, ASR, 63), ne);
   __ Csel(x14, x20, Operand(x20, ROR, 1), ne);
   __ Csel(x15, x20, 3, eq);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(-2, w0);
-  ASSERT_EQUAL_32(-1, w1);
-  ASSERT_EQUAL_32(0, w2);
-  ASSERT_EQUAL_32(1, w3);
-  ASSERT_EQUAL_32(2, w4);
-  ASSERT_EQUAL_32(-1, w5);
-  ASSERT_EQUAL_32(0x40000000, w6);
-  ASSERT_EQUAL_32(0x80000000, w7);
+  CHECK_EQUAL_32(-2, w0);
+  CHECK_EQUAL_32(-1, w1);
+  CHECK_EQUAL_32(0, w2);
+  CHECK_EQUAL_32(1, w3);
+  CHECK_EQUAL_32(2, w4);
+  CHECK_EQUAL_32(-1, w5);
+  CHECK_EQUAL_32(0x40000000, w6);
+  CHECK_EQUAL_32(0x80000000, w7);
 
-  ASSERT_EQUAL_64(-2, x8);
-  ASSERT_EQUAL_64(-1, x9);
-  ASSERT_EQUAL_64(0, x10);
-  ASSERT_EQUAL_64(1, x11);
-  ASSERT_EQUAL_64(2, x12);
-  ASSERT_EQUAL_64(-1, x13);
-  ASSERT_EQUAL_64(0x4000000000000000UL, x14);
-  ASSERT_EQUAL_64(0x8000000000000000UL, x15);
+  CHECK_EQUAL_64(-2, x8);
+  CHECK_EQUAL_64(-1, x9);
+  CHECK_EQUAL_64(0, x10);
+  CHECK_EQUAL_64(1, x11);
+  CHECK_EQUAL_64(2, x12);
+  CHECK_EQUAL_64(-1, x13);
+  CHECK_EQUAL_64(0x4000000000000000UL, x14);
+  CHECK_EQUAL_64(0x8000000000000000UL, x15);
 
   TEARDOWN();
 }
 
 
 TEST(lslv) {
   INIT_V8();
   SETUP();
 
   uint64_t value = 0x0123456789abcdefUL;
@@ skipping 20 matching lines @@
   __ Lsl(w22, w0, w1);
   __ Lsl(w23, w0, w2);
   __ Lsl(w24, w0, w3);
   __ Lsl(w25, w0, w4);
   __ Lsl(w26, w0, w5);
   __ Lsl(w27, w0, w6);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(value, x0);
-  ASSERT_EQUAL_64(value << (shift[0] & 63), x16);
-  ASSERT_EQUAL_64(value << (shift[1] & 63), x17);
-  ASSERT_EQUAL_64(value << (shift[2] & 63), x18);
-  ASSERT_EQUAL_64(value << (shift[3] & 63), x19);
-  ASSERT_EQUAL_64(value << (shift[4] & 63), x20);
-  ASSERT_EQUAL_64(value << (shift[5] & 63), x21);
-  ASSERT_EQUAL_32(value << (shift[0] & 31), w22);
-  ASSERT_EQUAL_32(value << (shift[1] & 31), w23);
-  ASSERT_EQUAL_32(value << (shift[2] & 31), w24);
-  ASSERT_EQUAL_32(value << (shift[3] & 31), w25);
-  ASSERT_EQUAL_32(value << (shift[4] & 31), w26);
-  ASSERT_EQUAL_32(value << (shift[5] & 31), w27);
+  CHECK_EQUAL_64(value, x0);
+  CHECK_EQUAL_64(value << (shift[0] & 63), x16);
+  CHECK_EQUAL_64(value << (shift[1] & 63), x17);
+  CHECK_EQUAL_64(value << (shift[2] & 63), x18);
+  CHECK_EQUAL_64(value << (shift[3] & 63), x19);
+  CHECK_EQUAL_64(value << (shift[4] & 63), x20);
+  CHECK_EQUAL_64(value << (shift[5] & 63), x21);
+  CHECK_EQUAL_32(value << (shift[0] & 31), w22);
+  CHECK_EQUAL_32(value << (shift[1] & 31), w23);
+  CHECK_EQUAL_32(value << (shift[2] & 31), w24);
+  CHECK_EQUAL_32(value << (shift[3] & 31), w25);
+  CHECK_EQUAL_32(value << (shift[4] & 31), w26);
+  CHECK_EQUAL_32(value << (shift[5] & 31), w27);
 
   TEARDOWN();
 }
 
 
 TEST(lsrv) {
   INIT_V8();
   SETUP();
 
   uint64_t value = 0x0123456789abcdefUL;
@@ skipping 20 matching lines @@
   __ Lsr(w22, w0, w1);
   __ Lsr(w23, w0, w2);
   __ Lsr(w24, w0, w3);
   __ Lsr(w25, w0, w4);
   __ Lsr(w26, w0, w5);
   __ Lsr(w27, w0, w6);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(value, x0);
-  ASSERT_EQUAL_64(value >> (shift[0] & 63), x16);
-  ASSERT_EQUAL_64(value >> (shift[1] & 63), x17);
-  ASSERT_EQUAL_64(value >> (shift[2] & 63), x18);
-  ASSERT_EQUAL_64(value >> (shift[3] & 63), x19);
-  ASSERT_EQUAL_64(value >> (shift[4] & 63), x20);
-  ASSERT_EQUAL_64(value >> (shift[5] & 63), x21);
+  CHECK_EQUAL_64(value, x0);
+  CHECK_EQUAL_64(value >> (shift[0] & 63), x16);
+  CHECK_EQUAL_64(value >> (shift[1] & 63), x17);
+  CHECK_EQUAL_64(value >> (shift[2] & 63), x18);
+  CHECK_EQUAL_64(value >> (shift[3] & 63), x19);
+  CHECK_EQUAL_64(value >> (shift[4] & 63), x20);
+  CHECK_EQUAL_64(value >> (shift[5] & 63), x21);
 
   value &= 0xffffffffUL;
-  ASSERT_EQUAL_32(value >> (shift[0] & 31), w22);
-  ASSERT_EQUAL_32(value >> (shift[1] & 31), w23);
-  ASSERT_EQUAL_32(value >> (shift[2] & 31), w24);
-  ASSERT_EQUAL_32(value >> (shift[3] & 31), w25);
-  ASSERT_EQUAL_32(value >> (shift[4] & 31), w26);
-  ASSERT_EQUAL_32(value >> (shift[5] & 31), w27);
+  CHECK_EQUAL_32(value >> (shift[0] & 31), w22);
+  CHECK_EQUAL_32(value >> (shift[1] & 31), w23);
+  CHECK_EQUAL_32(value >> (shift[2] & 31), w24);
+  CHECK_EQUAL_32(value >> (shift[3] & 31), w25);
+  CHECK_EQUAL_32(value >> (shift[4] & 31), w26);
+  CHECK_EQUAL_32(value >> (shift[5] & 31), w27);
 
   TEARDOWN();
 }
 
 
 TEST(asrv) {
   INIT_V8();
   SETUP();
 
   int64_t value = 0xfedcba98fedcba98UL;
@@ skipping 20 matching lines @@
   __ Asr(w22, w0, w1);
   __ Asr(w23, w0, w2);
   __ Asr(w24, w0, w3);
   __ Asr(w25, w0, w4);
   __ Asr(w26, w0, w5);
   __ Asr(w27, w0, w6);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(value, x0);
-  ASSERT_EQUAL_64(value >> (shift[0] & 63), x16);
-  ASSERT_EQUAL_64(value >> (shift[1] & 63), x17);
-  ASSERT_EQUAL_64(value >> (shift[2] & 63), x18);
-  ASSERT_EQUAL_64(value >> (shift[3] & 63), x19);
-  ASSERT_EQUAL_64(value >> (shift[4] & 63), x20);
-  ASSERT_EQUAL_64(value >> (shift[5] & 63), x21);
+  CHECK_EQUAL_64(value, x0);
+  CHECK_EQUAL_64(value >> (shift[0] & 63), x16);
+  CHECK_EQUAL_64(value >> (shift[1] & 63), x17);
+  CHECK_EQUAL_64(value >> (shift[2] & 63), x18);
+  CHECK_EQUAL_64(value >> (shift[3] & 63), x19);
+  CHECK_EQUAL_64(value >> (shift[4] & 63), x20);
+  CHECK_EQUAL_64(value >> (shift[5] & 63), x21);
 
   int32_t value32 = static_cast<int32_t>(value & 0xffffffffUL);
-  ASSERT_EQUAL_32(value32 >> (shift[0] & 31), w22);
-  ASSERT_EQUAL_32(value32 >> (shift[1] & 31), w23);
-  ASSERT_EQUAL_32(value32 >> (shift[2] & 31), w24);
-  ASSERT_EQUAL_32(value32 >> (shift[3] & 31), w25);
-  ASSERT_EQUAL_32(value32 >> (shift[4] & 31), w26);
-  ASSERT_EQUAL_32(value32 >> (shift[5] & 31), w27);
+  CHECK_EQUAL_32(value32 >> (shift[0] & 31), w22);
+  CHECK_EQUAL_32(value32 >> (shift[1] & 31), w23);
+  CHECK_EQUAL_32(value32 >> (shift[2] & 31), w24);
+  CHECK_EQUAL_32(value32 >> (shift[3] & 31), w25);
+  CHECK_EQUAL_32(value32 >> (shift[4] & 31), w26);
+  CHECK_EQUAL_32(value32 >> (shift[5] & 31), w27);
 
   TEARDOWN();
 }
 
 
 TEST(rorv) {
   INIT_V8();
   SETUP();
 
   uint64_t value = 0x0123456789abcdefUL;
@@ skipping 20 matching lines @@
   __ Ror(w22, w0, w1);
   __ Ror(w23, w0, w2);
   __ Ror(w24, w0, w3);
   __ Ror(w25, w0, w4);
   __ Ror(w26, w0, w5);
   __ Ror(w27, w0, w6);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(value, x0);
-  ASSERT_EQUAL_64(0xf0123456789abcdeUL, x16);
-  ASSERT_EQUAL_64(0xef0123456789abcdUL, x17);
-  ASSERT_EQUAL_64(0xdef0123456789abcUL, x18);
-  ASSERT_EQUAL_64(0xcdef0123456789abUL, x19);
-  ASSERT_EQUAL_64(0xabcdef0123456789UL, x20);
-  ASSERT_EQUAL_64(0x789abcdef0123456UL, x21);
-  ASSERT_EQUAL_32(0xf89abcde, w22);
-  ASSERT_EQUAL_32(0xef89abcd, w23);
-  ASSERT_EQUAL_32(0xdef89abc, w24);
-  ASSERT_EQUAL_32(0xcdef89ab, w25);
-  ASSERT_EQUAL_32(0xabcdef89, w26);
-  ASSERT_EQUAL_32(0xf89abcde, w27);
+  CHECK_EQUAL_64(value, x0);
+  CHECK_EQUAL_64(0xf0123456789abcdeUL, x16);
+  CHECK_EQUAL_64(0xef0123456789abcdUL, x17);
+  CHECK_EQUAL_64(0xdef0123456789abcUL, x18);
+  CHECK_EQUAL_64(0xcdef0123456789abUL, x19);
+  CHECK_EQUAL_64(0xabcdef0123456789UL, x20);
+  CHECK_EQUAL_64(0x789abcdef0123456UL, x21);
+  CHECK_EQUAL_32(0xf89abcde, w22);
+  CHECK_EQUAL_32(0xef89abcd, w23);
+  CHECK_EQUAL_32(0xdef89abc, w24);
+  CHECK_EQUAL_32(0xcdef89ab, w25);
+  CHECK_EQUAL_32(0xabcdef89, w26);
+  CHECK_EQUAL_32(0xf89abcde, w27);
 
   TEARDOWN();
 }
 
 
 TEST(bfm) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 13 matching lines @@
   __ bfm(w21, w1, 24, 15);
 
   // Aliases.
   __ Bfi(x12, x1, 16, 8);
   __ Bfxil(x13, x1, 16, 8);
   END();
 
   RUN();
 
 
-  ASSERT_EQUAL_64(0x88888888888889abL, x10);
-  ASSERT_EQUAL_64(0x8888cdef88888888L, x11);
+  CHECK_EQUAL_64(0x88888888888889abL, x10);
+  CHECK_EQUAL_64(0x8888cdef88888888L, x11);
 
-  ASSERT_EQUAL_32(0x888888ab, w20);
-  ASSERT_EQUAL_32(0x88cdef88, w21);
+  CHECK_EQUAL_32(0x888888ab, w20);
+  CHECK_EQUAL_32(0x88cdef88, w21);
 
-  ASSERT_EQUAL_64(0x8888888888ef8888L, x12);
-  ASSERT_EQUAL_64(0x88888888888888abL, x13);
+  CHECK_EQUAL_64(0x8888888888ef8888L, x12);
+  CHECK_EQUAL_64(0x88888888888888abL, x13);
 
   TEARDOWN();
 }
 
 
 TEST(sbfm) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 21 matching lines @@
   __ Sxtb(x25, x2);
   __ Sxth(x26, w1);
   __ Sxth(x27, x2);
   __ Sxtw(x28, w1);
   __ Sxtw(x29, x2);
   END();
 
   RUN();
 
 
-  ASSERT_EQUAL_64(0xffffffffffff89abL, x10);
-  ASSERT_EQUAL_64(0xffffcdef00000000L, x11);
-  ASSERT_EQUAL_64(0x4567L, x12);
-  ASSERT_EQUAL_64(0x789abcdef0000L, x13);
+  CHECK_EQUAL_64(0xffffffffffff89abL, x10);
+  CHECK_EQUAL_64(0xffffcdef00000000L, x11);
+  CHECK_EQUAL_64(0x4567L, x12);
+  CHECK_EQUAL_64(0x789abcdef0000L, x13);
 
-  ASSERT_EQUAL_32(0xffffffab, w14);
-  ASSERT_EQUAL_32(0xffcdef00, w15);
-  ASSERT_EQUAL_32(0x54, w16);
-  ASSERT_EQUAL_32(0x00321000, w17);
+  CHECK_EQUAL_32(0xffffffab, w14);
+  CHECK_EQUAL_32(0xffcdef00, w15);
+  CHECK_EQUAL_32(0x54, w16);
+  CHECK_EQUAL_32(0x00321000, w17);
 
-  ASSERT_EQUAL_64(0x01234567L, x18);
-  ASSERT_EQUAL_64(0xfffffffffedcba98L, x19);
-  ASSERT_EQUAL_64(0xffffffffffcdef00L, x20);
-  ASSERT_EQUAL_64(0x321000L, x21);
-  ASSERT_EQUAL_64(0xffffffffffffabcdL, x22);
-  ASSERT_EQUAL_64(0x5432L, x23);
-  ASSERT_EQUAL_64(0xffffffffffffffefL, x24);
-  ASSERT_EQUAL_64(0x10, x25);
-  ASSERT_EQUAL_64(0xffffffffffffcdefL, x26);
-  ASSERT_EQUAL_64(0x3210, x27);
-  ASSERT_EQUAL_64(0xffffffff89abcdefL, x28);
-  ASSERT_EQUAL_64(0x76543210, x29);
+  CHECK_EQUAL_64(0x01234567L, x18);
+  CHECK_EQUAL_64(0xfffffffffedcba98L, x19);
+  CHECK_EQUAL_64(0xffffffffffcdef00L, x20);
+  CHECK_EQUAL_64(0x321000L, x21);
+  CHECK_EQUAL_64(0xffffffffffffabcdL, x22);
+  CHECK_EQUAL_64(0x5432L, x23);
+  CHECK_EQUAL_64(0xffffffffffffffefL, x24);
+  CHECK_EQUAL_64(0x10, x25);
+  CHECK_EQUAL_64(0xffffffffffffcdefL, x26);
+  CHECK_EQUAL_64(0x3210, x27);
+  CHECK_EQUAL_64(0xffffffff89abcdefL, x28);
+  CHECK_EQUAL_64(0x76543210, x29);
 
   TEARDOWN();
 }
 
 
 TEST(ubfm) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 19 matching lines @@
   __ Lsr(x17, x1, 32);
   __ Ubfiz(x18, x1, 8, 16);
   __ Ubfx(x19, x1, 8, 16);
   __ Uxtb(x20, x1);
   __ Uxth(x21, x1);
   __ Uxtw(x22, x1);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x00000000000089abL, x10);
-  ASSERT_EQUAL_64(0x0000cdef00000000L, x11);
-  ASSERT_EQUAL_64(0x4567L, x12);
-  ASSERT_EQUAL_64(0x789abcdef0000L, x13);
+  CHECK_EQUAL_64(0x00000000000089abL, x10);
+  CHECK_EQUAL_64(0x0000cdef00000000L, x11);
+  CHECK_EQUAL_64(0x4567L, x12);
+  CHECK_EQUAL_64(0x789abcdef0000L, x13);
 
-  ASSERT_EQUAL_32(0x000000ab, w25);
-  ASSERT_EQUAL_32(0x00cdef00, w26);
-  ASSERT_EQUAL_32(0x54, w27);
-  ASSERT_EQUAL_32(0x00321000, w28);
+  CHECK_EQUAL_32(0x000000ab, w25);
+  CHECK_EQUAL_32(0x00cdef00, w26);
+  CHECK_EQUAL_32(0x54, w27);
+  CHECK_EQUAL_32(0x00321000, w28);
 
-  ASSERT_EQUAL_64(0x8000000000000000L, x15);
-  ASSERT_EQUAL_64(0x0123456789abcdefL, x16);
-  ASSERT_EQUAL_64(0x01234567L, x17);
-  ASSERT_EQUAL_64(0xcdef00L, x18);
-  ASSERT_EQUAL_64(0xabcdL, x19);
-  ASSERT_EQUAL_64(0xefL, x20);
-  ASSERT_EQUAL_64(0xcdefL, x21);
-  ASSERT_EQUAL_64(0x89abcdefL, x22);
+  CHECK_EQUAL_64(0x8000000000000000L, x15);
+  CHECK_EQUAL_64(0x0123456789abcdefL, x16);
+  CHECK_EQUAL_64(0x01234567L, x17);
+  CHECK_EQUAL_64(0xcdef00L, x18);
+  CHECK_EQUAL_64(0xabcdL, x19);
+  CHECK_EQUAL_64(0xefL, x20);
+  CHECK_EQUAL_64(0xcdefL, x21);
+  CHECK_EQUAL_64(0x89abcdefL, x22);
 
   TEARDOWN();
 }
 
 
 TEST(extr) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x1, 0x0123456789abcdefL);
   __ Mov(x2, 0xfedcba9876543210L);
 
   __ Extr(w10, w1, w2, 0);
   __ Extr(x11, x1, x2, 0);
   __ Extr(w12, w1, w2, 1);
   __ Extr(x13, x2, x1, 2);
 
   __ Ror(w20, w1, 0);
   __ Ror(x21, x1, 0);
   __ Ror(w22, w2, 17);
   __ Ror(w23, w1, 31);
   __ Ror(x24, x2, 1);
   __ Ror(x25, x1, 63);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x76543210, x10);
-  ASSERT_EQUAL_64(0xfedcba9876543210L, x11);
-  ASSERT_EQUAL_64(0xbb2a1908, x12);
-  ASSERT_EQUAL_64(0x0048d159e26af37bUL, x13);
-  ASSERT_EQUAL_64(0x89abcdef, x20);
-  ASSERT_EQUAL_64(0x0123456789abcdefL, x21);
-  ASSERT_EQUAL_64(0x19083b2a, x22);
-  ASSERT_EQUAL_64(0x13579bdf, x23);
-  ASSERT_EQUAL_64(0x7f6e5d4c3b2a1908UL, x24);
-  ASSERT_EQUAL_64(0x02468acf13579bdeUL, x25);
+  CHECK_EQUAL_64(0x76543210, x10);
+  CHECK_EQUAL_64(0xfedcba9876543210L, x11);
+  CHECK_EQUAL_64(0xbb2a1908, x12);
+  CHECK_EQUAL_64(0x0048d159e26af37bUL, x13);
+  CHECK_EQUAL_64(0x89abcdef, x20);
+  CHECK_EQUAL_64(0x0123456789abcdefL, x21);
+  CHECK_EQUAL_64(0x19083b2a, x22);
+  CHECK_EQUAL_64(0x13579bdf, x23);
+  CHECK_EQUAL_64(0x7f6e5d4c3b2a1908UL, x24);
+  CHECK_EQUAL_64(0x02468acf13579bdeUL, x25);
 
   TEARDOWN();
 }
 
 
 TEST(fmov_imm) {
   INIT_V8();
   SETUP();
 
   START();
   __ Fmov(s11, 1.0);
   __ Fmov(d22, -13.0);
   __ Fmov(s1, 255.0);
   __ Fmov(d2, 12.34567);
   __ Fmov(s3, 0.0);
   __ Fmov(d4, 0.0);
   __ Fmov(s5, kFP32PositiveInfinity);
   __ Fmov(d6, kFP64NegativeInfinity);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(1.0, s11);
-  ASSERT_EQUAL_FP64(-13.0, d22);
-  ASSERT_EQUAL_FP32(255.0, s1);
-  ASSERT_EQUAL_FP64(12.34567, d2);
-  ASSERT_EQUAL_FP32(0.0, s3);
-  ASSERT_EQUAL_FP64(0.0, d4);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s5);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d6);
+  CHECK_EQUAL_FP32(1.0, s11);
+  CHECK_EQUAL_FP64(-13.0, d22);
+  CHECK_EQUAL_FP32(255.0, s1);
+  CHECK_EQUAL_FP64(12.34567, d2);
+  CHECK_EQUAL_FP32(0.0, s3);
+  CHECK_EQUAL_FP64(0.0, d4);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s5);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d6);
 
   TEARDOWN();
 }
 
 
 TEST(fmov_reg) {
   INIT_V8();
   SETUP();
 
   START();
   __ Fmov(s20, 1.0);
   __ Fmov(w10, s20);
   __ Fmov(s30, w10);
   __ Fmov(s5, s20);
   __ Fmov(d1, -13.0);
   __ Fmov(x1, d1);
   __ Fmov(d2, x1);
   __ Fmov(d4, d1);
   __ Fmov(d6, rawbits_to_double(0x0123456789abcdefL));
   __ Fmov(s6, s6);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(float_to_rawbits(1.0), w10);
-  ASSERT_EQUAL_FP32(1.0, s30);
-  ASSERT_EQUAL_FP32(1.0, s5);
-  ASSERT_EQUAL_64(double_to_rawbits(-13.0), x1);
-  ASSERT_EQUAL_FP64(-13.0, d2);
-  ASSERT_EQUAL_FP64(-13.0, d4);
-  ASSERT_EQUAL_FP32(rawbits_to_float(0x89abcdef), s6);
+  CHECK_EQUAL_32(float_to_rawbits(1.0), w10);
+  CHECK_EQUAL_FP32(1.0, s30);
+  CHECK_EQUAL_FP32(1.0, s5);
+  CHECK_EQUAL_64(double_to_rawbits(-13.0), x1);
+  CHECK_EQUAL_FP64(-13.0, d2);
+  CHECK_EQUAL_FP64(-13.0, d4);
+  CHECK_EQUAL_FP32(rawbits_to_float(0x89abcdef), s6);
 
   TEARDOWN();
 }
 
 
 TEST(fadd) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 23 matching lines @@
   __ Fadd(d8, d29, d31);
   __ Fadd(d9, d26, d31);
   __ Fadd(d10, d27, d31);
   __ Fadd(d11, d28, d31);
   __ Fadd(d12, d27, d28);
   __ Fadd(d13, d28, d27);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(4.25, s0);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(1.0, s2);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s3);
-  ASSERT_EQUAL_FP32(kFP32NegativeInfinity, s4);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s5);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s6);
-  ASSERT_EQUAL_FP64(0.25, d7);
-  ASSERT_EQUAL_FP64(2.25, d8);
-  ASSERT_EQUAL_FP64(2.25, d9);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d10);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d11);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d12);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d13);
+  CHECK_EQUAL_FP32(4.25, s0);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(1.0, s2);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s3);
+  CHECK_EQUAL_FP32(kFP32NegativeInfinity, s4);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s5);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s6);
+  CHECK_EQUAL_FP64(0.25, d7);
+  CHECK_EQUAL_FP64(2.25, d8);
+  CHECK_EQUAL_FP64(2.25, d9);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d10);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d11);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d12);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d13);
 
   TEARDOWN();
 }
 
 
 TEST(fsub) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 23 matching lines @@
   __ Fsub(d8, d29, d31);
   __ Fsub(d9, d26, d31);
   __ Fsub(d10, d31, d27);
   __ Fsub(d11, d31, d28);
   __ Fsub(d12, d27, d27);
   __ Fsub(d13, d28, d28);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(2.25, s0);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(-1.0, s2);
-  ASSERT_EQUAL_FP32(kFP32NegativeInfinity, s3);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s4);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s5);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s6);
-  ASSERT_EQUAL_FP64(-4.25, d7);
-  ASSERT_EQUAL_FP64(-2.25, d8);
-  ASSERT_EQUAL_FP64(-2.25, d9);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d10);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d11);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d12);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d13);
+  CHECK_EQUAL_FP32(2.25, s0);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(-1.0, s2);
+  CHECK_EQUAL_FP32(kFP32NegativeInfinity, s3);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s4);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s5);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s6);
+  CHECK_EQUAL_FP64(-4.25, d7);
+  CHECK_EQUAL_FP64(-2.25, d8);
+  CHECK_EQUAL_FP64(-2.25, d9);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d10);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d11);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d12);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d13);
 
   TEARDOWN();
 }
 
 
 TEST(fmul) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 24 matching lines @@
   __ Fmul(d8, d29, d31);
   __ Fmul(d9, d26, d26);
   __ Fmul(d10, d27, d30);
   __ Fmul(d11, d28, d30);
   __ Fmul(d12, d27, d29);
   __ Fmul(d13, d29, d28);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(6.5, s0);
-  ASSERT_EQUAL_FP32(0.0, s1);
-  ASSERT_EQUAL_FP32(0.0, s2);
-  ASSERT_EQUAL_FP32(kFP32NegativeInfinity, s3);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s4);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s5);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s6);
-  ASSERT_EQUAL_FP64(-4.5, d7);
-  ASSERT_EQUAL_FP64(0.0, d8);
-  ASSERT_EQUAL_FP64(0.0, d9);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d10);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d11);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d12);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d13);
+  CHECK_EQUAL_FP32(6.5, s0);
+  CHECK_EQUAL_FP32(0.0, s1);
+  CHECK_EQUAL_FP32(0.0, s2);
+  CHECK_EQUAL_FP32(kFP32NegativeInfinity, s3);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s4);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s5);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s6);
+  CHECK_EQUAL_FP64(-4.5, d7);
+  CHECK_EQUAL_FP64(0.0, d8);
+  CHECK_EQUAL_FP64(0.0, d9);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d10);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d11);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d12);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d13);
 
   TEARDOWN();
 }
 
 
 static void FmaddFmsubHelper(double n, double m, double a,
                              double fmadd, double fmsub,
                              double fnmadd, double fnmsub) {
   SETUP();
   START();
 
   __ Fmov(d0, n);
   __ Fmov(d1, m);
   __ Fmov(d2, a);
   __ Fmadd(d28, d0, d1, d2);
   __ Fmsub(d29, d0, d1, d2);
   __ Fnmadd(d30, d0, d1, d2);
   __ Fnmsub(d31, d0, d1, d2);
 
   END();
   RUN();
 
-  ASSERT_EQUAL_FP64(fmadd, d28);
-  ASSERT_EQUAL_FP64(fmsub, d29);
-  ASSERT_EQUAL_FP64(fnmadd, d30);
-  ASSERT_EQUAL_FP64(fnmsub, d31);
+  CHECK_EQUAL_FP64(fmadd, d28);
+  CHECK_EQUAL_FP64(fmsub, d29);
+  CHECK_EQUAL_FP64(fnmadd, d30);
+  CHECK_EQUAL_FP64(fnmsub, d31);
 
   TEARDOWN();
 }
 
 
 TEST(fmadd_fmsub_double) {
   INIT_V8();
 
   // It's hard to check the result of fused operations because the only way to
   // calculate the result is using fma, which is what the simulator uses anyway.
@@ skipping 44 matching lines @@
   __ Fmov(s1, m);
   __ Fmov(s2, a);
   __ Fmadd(s28, s0, s1, s2);
   __ Fmsub(s29, s0, s1, s2);
   __ Fnmadd(s30, s0, s1, s2);
   __ Fnmsub(s31, s0, s1, s2);
 
   END();
   RUN();
 
-  ASSERT_EQUAL_FP32(fmadd, s28);
-  ASSERT_EQUAL_FP32(fmsub, s29);
-  ASSERT_EQUAL_FP32(fnmadd, s30);
-  ASSERT_EQUAL_FP32(fnmsub, s31);
+  CHECK_EQUAL_FP32(fmadd, s28);
+  CHECK_EQUAL_FP32(fmsub, s29);
+  CHECK_EQUAL_FP32(fnmadd, s30);
+  CHECK_EQUAL_FP32(fnmsub, s31);
 
   TEARDOWN();
 }
 
 
 TEST(fmadd_fmsub_float) {
   INIT_V8();
   // It's hard to check the result of fused operations because the only way to
   // calculate the result is using fma, which is what the simulator uses anyway.
   // TODO(jbramley): Add tests to check behaviour against a hardware trace.
@@ skipping 35 matching lines @@
 
 TEST(fmadd_fmsub_double_nans) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   double s1 = rawbits_to_double(0x7ff5555511111111);
   double s2 = rawbits_to_double(0x7ff5555522222222);
   double sa = rawbits_to_double(0x7ff55555aaaaaaaa);
   double q1 = rawbits_to_double(0x7ffaaaaa11111111);
   double q2 = rawbits_to_double(0x7ffaaaaa22222222);
   double qa = rawbits_to_double(0x7ffaaaaaaaaaaaaa);
-  ASSERT(IsSignallingNaN(s1));
-  ASSERT(IsSignallingNaN(s2));
-  ASSERT(IsSignallingNaN(sa));
-  ASSERT(IsQuietNaN(q1));
-  ASSERT(IsQuietNaN(q2));
-  ASSERT(IsQuietNaN(qa));
+  DCHECK(IsSignallingNaN(s1));
+  DCHECK(IsSignallingNaN(s2));
+  DCHECK(IsSignallingNaN(sa));
+  DCHECK(IsQuietNaN(q1));
+  DCHECK(IsQuietNaN(q2));
+  DCHECK(IsQuietNaN(qa));
 
   // The input NaNs after passing through ProcessNaN.
   double s1_proc = rawbits_to_double(0x7ffd555511111111);
   double s2_proc = rawbits_to_double(0x7ffd555522222222);
   double sa_proc = rawbits_to_double(0x7ffd5555aaaaaaaa);
   double q1_proc = q1;
   double q2_proc = q2;
   double qa_proc = qa;
-  ASSERT(IsQuietNaN(s1_proc));
-  ASSERT(IsQuietNaN(s2_proc));
-  ASSERT(IsQuietNaN(sa_proc));
-  ASSERT(IsQuietNaN(q1_proc));
-  ASSERT(IsQuietNaN(q2_proc));
-  ASSERT(IsQuietNaN(qa_proc));
+  DCHECK(IsQuietNaN(s1_proc));
+  DCHECK(IsQuietNaN(s2_proc));
+  DCHECK(IsQuietNaN(sa_proc));
+  DCHECK(IsQuietNaN(q1_proc));
+  DCHECK(IsQuietNaN(q2_proc));
+  DCHECK(IsQuietNaN(qa_proc));
 
   // Negated NaNs as it would be done on ARMv8 hardware.
   double s1_proc_neg = rawbits_to_double(0xfffd555511111111);
   double sa_proc_neg = rawbits_to_double(0xfffd5555aaaaaaaa);
   double q1_proc_neg = rawbits_to_double(0xfffaaaaa11111111);
   double qa_proc_neg = rawbits_to_double(0xfffaaaaaaaaaaaaa);
-  ASSERT(IsQuietNaN(s1_proc_neg));
-  ASSERT(IsQuietNaN(sa_proc_neg));
-  ASSERT(IsQuietNaN(q1_proc_neg));
-  ASSERT(IsQuietNaN(qa_proc_neg));
+  DCHECK(IsQuietNaN(s1_proc_neg));
+  DCHECK(IsQuietNaN(sa_proc_neg));
+  DCHECK(IsQuietNaN(q1_proc_neg));
+  DCHECK(IsQuietNaN(qa_proc_neg));
 
   // Quiet NaNs are propagated.
   FmaddFmsubHelper(q1, 0, 0, q1_proc, q1_proc_neg, q1_proc_neg, q1_proc);
   FmaddFmsubHelper(0, q2, 0, q2_proc, q2_proc, q2_proc, q2_proc);
   FmaddFmsubHelper(0, 0, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, q2, 0, q1_proc, q1_proc_neg, q1_proc_neg, q1_proc);
   FmaddFmsubHelper(0, q2, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, 0, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, q2, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
 
@@ skipping 33 matching lines @@
 
 TEST(fmadd_fmsub_float_nans) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   float s1 = rawbits_to_float(0x7f951111);
   float s2 = rawbits_to_float(0x7f952222);
   float sa = rawbits_to_float(0x7f95aaaa);
   float q1 = rawbits_to_float(0x7fea1111);
   float q2 = rawbits_to_float(0x7fea2222);
   float qa = rawbits_to_float(0x7feaaaaa);
-  ASSERT(IsSignallingNaN(s1));
-  ASSERT(IsSignallingNaN(s2));
-  ASSERT(IsSignallingNaN(sa));
-  ASSERT(IsQuietNaN(q1));
-  ASSERT(IsQuietNaN(q2));
-  ASSERT(IsQuietNaN(qa));
+  DCHECK(IsSignallingNaN(s1));
+  DCHECK(IsSignallingNaN(s2));
+  DCHECK(IsSignallingNaN(sa));
+  DCHECK(IsQuietNaN(q1));
+  DCHECK(IsQuietNaN(q2));
+  DCHECK(IsQuietNaN(qa));
 
   // The input NaNs after passing through ProcessNaN.
   float s1_proc = rawbits_to_float(0x7fd51111);
   float s2_proc = rawbits_to_float(0x7fd52222);
   float sa_proc = rawbits_to_float(0x7fd5aaaa);
   float q1_proc = q1;
   float q2_proc = q2;
   float qa_proc = qa;
-  ASSERT(IsQuietNaN(s1_proc));
-  ASSERT(IsQuietNaN(s2_proc));
-  ASSERT(IsQuietNaN(sa_proc));
-  ASSERT(IsQuietNaN(q1_proc));
-  ASSERT(IsQuietNaN(q2_proc));
-  ASSERT(IsQuietNaN(qa_proc));
+  DCHECK(IsQuietNaN(s1_proc));
+  DCHECK(IsQuietNaN(s2_proc));
+  DCHECK(IsQuietNaN(sa_proc));
+  DCHECK(IsQuietNaN(q1_proc));
+  DCHECK(IsQuietNaN(q2_proc));
+  DCHECK(IsQuietNaN(qa_proc));
 
   // Negated NaNs as it would be done on ARMv8 hardware.
   float s1_proc_neg = rawbits_to_float(0xffd51111);
   float sa_proc_neg = rawbits_to_float(0xffd5aaaa);
   float q1_proc_neg = rawbits_to_float(0xffea1111);
   float qa_proc_neg = rawbits_to_float(0xffeaaaaa);
-  ASSERT(IsQuietNaN(s1_proc_neg));
-  ASSERT(IsQuietNaN(sa_proc_neg));
-  ASSERT(IsQuietNaN(q1_proc_neg));
-  ASSERT(IsQuietNaN(qa_proc_neg));
+  DCHECK(IsQuietNaN(s1_proc_neg));
+  DCHECK(IsQuietNaN(sa_proc_neg));
+  DCHECK(IsQuietNaN(q1_proc_neg));
+  DCHECK(IsQuietNaN(qa_proc_neg));
 
   // Quiet NaNs are propagated.
   FmaddFmsubHelper(q1, 0, 0, q1_proc, q1_proc_neg, q1_proc_neg, q1_proc);
   FmaddFmsubHelper(0, q2, 0, q2_proc, q2_proc, q2_proc, q2_proc);
   FmaddFmsubHelper(0, 0, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, q2, 0, q1_proc, q1_proc_neg, q1_proc_neg, q1_proc);
   FmaddFmsubHelper(0, q2, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, 0, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
   FmaddFmsubHelper(q1, q2, qa, qa_proc, qa_proc, qa_proc_neg, qa_proc_neg);
 
@@ skipping 63 matching lines @@
   __ Fdiv(d8, d29, d31);
   __ Fdiv(d9, d26, d31);
   __ Fdiv(d10, d31, d27);
   __ Fdiv(d11, d31, d28);
   __ Fdiv(d12, d28, d27);
   __ Fdiv(d13, d29, d29);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(1.625f, s0);
-  ASSERT_EQUAL_FP32(1.0f, s1);
-  ASSERT_EQUAL_FP32(-0.0f, s2);
-  ASSERT_EQUAL_FP32(0.0f, s3);
-  ASSERT_EQUAL_FP32(-0.0f, s4);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s5);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s6);
-  ASSERT_EQUAL_FP64(-1.125, d7);
-  ASSERT_EQUAL_FP64(0.0, d8);
-  ASSERT_EQUAL_FP64(-0.0, d9);
-  ASSERT_EQUAL_FP64(0.0, d10);
-  ASSERT_EQUAL_FP64(-0.0, d11);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d12);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d13);
+  CHECK_EQUAL_FP32(1.625f, s0);
+  CHECK_EQUAL_FP32(1.0f, s1);
+  CHECK_EQUAL_FP32(-0.0f, s2);
+  CHECK_EQUAL_FP32(0.0f, s3);
+  CHECK_EQUAL_FP32(-0.0f, s4);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s5);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s6);
+  CHECK_EQUAL_FP64(-1.125, d7);
+  CHECK_EQUAL_FP64(0.0, d8);
+  CHECK_EQUAL_FP64(-0.0, d9);
+  CHECK_EQUAL_FP64(0.0, d10);
+  CHECK_EQUAL_FP64(-0.0, d11);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d12);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d13);
 
   TEARDOWN();
 }
 
 
 static float MinMaxHelper(float n,
                           float m,
                           bool min,
                           float quiet_nan_substitute = 0.0) {
   uint32_t raw_n = float_to_rawbits(n);
@@ skipping 82 matching lines @@
   __ Fmov(d0, n);
   __ Fmov(d1, m);
   __ Fmin(d28, d0, d1);
   __ Fmax(d29, d0, d1);
   __ Fminnm(d30, d0, d1);
   __ Fmaxnm(d31, d0, d1);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP64(min, d28);
-  ASSERT_EQUAL_FP64(max, d29);
-  ASSERT_EQUAL_FP64(minnm, d30);
-  ASSERT_EQUAL_FP64(maxnm, d31);
+  CHECK_EQUAL_FP64(min, d28);
+  CHECK_EQUAL_FP64(max, d29);
+  CHECK_EQUAL_FP64(minnm, d30);
+  CHECK_EQUAL_FP64(maxnm, d31);
 
   TEARDOWN();
 }
 
 
 TEST(fmax_fmin_d) {
   INIT_V8();
   // Use non-standard NaNs to check that the payload bits are preserved.
   double snan = rawbits_to_double(0x7ff5555512345678);
   double qnan = rawbits_to_double(0x7ffaaaaa87654321);
 
   double snan_processed = rawbits_to_double(0x7ffd555512345678);
   double qnan_processed = qnan;
 
-  ASSERT(IsSignallingNaN(snan));
-  ASSERT(IsQuietNaN(qnan));
-  ASSERT(IsQuietNaN(snan_processed));
-  ASSERT(IsQuietNaN(qnan_processed));
+  DCHECK(IsSignallingNaN(snan));
+  DCHECK(IsQuietNaN(qnan));
+  DCHECK(IsQuietNaN(snan_processed));
+  DCHECK(IsQuietNaN(qnan_processed));
 
   // Bootstrap tests.
   FminFmaxDoubleHelper(0, 0, 0, 0, 0, 0);
   FminFmaxDoubleHelper(0, 1, 0, 1, 0, 1);
   FminFmaxDoubleHelper(kFP64PositiveInfinity, kFP64NegativeInfinity,
                        kFP64NegativeInfinity, kFP64PositiveInfinity,
                        kFP64NegativeInfinity, kFP64PositiveInfinity);
   FminFmaxDoubleHelper(snan, 0,
                        snan_processed, snan_processed,
                        snan_processed, snan_processed);
@@ skipping 43 matching lines @@
   __ Fmov(s0, n);
   __ Fmov(s1, m);
   __ Fmin(s28, s0, s1);
   __ Fmax(s29, s0, s1);
   __ Fminnm(s30, s0, s1);
   __ Fmaxnm(s31, s0, s1);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(min, s28);
-  ASSERT_EQUAL_FP32(max, s29);
-  ASSERT_EQUAL_FP32(minnm, s30);
-  ASSERT_EQUAL_FP32(maxnm, s31);
+  CHECK_EQUAL_FP32(min, s28);
+  CHECK_EQUAL_FP32(max, s29);
+  CHECK_EQUAL_FP32(minnm, s30);
+  CHECK_EQUAL_FP32(maxnm, s31);
 
   TEARDOWN();
 }
 
 
 TEST(fmax_fmin_s) {
   INIT_V8();
   // Use non-standard NaNs to check that the payload bits are preserved.
   float snan = rawbits_to_float(0x7f951234);
   float qnan = rawbits_to_float(0x7fea8765);
 
   float snan_processed = rawbits_to_float(0x7fd51234);
   float qnan_processed = qnan;
 
-  ASSERT(IsSignallingNaN(snan));
-  ASSERT(IsQuietNaN(qnan));
-  ASSERT(IsQuietNaN(snan_processed));
-  ASSERT(IsQuietNaN(qnan_processed));
+  DCHECK(IsSignallingNaN(snan));
+  DCHECK(IsQuietNaN(qnan));
+  DCHECK(IsQuietNaN(snan_processed));
+  DCHECK(IsQuietNaN(qnan_processed));
 
   // Bootstrap tests.
   FminFmaxFloatHelper(0, 0, 0, 0, 0, 0);
   FminFmaxFloatHelper(0, 1, 0, 1, 0, 1);
   FminFmaxFloatHelper(kFP32PositiveInfinity, kFP32NegativeInfinity,
                       kFP32NegativeInfinity, kFP32PositiveInfinity,
                       kFP32NegativeInfinity, kFP32PositiveInfinity);
   FminFmaxFloatHelper(snan, 0,
                       snan_processed, snan_processed,
                       snan_processed, snan_processed);
@@ skipping 81 matching lines @@
   __ fccmp(s16, s16, NFlag, al);
   __ Mrs(x8, NZCV);
 
   __ fccmp(d18, d18, NFlag, nv);
   __ Mrs(x9, NZCV);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(ZCFlag, w0);
-  ASSERT_EQUAL_32(VFlag, w1);
-  ASSERT_EQUAL_32(NFlag, w2);
-  ASSERT_EQUAL_32(CVFlag, w3);
-  ASSERT_EQUAL_32(ZCFlag, w4);
-  ASSERT_EQUAL_32(ZVFlag, w5);
-  ASSERT_EQUAL_32(CFlag, w6);
-  ASSERT_EQUAL_32(NFlag, w7);
-  ASSERT_EQUAL_32(ZCFlag, w8);
-  ASSERT_EQUAL_32(ZCFlag, w9);
+  CHECK_EQUAL_32(ZCFlag, w0);
+  CHECK_EQUAL_32(VFlag, w1);
+  CHECK_EQUAL_32(NFlag, w2);
+  CHECK_EQUAL_32(CVFlag, w3);
+  CHECK_EQUAL_32(ZCFlag, w4);
+  CHECK_EQUAL_32(ZVFlag, w5);
+  CHECK_EQUAL_32(CFlag, w6);
+  CHECK_EQUAL_32(NFlag, w7);
+  CHECK_EQUAL_32(ZCFlag, w8);
+  CHECK_EQUAL_32(ZCFlag, w9);
 
   TEARDOWN();
 }
 
 
 TEST(fcmp) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 49 matching lines @@
     masm.FPTmpList()->set_list(d0.Bit());
     __ Fcmp(d19, 12.3456);
     masm.FPTmpList()->set_list(0);
     __ Mrs(x16, NZCV);
   }
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_32(ZCFlag, w0);
-  ASSERT_EQUAL_32(NFlag, w1);
-  ASSERT_EQUAL_32(CFlag, w2);
-  ASSERT_EQUAL_32(CVFlag, w3);
-  ASSERT_EQUAL_32(CVFlag, w4);
-  ASSERT_EQUAL_32(ZCFlag, w5);
-  ASSERT_EQUAL_32(NFlag, w6);
-  ASSERT_EQUAL_32(ZCFlag, w10);
-  ASSERT_EQUAL_32(NFlag, w11);
-  ASSERT_EQUAL_32(CFlag, w12);
-  ASSERT_EQUAL_32(CVFlag, w13);
-  ASSERT_EQUAL_32(CVFlag, w14);
-  ASSERT_EQUAL_32(ZCFlag, w15);
-  ASSERT_EQUAL_32(NFlag, w16);
+  CHECK_EQUAL_32(ZCFlag, w0);
+  CHECK_EQUAL_32(NFlag, w1);
+  CHECK_EQUAL_32(CFlag, w2);
+  CHECK_EQUAL_32(CVFlag, w3);
+  CHECK_EQUAL_32(CVFlag, w4);
+  CHECK_EQUAL_32(ZCFlag, w5);
+  CHECK_EQUAL_32(NFlag, w6);
+  CHECK_EQUAL_32(ZCFlag, w10);
+  CHECK_EQUAL_32(NFlag, w11);
+  CHECK_EQUAL_32(CFlag, w12);
+  CHECK_EQUAL_32(CVFlag, w13);
+  CHECK_EQUAL_32(CVFlag, w14);
+  CHECK_EQUAL_32(ZCFlag, w15);
+  CHECK_EQUAL_32(NFlag, w16);
 
   TEARDOWN();
 }
 
 
 TEST(fcsel) {
   INIT_V8();
   SETUP();
 
   START();
   __ Mov(x16, 0);
   __ Fmov(s16, 1.0);
   __ Fmov(s17, 2.0);
   __ Fmov(d18, 3.0);
   __ Fmov(d19, 4.0);
 
   __ Cmp(x16, 0);
   __ Fcsel(s0, s16, s17, eq);
   __ Fcsel(s1, s16, s17, ne);
   __ Fcsel(d2, d18, d19, eq);
   __ Fcsel(d3, d18, d19, ne);
   __ fcsel(s4, s16, s17, al);
   __ fcsel(d5, d18, d19, nv);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(1.0, s0);
-  ASSERT_EQUAL_FP32(2.0, s1);
-  ASSERT_EQUAL_FP64(3.0, d2);
-  ASSERT_EQUAL_FP64(4.0, d3);
-  ASSERT_EQUAL_FP32(1.0, s4);
-  ASSERT_EQUAL_FP64(3.0, d5);
+  CHECK_EQUAL_FP32(1.0, s0);
+  CHECK_EQUAL_FP32(2.0, s1);
+  CHECK_EQUAL_FP64(3.0, d2);
+  CHECK_EQUAL_FP64(4.0, d3);
+  CHECK_EQUAL_FP32(1.0, s4);
+  CHECK_EQUAL_FP64(3.0, d5);
 
   TEARDOWN();
 }
 
 
 TEST(fneg) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 13 matching lines @@
   __ Fneg(d6, d19);
   __ Fneg(d7, d6);
   __ Fneg(d8, d20);
   __ Fneg(d9, d8);
   __ Fneg(d10, d21);
   __ Fneg(d11, d10);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(-1.0, s0);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(-0.0, s2);
-  ASSERT_EQUAL_FP32(0.0, s3);
-  ASSERT_EQUAL_FP32(kFP32NegativeInfinity, s4);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s5);
-  ASSERT_EQUAL_FP64(-1.0, d6);
-  ASSERT_EQUAL_FP64(1.0, d7);
-  ASSERT_EQUAL_FP64(-0.0, d8);
-  ASSERT_EQUAL_FP64(0.0, d9);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d10);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d11);
+  CHECK_EQUAL_FP32(-1.0, s0);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(-0.0, s2);
+  CHECK_EQUAL_FP32(0.0, s3);
+  CHECK_EQUAL_FP32(kFP32NegativeInfinity, s4);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s5);
+  CHECK_EQUAL_FP64(-1.0, d6);
+  CHECK_EQUAL_FP64(1.0, d7);
+  CHECK_EQUAL_FP64(-0.0, d8);
+  CHECK_EQUAL_FP64(0.0, d9);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d10);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d11);
 
   TEARDOWN();
 }
 
 
 TEST(fabs) {
   INIT_V8();
   SETUP();
 
   START();
   __ Fmov(s16, -1.0);
   __ Fmov(s17, -0.0);
   __ Fmov(s18, kFP32NegativeInfinity);
   __ Fmov(d19, -1.0);
   __ Fmov(d20, -0.0);
   __ Fmov(d21, kFP64NegativeInfinity);
 
   __ Fabs(s0, s16);
   __ Fabs(s1, s0);
   __ Fabs(s2, s17);
   __ Fabs(s3, s18);
   __ Fabs(d4, d19);
   __ Fabs(d5, d4);
   __ Fabs(d6, d20);
   __ Fabs(d7, d21);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(1.0, s0);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(0.0, s2);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s3);
-  ASSERT_EQUAL_FP64(1.0, d4);
-  ASSERT_EQUAL_FP64(1.0, d5);
-  ASSERT_EQUAL_FP64(0.0, d6);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d7);
+  CHECK_EQUAL_FP32(1.0, s0);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(0.0, s2);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s3);
+  CHECK_EQUAL_FP64(1.0, d4);
+  CHECK_EQUAL_FP64(1.0, d5);
+  CHECK_EQUAL_FP64(0.0, d6);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d7);
 
   TEARDOWN();
 }
 
 
 TEST(fsqrt) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 23 matching lines @@
   __ Fsqrt(d8, d24);
   __ Fsqrt(d9, d25);
   __ Fsqrt(d10, d26);
   __ Fsqrt(d11, d27);
   __ Fsqrt(d12, d28);
   __ Fsqrt(d13, d29);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(0.0, s0);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(0.5, s2);
-  ASSERT_EQUAL_FP32(256.0, s3);
-  ASSERT_EQUAL_FP32(-0.0, s4);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s5);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s6);
-  ASSERT_EQUAL_FP64(0.0, d7);
-  ASSERT_EQUAL_FP64(1.0, d8);
-  ASSERT_EQUAL_FP64(0.5, d9);
-  ASSERT_EQUAL_FP64(65536.0, d10);
-  ASSERT_EQUAL_FP64(-0.0, d11);
-  ASSERT_EQUAL_FP64(kFP32PositiveInfinity, d12);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d13);
+  CHECK_EQUAL_FP32(0.0, s0);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(0.5, s2);
+  CHECK_EQUAL_FP32(256.0, s3);
+  CHECK_EQUAL_FP32(-0.0, s4);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s5);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s6);
+  CHECK_EQUAL_FP64(0.0, d7);
+  CHECK_EQUAL_FP64(1.0, d8);
+  CHECK_EQUAL_FP64(0.5, d9);
+  CHECK_EQUAL_FP64(65536.0, d10);
+  CHECK_EQUAL_FP64(-0.0, d11);
+  CHECK_EQUAL_FP64(kFP32PositiveInfinity, d12);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d13);
 
   TEARDOWN();
 }
 
 
 TEST(frinta) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 45 matching lines @@
   __ Frinta(d18, d22);
   __ Frinta(d19, d23);
   __ Frinta(d20, d24);
   __ Frinta(d21, d25);
   __ Frinta(d22, d26);
   __ Frinta(d23, d27);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(1.0, s0);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(2.0, s2);
-  ASSERT_EQUAL_FP32(2.0, s3);
-  ASSERT_EQUAL_FP32(3.0, s4);
-  ASSERT_EQUAL_FP32(-2.0, s5);
-  ASSERT_EQUAL_FP32(-3.0, s6);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s7);
-  ASSERT_EQUAL_FP32(kFP32NegativeInfinity, s8);
-  ASSERT_EQUAL_FP32(0.0, s9);
-  ASSERT_EQUAL_FP32(-0.0, s10);
-  ASSERT_EQUAL_FP32(-0.0, s11);
-  ASSERT_EQUAL_FP64(1.0, d12);
-  ASSERT_EQUAL_FP64(1.0, d13);
-  ASSERT_EQUAL_FP64(2.0, d14);
-  ASSERT_EQUAL_FP64(2.0, d15);
-  ASSERT_EQUAL_FP64(3.0, d16);
-  ASSERT_EQUAL_FP64(-2.0, d17);
-  ASSERT_EQUAL_FP64(-3.0, d18);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d19);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d20);
-  ASSERT_EQUAL_FP64(0.0, d21);
-  ASSERT_EQUAL_FP64(-0.0, d22);
-  ASSERT_EQUAL_FP64(-0.0, d23);
+  CHECK_EQUAL_FP32(1.0, s0);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(2.0, s2);
+  CHECK_EQUAL_FP32(2.0, s3);
+  CHECK_EQUAL_FP32(3.0, s4);
+  CHECK_EQUAL_FP32(-2.0, s5);
+  CHECK_EQUAL_FP32(-3.0, s6);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s7);
+  CHECK_EQUAL_FP32(kFP32NegativeInfinity, s8);
+  CHECK_EQUAL_FP32(0.0, s9);
+  CHECK_EQUAL_FP32(-0.0, s10);
+  CHECK_EQUAL_FP32(-0.0, s11);
+  CHECK_EQUAL_FP64(1.0, d12);
+  CHECK_EQUAL_FP64(1.0, d13);
+  CHECK_EQUAL_FP64(2.0, d14);
+  CHECK_EQUAL_FP64(2.0, d15);
+  CHECK_EQUAL_FP64(3.0, d16);
+  CHECK_EQUAL_FP64(-2.0, d17);
+  CHECK_EQUAL_FP64(-3.0, d18);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d19);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d20);
+  CHECK_EQUAL_FP64(0.0, d21);
+  CHECK_EQUAL_FP64(-0.0, d22);
+  CHECK_EQUAL_FP64(-0.0, d23);
 
   TEARDOWN();
 }
 
 
 TEST(frintm) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 45 matching lines @@
   __ Frintm(d18, d22);
   __ Frintm(d19, d23);
   __ Frintm(d20, d24);
   __ Frintm(d21, d25);
   __ Frintm(d22, d26);
   __ Frintm(d23, d27);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(1.0, s0);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(1.0, s2);
-  ASSERT_EQUAL_FP32(1.0, s3);
-  ASSERT_EQUAL_FP32(2.0, s4);
-  ASSERT_EQUAL_FP32(-2.0, s5);
-  ASSERT_EQUAL_FP32(-3.0, s6);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s7);
-  ASSERT_EQUAL_FP32(kFP32NegativeInfinity, s8);
-  ASSERT_EQUAL_FP32(0.0, s9);
-  ASSERT_EQUAL_FP32(-0.0, s10);
-  ASSERT_EQUAL_FP32(-1.0, s11);
-  ASSERT_EQUAL_FP64(1.0, d12);
-  ASSERT_EQUAL_FP64(1.0, d13);
-  ASSERT_EQUAL_FP64(1.0, d14);
-  ASSERT_EQUAL_FP64(1.0, d15);
-  ASSERT_EQUAL_FP64(2.0, d16);
-  ASSERT_EQUAL_FP64(-2.0, d17);
-  ASSERT_EQUAL_FP64(-3.0, d18);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d19);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d20);
-  ASSERT_EQUAL_FP64(0.0, d21);
-  ASSERT_EQUAL_FP64(-0.0, d22);
-  ASSERT_EQUAL_FP64(-1.0, d23);
+  CHECK_EQUAL_FP32(1.0, s0);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(1.0, s2);
+  CHECK_EQUAL_FP32(1.0, s3);
+  CHECK_EQUAL_FP32(2.0, s4);
+  CHECK_EQUAL_FP32(-2.0, s5);
+  CHECK_EQUAL_FP32(-3.0, s6);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s7);
+  CHECK_EQUAL_FP32(kFP32NegativeInfinity, s8);
+  CHECK_EQUAL_FP32(0.0, s9);
+  CHECK_EQUAL_FP32(-0.0, s10);
+  CHECK_EQUAL_FP32(-1.0, s11);
+  CHECK_EQUAL_FP64(1.0, d12);
+  CHECK_EQUAL_FP64(1.0, d13);
+  CHECK_EQUAL_FP64(1.0, d14);
+  CHECK_EQUAL_FP64(1.0, d15);
+  CHECK_EQUAL_FP64(2.0, d16);
+  CHECK_EQUAL_FP64(-2.0, d17);
+  CHECK_EQUAL_FP64(-3.0, d18);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d19);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d20);
+  CHECK_EQUAL_FP64(0.0, d21);
+  CHECK_EQUAL_FP64(-0.0, d22);
+  CHECK_EQUAL_FP64(-1.0, d23);
 
   TEARDOWN();
 }
 
 
 TEST(frintn) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 45 matching lines @@
   __ Frintn(d18, d22);
   __ Frintn(d19, d23);
   __ Frintn(d20, d24);
   __ Frintn(d21, d25);
   __ Frintn(d22, d26);
   __ Frintn(d23, d27);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(1.0, s0);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(2.0, s2);
-  ASSERT_EQUAL_FP32(2.0, s3);
-  ASSERT_EQUAL_FP32(2.0, s4);
-  ASSERT_EQUAL_FP32(-2.0, s5);
-  ASSERT_EQUAL_FP32(-2.0, s6);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s7);
-  ASSERT_EQUAL_FP32(kFP32NegativeInfinity, s8);
-  ASSERT_EQUAL_FP32(0.0, s9);
-  ASSERT_EQUAL_FP32(-0.0, s10);
-  ASSERT_EQUAL_FP32(-0.0, s11);
-  ASSERT_EQUAL_FP64(1.0, d12);
-  ASSERT_EQUAL_FP64(1.0, d13);
-  ASSERT_EQUAL_FP64(2.0, d14);
-  ASSERT_EQUAL_FP64(2.0, d15);
-  ASSERT_EQUAL_FP64(2.0, d16);
-  ASSERT_EQUAL_FP64(-2.0, d17);
-  ASSERT_EQUAL_FP64(-2.0, d18);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d19);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d20);
-  ASSERT_EQUAL_FP64(0.0, d21);
-  ASSERT_EQUAL_FP64(-0.0, d22);
-  ASSERT_EQUAL_FP64(-0.0, d23);
+  CHECK_EQUAL_FP32(1.0, s0);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(2.0, s2);
+  CHECK_EQUAL_FP32(2.0, s3);
+  CHECK_EQUAL_FP32(2.0, s4);
+  CHECK_EQUAL_FP32(-2.0, s5);
+  CHECK_EQUAL_FP32(-2.0, s6);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s7);
+  CHECK_EQUAL_FP32(kFP32NegativeInfinity, s8);
+  CHECK_EQUAL_FP32(0.0, s9);
+  CHECK_EQUAL_FP32(-0.0, s10);
+  CHECK_EQUAL_FP32(-0.0, s11);
+  CHECK_EQUAL_FP64(1.0, d12);
+  CHECK_EQUAL_FP64(1.0, d13);
+  CHECK_EQUAL_FP64(2.0, d14);
+  CHECK_EQUAL_FP64(2.0, d15);
+  CHECK_EQUAL_FP64(2.0, d16);
+  CHECK_EQUAL_FP64(-2.0, d17);
+  CHECK_EQUAL_FP64(-2.0, d18);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d19);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d20);
+  CHECK_EQUAL_FP64(0.0, d21);
+  CHECK_EQUAL_FP64(-0.0, d22);
+  CHECK_EQUAL_FP64(-0.0, d23);
 
   TEARDOWN();
 }
 
 
 TEST(frintz) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 41 matching lines @@
   __ Frintz(d16, d21);
   __ Frintz(d17, d22);
   __ Frintz(d18, d23);
   __ Frintz(d19, d24);
   __ Frintz(d20, d25);
   __ Frintz(d21, d26);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP32(1.0, s0);
-  ASSERT_EQUAL_FP32(1.0, s1);
-  ASSERT_EQUAL_FP32(1.0, s2);
-  ASSERT_EQUAL_FP32(1.0, s3);
-  ASSERT_EQUAL_FP32(2.0, s4);
-  ASSERT_EQUAL_FP32(-1.0, s5);
-  ASSERT_EQUAL_FP32(-2.0, s6);
-  ASSERT_EQUAL_FP32(kFP32PositiveInfinity, s7);
-  ASSERT_EQUAL_FP32(kFP32NegativeInfinity, s8);
-  ASSERT_EQUAL_FP32(0.0, s9);
-  ASSERT_EQUAL_FP32(-0.0, s10);
-  ASSERT_EQUAL_FP64(1.0, d11);
-  ASSERT_EQUAL_FP64(1.0, d12);
-  ASSERT_EQUAL_FP64(1.0, d13);
-  ASSERT_EQUAL_FP64(1.0, d14);
-  ASSERT_EQUAL_FP64(2.0, d15);
-  ASSERT_EQUAL_FP64(-1.0, d16);
-  ASSERT_EQUAL_FP64(-2.0, d17);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d18);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d19);
-  ASSERT_EQUAL_FP64(0.0, d20);
-  ASSERT_EQUAL_FP64(-0.0, d21);
+  CHECK_EQUAL_FP32(1.0, s0);
+  CHECK_EQUAL_FP32(1.0, s1);
+  CHECK_EQUAL_FP32(1.0, s2);
+  CHECK_EQUAL_FP32(1.0, s3);
+  CHECK_EQUAL_FP32(2.0, s4);
+  CHECK_EQUAL_FP32(-1.0, s5);
+  CHECK_EQUAL_FP32(-2.0, s6);
+  CHECK_EQUAL_FP32(kFP32PositiveInfinity, s7);
+  CHECK_EQUAL_FP32(kFP32NegativeInfinity, s8);
+  CHECK_EQUAL_FP32(0.0, s9);
+  CHECK_EQUAL_FP32(-0.0, s10);
+  CHECK_EQUAL_FP64(1.0, d11);
+  CHECK_EQUAL_FP64(1.0, d12);
+  CHECK_EQUAL_FP64(1.0, d13);
+  CHECK_EQUAL_FP64(1.0, d14);
+  CHECK_EQUAL_FP64(2.0, d15);
+  CHECK_EQUAL_FP64(-1.0, d16);
+  CHECK_EQUAL_FP64(-2.0, d17);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d18);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d19);
+  CHECK_EQUAL_FP64(0.0, d20);
+  CHECK_EQUAL_FP64(-0.0, d21);
 
   TEARDOWN();
 }
 
 
 TEST(fcvt_ds) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 25 matching lines @@
   __ Fcvt(d9, s25);
   __ Fcvt(d10, s26);
   __ Fcvt(d11, s27);
   __ Fcvt(d12, s28);
   __ Fcvt(d13, s29);
   __ Fcvt(d14, s30);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_FP64(1.0f, d0);
-  ASSERT_EQUAL_FP64(1.1f, d1);
-  ASSERT_EQUAL_FP64(1.5f, d2);
-  ASSERT_EQUAL_FP64(1.9f, d3);
-  ASSERT_EQUAL_FP64(2.5f, d4);
-  ASSERT_EQUAL_FP64(-1.5f, d5);
-  ASSERT_EQUAL_FP64(-2.5f, d6);
-  ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d7);
-  ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d8);
-  ASSERT_EQUAL_FP64(0.0f, d9);
-  ASSERT_EQUAL_FP64(-0.0f, d10);
-  ASSERT_EQUAL_FP64(FLT_MAX, d11);
-  ASSERT_EQUAL_FP64(FLT_MIN, d12);
+  CHECK_EQUAL_FP64(1.0f, d0);
+  CHECK_EQUAL_FP64(1.1f, d1);
+  CHECK_EQUAL_FP64(1.5f, d2);
+  CHECK_EQUAL_FP64(1.9f, d3);
+  CHECK_EQUAL_FP64(2.5f, d4);
+  CHECK_EQUAL_FP64(-1.5f, d5);
+  CHECK_EQUAL_FP64(-2.5f, d6);
+  CHECK_EQUAL_FP64(kFP64PositiveInfinity, d7);
+  CHECK_EQUAL_FP64(kFP64NegativeInfinity, d8);
+  CHECK_EQUAL_FP64(0.0f, d9);
+  CHECK_EQUAL_FP64(-0.0f, d10);
+  CHECK_EQUAL_FP64(FLT_MAX, d11);
+  CHECK_EQUAL_FP64(FLT_MIN, d12);
 
   // Check that the NaN payload is preserved according to ARM64 conversion
   // rules:
   //  - The sign bit is preserved.
   //  - The top bit of the mantissa is forced to 1 (making it a quiet NaN).
   //  - The remaining mantissa bits are copied until they run out.
   //  - The low-order bits that haven't already been assigned are set to 0.
-  ASSERT_EQUAL_FP64(rawbits_to_double(0x7ff82468a0000000), d13);
-  ASSERT_EQUAL_FP64(rawbits_to_double(0x7ff82468a0000000), d14);
+  CHECK_EQUAL_FP64(rawbits_to_double(0x7ff82468a0000000), d13);
+  CHECK_EQUAL_FP64(rawbits_to_double(0x7ff82468a0000000), d14);
 
   TEARDOWN();
 }
 
 
 TEST(fcvt_sd) {
   INIT_V8();
   // There are a huge number of corner-cases to check, so this test iterates
   // through a list. The list is then negated and checked again (since the sign
   // is irrelevant in ties-to-even rounding), so the list shouldn't include any
@@ skipping 79 matching lines @@
     {rawbits_to_double(0x7ff02468bfffffff), rawbits_to_float(0x7fc12345)},
     {rawbits_to_double(0x7ff000001fffffff), rawbits_to_float(0x7fc00000)},
   };
   int count = sizeof(test) / sizeof(test[0]);
 
   for (int i = 0; i < count; i++) {
     double in = test[i].in;
     float expected = test[i].expected;
 
     // We only expect positive input.
-    ASSERT(std::signbit(in) == 0);
-    ASSERT(std::signbit(expected) == 0);
+    DCHECK(std::signbit(in) == 0);
+    DCHECK(std::signbit(expected) == 0);
 
     SETUP();
     START();
 
     __ Fmov(d10, in);
     __ Fcvt(s20, d10);
 
     __ Fmov(d11, -in);
     __ Fcvt(s21, d11);
 
     END();
     RUN();
-    ASSERT_EQUAL_FP32(expected, s20);
-    ASSERT_EQUAL_FP32(-expected, s21);
+    CHECK_EQUAL_FP32(expected, s20);
+    CHECK_EQUAL_FP32(-expected, s21);
     TEARDOWN();
   }
 }
 
 
 TEST(fcvtas) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 55 matching lines @@
   __ Fcvtas(x25, d25);
   __ Fcvtas(x26, d26);
   __ Fcvtas(x27, d27);
   __ Fcvtas(x28, d28);
   __ Fcvtas(x29, d29);
   __ Fcvtas(x30, d30);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(3, x2);
-  ASSERT_EQUAL_64(0xfffffffd, x3);
-  ASSERT_EQUAL_64(0x7fffffff, x4);
-  ASSERT_EQUAL_64(0x80000000, x5);
-  ASSERT_EQUAL_64(0x7fffff80, x6);
-  ASSERT_EQUAL_64(0x80000080, x7);
-  ASSERT_EQUAL_64(1, x8);
-  ASSERT_EQUAL_64(1, x9);
-  ASSERT_EQUAL_64(3, x10);
-  ASSERT_EQUAL_64(0xfffffffd, x11);
-  ASSERT_EQUAL_64(0x7fffffff, x12);
-  ASSERT_EQUAL_64(0x80000000, x13);
-  ASSERT_EQUAL_64(0x7ffffffe, x14);
-  ASSERT_EQUAL_64(0x80000001, x15);
-  ASSERT_EQUAL_64(1, x17);
-  ASSERT_EQUAL_64(3, x18);
-  ASSERT_EQUAL_64(0xfffffffffffffffdUL, x19);
-  ASSERT_EQUAL_64(0x7fffffffffffffffUL, x20);
-  ASSERT_EQUAL_64(0x8000000000000000UL, x21);
-  ASSERT_EQUAL_64(0x7fffff8000000000UL, x22);
-  ASSERT_EQUAL_64(0x8000008000000000UL, x23);
-  ASSERT_EQUAL_64(1, x24);
-  ASSERT_EQUAL_64(3, x25);
-  ASSERT_EQUAL_64(0xfffffffffffffffdUL, x26);
-  ASSERT_EQUAL_64(0x7fffffffffffffffUL, x27);
-  ASSERT_EQUAL_64(0x8000000000000000UL, x28);
-  ASSERT_EQUAL_64(0x7ffffffffffffc00UL, x29);
-  ASSERT_EQUAL_64(0x8000000000000400UL, x30);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(3, x2);
+  CHECK_EQUAL_64(0xfffffffd, x3);
+  CHECK_EQUAL_64(0x7fffffff, x4);
+  CHECK_EQUAL_64(0x80000000, x5);
+  CHECK_EQUAL_64(0x7fffff80, x6);
+  CHECK_EQUAL_64(0x80000080, x7);
+  CHECK_EQUAL_64(1, x8);
+  CHECK_EQUAL_64(1, x9);
+  CHECK_EQUAL_64(3, x10);
+  CHECK_EQUAL_64(0xfffffffd, x11);
+  CHECK_EQUAL_64(0x7fffffff, x12);
+  CHECK_EQUAL_64(0x80000000, x13);
+  CHECK_EQUAL_64(0x7ffffffe, x14);
+  CHECK_EQUAL_64(0x80000001, x15);
+  CHECK_EQUAL_64(1, x17);
+  CHECK_EQUAL_64(3, x18);
+  CHECK_EQUAL_64(0xfffffffffffffffdUL, x19);
+  CHECK_EQUAL_64(0x7fffffffffffffffUL, x20);
+  CHECK_EQUAL_64(0x8000000000000000UL, x21);
+  CHECK_EQUAL_64(0x7fffff8000000000UL, x22);
+  CHECK_EQUAL_64(0x8000008000000000UL, x23);
+  CHECK_EQUAL_64(1, x24);
+  CHECK_EQUAL_64(3, x25);
+  CHECK_EQUAL_64(0xfffffffffffffffdUL, x26);
+  CHECK_EQUAL_64(0x7fffffffffffffffUL, x27);
+  CHECK_EQUAL_64(0x8000000000000000UL, x28);
+  CHECK_EQUAL_64(0x7ffffffffffffc00UL, x29);
+  CHECK_EQUAL_64(0x8000000000000400UL, x30);
 
   TEARDOWN();
 }
 
 
 TEST(fcvtau) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 52 matching lines @@
   __ Fcvtau(x25, d25);
   __ Fcvtau(x26, d26);
   __ Fcvtau(x27, d27);
   __ Fcvtau(x28, d28);
   __ Fcvtau(x29, d29);
   __ Fcvtau(w30, s30);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(3, x2);
-  ASSERT_EQUAL_64(0, x3);
-  ASSERT_EQUAL_64(0xffffffff, x4);
-  ASSERT_EQUAL_64(0, x5);
-  ASSERT_EQUAL_64(0xffffff00, x6);
-  ASSERT_EQUAL_64(1, x8);
-  ASSERT_EQUAL_64(1, x9);
-  ASSERT_EQUAL_64(3, x10);
-  ASSERT_EQUAL_64(0, x11);
-  ASSERT_EQUAL_64(0xffffffff, x12);
-  ASSERT_EQUAL_64(0, x13);
-  ASSERT_EQUAL_64(0xfffffffe, x14);
-  ASSERT_EQUAL_64(1, x16);
-  ASSERT_EQUAL_64(1, x17);
-  ASSERT_EQUAL_64(3, x18);
-  ASSERT_EQUAL_64(0, x19);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x20);
-  ASSERT_EQUAL_64(0, x21);
-  ASSERT_EQUAL_64(0xffffff0000000000UL, x22);
-  ASSERT_EQUAL_64(1, x24);
-  ASSERT_EQUAL_64(3, x25);
-  ASSERT_EQUAL_64(0, x26);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x27);
-  ASSERT_EQUAL_64(0, x28);
-  ASSERT_EQUAL_64(0xfffffffffffff800UL, x29);
-  ASSERT_EQUAL_64(0xffffffff, x30);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(3, x2);
+  CHECK_EQUAL_64(0, x3);
+  CHECK_EQUAL_64(0xffffffff, x4);
+  CHECK_EQUAL_64(0, x5);
+  CHECK_EQUAL_64(0xffffff00, x6);
+  CHECK_EQUAL_64(1, x8);
+  CHECK_EQUAL_64(1, x9);
+  CHECK_EQUAL_64(3, x10);
+  CHECK_EQUAL_64(0, x11);
+  CHECK_EQUAL_64(0xffffffff, x12);
+  CHECK_EQUAL_64(0, x13);
+  CHECK_EQUAL_64(0xfffffffe, x14);
+  CHECK_EQUAL_64(1, x16);
+  CHECK_EQUAL_64(1, x17);
+  CHECK_EQUAL_64(3, x18);
+  CHECK_EQUAL_64(0, x19);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x20);
+  CHECK_EQUAL_64(0, x21);
+  CHECK_EQUAL_64(0xffffff0000000000UL, x22);
+  CHECK_EQUAL_64(1, x24);
+  CHECK_EQUAL_64(3, x25);
+  CHECK_EQUAL_64(0, x26);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x27);
+  CHECK_EQUAL_64(0, x28);
+  CHECK_EQUAL_64(0xfffffffffffff800UL, x29);
+  CHECK_EQUAL_64(0xffffffff, x30);
 
   TEARDOWN();
 }
 
 
 TEST(fcvtms) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 55 matching lines @@
   __ Fcvtms(x25, d25);
   __ Fcvtms(x26, d26);
   __ Fcvtms(x27, d27);
   __ Fcvtms(x28, d28);
   __ Fcvtms(x29, d29);
   __ Fcvtms(x30, d30);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(1, x2);
-  ASSERT_EQUAL_64(0xfffffffe, x3);
-  ASSERT_EQUAL_64(0x7fffffff, x4);
-  ASSERT_EQUAL_64(0x80000000, x5);
-  ASSERT_EQUAL_64(0x7fffff80, x6);
-  ASSERT_EQUAL_64(0x80000080, x7);
-  ASSERT_EQUAL_64(1, x8);
-  ASSERT_EQUAL_64(1, x9);
-  ASSERT_EQUAL_64(1, x10);
-  ASSERT_EQUAL_64(0xfffffffe, x11);
-  ASSERT_EQUAL_64(0x7fffffff, x12);
-  ASSERT_EQUAL_64(0x80000000, x13);
-  ASSERT_EQUAL_64(0x7ffffffe, x14);
-  ASSERT_EQUAL_64(0x80000001, x15);
-  ASSERT_EQUAL_64(1, x17);
-  ASSERT_EQUAL_64(1, x18);
-  ASSERT_EQUAL_64(0xfffffffffffffffeUL, x19);
-  ASSERT_EQUAL_64(0x7fffffffffffffffUL, x20);
-  ASSERT_EQUAL_64(0x8000000000000000UL, x21);
-  ASSERT_EQUAL_64(0x7fffff8000000000UL, x22);
-  ASSERT_EQUAL_64(0x8000008000000000UL, x23);
-  ASSERT_EQUAL_64(1, x24);
-  ASSERT_EQUAL_64(1, x25);
-  ASSERT_EQUAL_64(0xfffffffffffffffeUL, x26);
-  ASSERT_EQUAL_64(0x7fffffffffffffffUL, x27);
-  ASSERT_EQUAL_64(0x8000000000000000UL, x28);
-  ASSERT_EQUAL_64(0x7ffffffffffffc00UL, x29);
-  ASSERT_EQUAL_64(0x8000000000000400UL, x30);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(1, x2);
+  CHECK_EQUAL_64(0xfffffffe, x3);
+  CHECK_EQUAL_64(0x7fffffff, x4);
+  CHECK_EQUAL_64(0x80000000, x5);
+  CHECK_EQUAL_64(0x7fffff80, x6);
+  CHECK_EQUAL_64(0x80000080, x7);
+  CHECK_EQUAL_64(1, x8);
+  CHECK_EQUAL_64(1, x9);
+  CHECK_EQUAL_64(1, x10);
+  CHECK_EQUAL_64(0xfffffffe, x11);
+  CHECK_EQUAL_64(0x7fffffff, x12);
+  CHECK_EQUAL_64(0x80000000, x13);
+  CHECK_EQUAL_64(0x7ffffffe, x14);
+  CHECK_EQUAL_64(0x80000001, x15);
+  CHECK_EQUAL_64(1, x17);
+  CHECK_EQUAL_64(1, x18);
+  CHECK_EQUAL_64(0xfffffffffffffffeUL, x19);
+  CHECK_EQUAL_64(0x7fffffffffffffffUL, x20);
+  CHECK_EQUAL_64(0x8000000000000000UL, x21);
+  CHECK_EQUAL_64(0x7fffff8000000000UL, x22);
+  CHECK_EQUAL_64(0x8000008000000000UL, x23);
+  CHECK_EQUAL_64(1, x24);
+  CHECK_EQUAL_64(1, x25);
+  CHECK_EQUAL_64(0xfffffffffffffffeUL, x26);
+  CHECK_EQUAL_64(0x7fffffffffffffffUL, x27);
+  CHECK_EQUAL_64(0x8000000000000000UL, x28);
+  CHECK_EQUAL_64(0x7ffffffffffffc00UL, x29);
+  CHECK_EQUAL_64(0x8000000000000400UL, x30);
 
   TEARDOWN();
 }
 
 
 TEST(fcvtmu) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 54 matching lines @@
   __ Fcvtmu(x25, d25);
   __ Fcvtmu(x26, d26);
   __ Fcvtmu(x27, d27);
   __ Fcvtmu(x28, d28);
   __ Fcvtmu(x29, d29);
   __ Fcvtmu(x30, d30);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(1, x2);
-  ASSERT_EQUAL_64(0, x3);
-  ASSERT_EQUAL_64(0xffffffff, x4);
-  ASSERT_EQUAL_64(0, x5);
-  ASSERT_EQUAL_64(0x7fffff80, x6);
-  ASSERT_EQUAL_64(0, x7);
-  ASSERT_EQUAL_64(1, x8);
-  ASSERT_EQUAL_64(1, x9);
-  ASSERT_EQUAL_64(1, x10);
-  ASSERT_EQUAL_64(0, x11);
-  ASSERT_EQUAL_64(0xffffffff, x12);
-  ASSERT_EQUAL_64(0, x13);
-  ASSERT_EQUAL_64(0x7ffffffe, x14);
-  ASSERT_EQUAL_64(1, x17);
-  ASSERT_EQUAL_64(1, x18);
-  ASSERT_EQUAL_64(0x0UL, x19);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x20);
-  ASSERT_EQUAL_64(0x0UL, x21);
-  ASSERT_EQUAL_64(0x7fffff8000000000UL, x22);
-  ASSERT_EQUAL_64(0x0UL, x23);
-  ASSERT_EQUAL_64(1, x24);
-  ASSERT_EQUAL_64(1, x25);
-  ASSERT_EQUAL_64(0x0UL, x26);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x27);
-  ASSERT_EQUAL_64(0x0UL, x28);
-  ASSERT_EQUAL_64(0x7ffffffffffffc00UL, x29);
-  ASSERT_EQUAL_64(0x0UL, x30);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(1, x2);
+  CHECK_EQUAL_64(0, x3);
+  CHECK_EQUAL_64(0xffffffff, x4);
+  CHECK_EQUAL_64(0, x5);
+  CHECK_EQUAL_64(0x7fffff80, x6);
+  CHECK_EQUAL_64(0, x7);
+  CHECK_EQUAL_64(1, x8);
+  CHECK_EQUAL_64(1, x9);
+  CHECK_EQUAL_64(1, x10);
+  CHECK_EQUAL_64(0, x11);
+  CHECK_EQUAL_64(0xffffffff, x12);
+  CHECK_EQUAL_64(0, x13);
+  CHECK_EQUAL_64(0x7ffffffe, x14);
+  CHECK_EQUAL_64(1, x17);
+  CHECK_EQUAL_64(1, x18);
+  CHECK_EQUAL_64(0x0UL, x19);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x20);
+  CHECK_EQUAL_64(0x0UL, x21);
+  CHECK_EQUAL_64(0x7fffff8000000000UL, x22);
+  CHECK_EQUAL_64(0x0UL, x23);
+  CHECK_EQUAL_64(1, x24);
+  CHECK_EQUAL_64(1, x25);
+  CHECK_EQUAL_64(0x0UL, x26);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x27);
+  CHECK_EQUAL_64(0x0UL, x28);
+  CHECK_EQUAL_64(0x7ffffffffffffc00UL, x29);
+  CHECK_EQUAL_64(0x0UL, x30);
 
   TEARDOWN();
 }
 
 
 TEST(fcvtns) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 55 matching lines @@
   __ Fcvtns(x25, d25);
   __ Fcvtns(x26, d26);
   __ Fcvtns(x27, d27);
 //  __ Fcvtns(x28, d28);
   __ Fcvtns(x29, d29);
   __ Fcvtns(x30, d30);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(2, x2);
-  ASSERT_EQUAL_64(0xfffffffe, x3);
-  ASSERT_EQUAL_64(0x7fffffff, x4);
-  ASSERT_EQUAL_64(0x80000000, x5);
-  ASSERT_EQUAL_64(0x7fffff80, x6);
-  ASSERT_EQUAL_64(0x80000080, x7);
-  ASSERT_EQUAL_64(1, x8);
-  ASSERT_EQUAL_64(1, x9);
-  ASSERT_EQUAL_64(2, x10);
-  ASSERT_EQUAL_64(0xfffffffe, x11);
-  ASSERT_EQUAL_64(0x7fffffff, x12);
-  ASSERT_EQUAL_64(0x80000000, x13);
-  ASSERT_EQUAL_64(0x7ffffffe, x14);
-  ASSERT_EQUAL_64(0x80000001, x15);
-  ASSERT_EQUAL_64(1, x17);
-  ASSERT_EQUAL_64(2, x18);
-  ASSERT_EQUAL_64(0xfffffffffffffffeUL, x19);
-  ASSERT_EQUAL_64(0x7fffffffffffffffUL, x20);
-  ASSERT_EQUAL_64(0x8000000000000000UL, x21);
-  ASSERT_EQUAL_64(0x7fffff8000000000UL, x22);
-  ASSERT_EQUAL_64(0x8000008000000000UL, x23);
-  ASSERT_EQUAL_64(1, x24);
-  ASSERT_EQUAL_64(2, x25);
-  ASSERT_EQUAL_64(0xfffffffffffffffeUL, x26);
-  ASSERT_EQUAL_64(0x7fffffffffffffffUL, x27);
-//  ASSERT_EQUAL_64(0x8000000000000000UL, x28);
-  ASSERT_EQUAL_64(0x7ffffffffffffc00UL, x29);
-  ASSERT_EQUAL_64(0x8000000000000400UL, x30);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(2, x2);
+  CHECK_EQUAL_64(0xfffffffe, x3);
+  CHECK_EQUAL_64(0x7fffffff, x4);
+  CHECK_EQUAL_64(0x80000000, x5);
+  CHECK_EQUAL_64(0x7fffff80, x6);
+  CHECK_EQUAL_64(0x80000080, x7);
+  CHECK_EQUAL_64(1, x8);
+  CHECK_EQUAL_64(1, x9);
+  CHECK_EQUAL_64(2, x10);
+  CHECK_EQUAL_64(0xfffffffe, x11);
+  CHECK_EQUAL_64(0x7fffffff, x12);
+  CHECK_EQUAL_64(0x80000000, x13);
+  CHECK_EQUAL_64(0x7ffffffe, x14);
+  CHECK_EQUAL_64(0x80000001, x15);
+  CHECK_EQUAL_64(1, x17);
+  CHECK_EQUAL_64(2, x18);
+  CHECK_EQUAL_64(0xfffffffffffffffeUL, x19);
+  CHECK_EQUAL_64(0x7fffffffffffffffUL, x20);
+  CHECK_EQUAL_64(0x8000000000000000UL, x21);
+  CHECK_EQUAL_64(0x7fffff8000000000UL, x22);
+  CHECK_EQUAL_64(0x8000008000000000UL, x23);
+  CHECK_EQUAL_64(1, x24);
+  CHECK_EQUAL_64(2, x25);
+  CHECK_EQUAL_64(0xfffffffffffffffeUL, x26);
+  CHECK_EQUAL_64(0x7fffffffffffffffUL, x27);
+//  CHECK_EQUAL_64(0x8000000000000000UL, x28);
+  CHECK_EQUAL_64(0x7ffffffffffffc00UL, x29);
+  CHECK_EQUAL_64(0x8000000000000400UL, x30);
 
   TEARDOWN();
 }
 
 
 TEST(fcvtnu) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 52 matching lines @@
   __ Fcvtnu(x25, d25);
   __ Fcvtnu(x26, d26);
   __ Fcvtnu(x27, d27);
 //  __ Fcvtnu(x28, d28);
   __ Fcvtnu(x29, d29);
   __ Fcvtnu(w30, s30);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(2, x2);
-  ASSERT_EQUAL_64(0, x3);
-  ASSERT_EQUAL_64(0xffffffff, x4);
-  ASSERT_EQUAL_64(0, x5);
-  ASSERT_EQUAL_64(0xffffff00, x6);
-  ASSERT_EQUAL_64(1, x8);
-  ASSERT_EQUAL_64(1, x9);
-  ASSERT_EQUAL_64(2, x10);
-  ASSERT_EQUAL_64(0, x11);
-  ASSERT_EQUAL_64(0xffffffff, x12);
-  ASSERT_EQUAL_64(0, x13);
-  ASSERT_EQUAL_64(0xfffffffe, x14);
-  ASSERT_EQUAL_64(1, x16);
-  ASSERT_EQUAL_64(1, x17);
-  ASSERT_EQUAL_64(2, x18);
-  ASSERT_EQUAL_64(0, x19);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x20);
-  ASSERT_EQUAL_64(0, x21);
-  ASSERT_EQUAL_64(0xffffff0000000000UL, x22);
-  ASSERT_EQUAL_64(1, x24);
-  ASSERT_EQUAL_64(2, x25);
-  ASSERT_EQUAL_64(0, x26);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x27);
-//  ASSERT_EQUAL_64(0, x28);
-  ASSERT_EQUAL_64(0xfffffffffffff800UL, x29);
-  ASSERT_EQUAL_64(0xffffffff, x30);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(2, x2);
+  CHECK_EQUAL_64(0, x3);
+  CHECK_EQUAL_64(0xffffffff, x4);
+  CHECK_EQUAL_64(0, x5);
+  CHECK_EQUAL_64(0xffffff00, x6);
+  CHECK_EQUAL_64(1, x8);
+  CHECK_EQUAL_64(1, x9);
+  CHECK_EQUAL_64(2, x10);
+  CHECK_EQUAL_64(0, x11);
+  CHECK_EQUAL_64(0xffffffff, x12);
+  CHECK_EQUAL_64(0, x13);
+  CHECK_EQUAL_64(0xfffffffe, x14);
+  CHECK_EQUAL_64(1, x16);
+  CHECK_EQUAL_64(1, x17);
+  CHECK_EQUAL_64(2, x18);
+  CHECK_EQUAL_64(0, x19);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x20);
+  CHECK_EQUAL_64(0, x21);
+  CHECK_EQUAL_64(0xffffff0000000000UL, x22);
+  CHECK_EQUAL_64(1, x24);
+  CHECK_EQUAL_64(2, x25);
+  CHECK_EQUAL_64(0, x26);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x27);
+//  CHECK_EQUAL_64(0, x28);
+  CHECK_EQUAL_64(0xfffffffffffff800UL, x29);
+  CHECK_EQUAL_64(0xffffffff, x30);
 
   TEARDOWN();
 }
 
 
 TEST(fcvtzs) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 55 matching lines @@
   __ Fcvtzs(x25, d25);
   __ Fcvtzs(x26, d26);
   __ Fcvtzs(x27, d27);
   __ Fcvtzs(x28, d28);
   __ Fcvtzs(x29, d29);
   __ Fcvtzs(x30, d30);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(1, x2);
-  ASSERT_EQUAL_64(0xffffffff, x3);
-  ASSERT_EQUAL_64(0x7fffffff, x4);
-  ASSERT_EQUAL_64(0x80000000, x5);
-  ASSERT_EQUAL_64(0x7fffff80, x6);
-  ASSERT_EQUAL_64(0x80000080, x7);
-  ASSERT_EQUAL_64(1, x8);
-  ASSERT_EQUAL_64(1, x9);
-  ASSERT_EQUAL_64(1, x10);
-  ASSERT_EQUAL_64(0xffffffff, x11);
-  ASSERT_EQUAL_64(0x7fffffff, x12);
-  ASSERT_EQUAL_64(0x80000000, x13);
-  ASSERT_EQUAL_64(0x7ffffffe, x14);
-  ASSERT_EQUAL_64(0x80000001, x15);
-  ASSERT_EQUAL_64(1, x17);
-  ASSERT_EQUAL_64(1, x18);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x19);
-  ASSERT_EQUAL_64(0x7fffffffffffffffUL, x20);
-  ASSERT_EQUAL_64(0x8000000000000000UL, x21);
-  ASSERT_EQUAL_64(0x7fffff8000000000UL, x22);
-  ASSERT_EQUAL_64(0x8000008000000000UL, x23);
-  ASSERT_EQUAL_64(1, x24);
-  ASSERT_EQUAL_64(1, x25);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x26);
-  ASSERT_EQUAL_64(0x7fffffffffffffffUL, x27);
-  ASSERT_EQUAL_64(0x8000000000000000UL, x28);
-  ASSERT_EQUAL_64(0x7ffffffffffffc00UL, x29);
-  ASSERT_EQUAL_64(0x8000000000000400UL, x30);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(1, x2);
+  CHECK_EQUAL_64(0xffffffff, x3);
+  CHECK_EQUAL_64(0x7fffffff, x4);
+  CHECK_EQUAL_64(0x80000000, x5);
+  CHECK_EQUAL_64(0x7fffff80, x6);
+  CHECK_EQUAL_64(0x80000080, x7);
+  CHECK_EQUAL_64(1, x8);
+  CHECK_EQUAL_64(1, x9);
+  CHECK_EQUAL_64(1, x10);
+  CHECK_EQUAL_64(0xffffffff, x11);
+  CHECK_EQUAL_64(0x7fffffff, x12);
+  CHECK_EQUAL_64(0x80000000, x13);
+  CHECK_EQUAL_64(0x7ffffffe, x14);
+  CHECK_EQUAL_64(0x80000001, x15);
+  CHECK_EQUAL_64(1, x17);
+  CHECK_EQUAL_64(1, x18);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x19);
+  CHECK_EQUAL_64(0x7fffffffffffffffUL, x20);
+  CHECK_EQUAL_64(0x8000000000000000UL, x21);
+  CHECK_EQUAL_64(0x7fffff8000000000UL, x22);
+  CHECK_EQUAL_64(0x8000008000000000UL, x23);
+  CHECK_EQUAL_64(1, x24);
+  CHECK_EQUAL_64(1, x25);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x26);
+  CHECK_EQUAL_64(0x7fffffffffffffffUL, x27);
+  CHECK_EQUAL_64(0x8000000000000000UL, x28);
+  CHECK_EQUAL_64(0x7ffffffffffffc00UL, x29);
+  CHECK_EQUAL_64(0x8000000000000400UL, x30);
 
   TEARDOWN();
 }
 
 
 TEST(fcvtzu) {
   INIT_V8();
   SETUP();
 
   START();
@@ skipping 54 matching lines @@
   __ Fcvtzu(x25, d25);
   __ Fcvtzu(x26, d26);
   __ Fcvtzu(x27, d27);
   __ Fcvtzu(x28, d28);
   __ Fcvtzu(x29, d29);
   __ Fcvtzu(x30, d30);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
-  ASSERT_EQUAL_64(1, x1);
-  ASSERT_EQUAL_64(1, x2);
-  ASSERT_EQUAL_64(0, x3);
-  ASSERT_EQUAL_64(0xffffffff, x4);
-  ASSERT_EQUAL_64(0, x5);
-  ASSERT_EQUAL_64(0x7fffff80, x6);
-  ASSERT_EQUAL_64(0, x7);
-  ASSERT_EQUAL_64(1, x8);
-  ASSERT_EQUAL_64(1, x9);
-  ASSERT_EQUAL_64(1, x10);
-  ASSERT_EQUAL_64(0, x11);
-  ASSERT_EQUAL_64(0xffffffff, x12);
-  ASSERT_EQUAL_64(0, x13);
-  ASSERT_EQUAL_64(0x7ffffffe, x14);
-  ASSERT_EQUAL_64(1, x17);
-  ASSERT_EQUAL_64(1, x18);
-  ASSERT_EQUAL_64(0x0UL, x19);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x20);
-  ASSERT_EQUAL_64(0x0UL, x21);
-  ASSERT_EQUAL_64(0x7fffff8000000000UL, x22);
-  ASSERT_EQUAL_64(0x0UL, x23);
-  ASSERT_EQUAL_64(1, x24);
-  ASSERT_EQUAL_64(1, x25);
-  ASSERT_EQUAL_64(0x0UL, x26);
-  ASSERT_EQUAL_64(0xffffffffffffffffUL, x27);
-  ASSERT_EQUAL_64(0x0UL, x28);
-  ASSERT_EQUAL_64(0x7ffffffffffffc00UL, x29);
-  ASSERT_EQUAL_64(0x0UL, x30);
+  CHECK_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(1, x1);
+  CHECK_EQUAL_64(1, x2);
+  CHECK_EQUAL_64(0, x3);
+  CHECK_EQUAL_64(0xffffffff, x4);
+  CHECK_EQUAL_64(0, x5);
+  CHECK_EQUAL_64(0x7fffff80, x6);
+  CHECK_EQUAL_64(0, x7);
+  CHECK_EQUAL_64(1, x8);
+  CHECK_EQUAL_64(1, x9);
+  CHECK_EQUAL_64(1, x10);
+  CHECK_EQUAL_64(0, x11);
+  CHECK_EQUAL_64(0xffffffff, x12);
+  CHECK_EQUAL_64(0, x13);
+  CHECK_EQUAL_64(0x7ffffffe, x14);
+  CHECK_EQUAL_64(1, x17);
+  CHECK_EQUAL_64(1, x18);
+  CHECK_EQUAL_64(0x0UL, x19);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x20);
+  CHECK_EQUAL_64(0x0UL, x21);
+  CHECK_EQUAL_64(0x7fffff8000000000UL, x22);
+  CHECK_EQUAL_64(0x0UL, x23);
+  CHECK_EQUAL_64(1, x24);
+  CHECK_EQUAL_64(1, x25);
+  CHECK_EQUAL_64(0x0UL, x26);
+  CHECK_EQUAL_64(0xffffffffffffffffUL, x27);
+  CHECK_EQUAL_64(0x0UL, x28);
+  CHECK_EQUAL_64(0x7ffffffffffffc00UL, x29);
+  CHECK_EQUAL_64(0x0UL, x30);
 
   TEARDOWN();
 }
 
 
 // Test that scvtf and ucvtf can convert the 64-bit input into the expected
 // value. All possible values of 'fbits' are tested. The expected value is
 // modified accordingly in each case.
 //
 // The expected value is specified as the bit encoding of the expected double
@@ skipping 67 matching lines @@
   END();
   RUN();
 
   // Check the results.
   double expected_scvtf_base = rawbits_to_double(expected_scvtf_bits);
   double expected_ucvtf_base = rawbits_to_double(expected_ucvtf_bits);
 
   for (int fbits = 0; fbits <= 32; fbits++) {
     double expected_scvtf = expected_scvtf_base / pow(2.0, fbits);
     double expected_ucvtf = expected_ucvtf_base / pow(2.0, fbits);
-    ASSERT_EQUAL_FP64(expected_scvtf, results_scvtf_x[fbits]);
-    ASSERT_EQUAL_FP64(expected_ucvtf, results_ucvtf_x[fbits]);
-    if (cvtf_s32) ASSERT_EQUAL_FP64(expected_scvtf, results_scvtf_w[fbits]);
-    if (cvtf_u32) ASSERT_EQUAL_FP64(expected_ucvtf, results_ucvtf_w[fbits]);
+    CHECK_EQUAL_FP64(expected_scvtf, results_scvtf_x[fbits]);
+    CHECK_EQUAL_FP64(expected_ucvtf, results_ucvtf_x[fbits]);
+    if (cvtf_s32) CHECK_EQUAL_FP64(expected_scvtf, results_scvtf_w[fbits]);
+    if (cvtf_u32) CHECK_EQUAL_FP64(expected_ucvtf, results_ucvtf_w[fbits]);
   }
   for (int fbits = 33; fbits <= 64; fbits++) {
     double expected_scvtf = expected_scvtf_base / pow(2.0, fbits);
     double expected_ucvtf = expected_ucvtf_base / pow(2.0, fbits);
-    ASSERT_EQUAL_FP64(expected_scvtf, results_scvtf_x[fbits]);
-    ASSERT_EQUAL_FP64(expected_ucvtf, results_ucvtf_x[fbits]);
+    CHECK_EQUAL_FP64(expected_scvtf, results_scvtf_x[fbits]);
+    CHECK_EQUAL_FP64(expected_ucvtf, results_ucvtf_x[fbits]);
   }
 
   TEARDOWN();
 }
 
 
 TEST(scvtf_ucvtf_double) {
   INIT_V8();
   // Simple conversions of positive numbers which require no rounding; the
   // results should not depened on the rounding mode, and ucvtf and scvtf should
@@ skipping 125 matching lines @@
   END();
   RUN();
 
   // Check the results.
   float expected_scvtf_base = rawbits_to_float(expected_scvtf_bits);
   float expected_ucvtf_base = rawbits_to_float(expected_ucvtf_bits);
 
   for (int fbits = 0; fbits <= 32; fbits++) {
     float expected_scvtf = expected_scvtf_base / powf(2, fbits);
     float expected_ucvtf = expected_ucvtf_base / powf(2, fbits);
-    ASSERT_EQUAL_FP32(expected_scvtf, results_scvtf_x[fbits]);
-    ASSERT_EQUAL_FP32(expected_ucvtf, results_ucvtf_x[fbits]);
-    if (cvtf_s32) ASSERT_EQUAL_FP32(expected_scvtf, results_scvtf_w[fbits]);
-    if (cvtf_u32) ASSERT_EQUAL_FP32(expected_ucvtf, results_ucvtf_w[fbits]);
+    CHECK_EQUAL_FP32(expected_scvtf, results_scvtf_x[fbits]);
+    CHECK_EQUAL_FP32(expected_ucvtf, results_ucvtf_x[fbits]);
+    if (cvtf_s32) CHECK_EQUAL_FP32(expected_scvtf, results_scvtf_w[fbits]);
+    if (cvtf_u32) CHECK_EQUAL_FP32(expected_ucvtf, results_ucvtf_w[fbits]);
     break;
   }
   for (int fbits = 33; fbits <= 64; fbits++) {
     break;
     float expected_scvtf = expected_scvtf_base / powf(2, fbits);
     float expected_ucvtf = expected_ucvtf_base / powf(2, fbits);
-    ASSERT_EQUAL_FP32(expected_scvtf, results_scvtf_x[fbits]);
-    ASSERT_EQUAL_FP32(expected_ucvtf, results_ucvtf_x[fbits]);
+    CHECK_EQUAL_FP32(expected_scvtf, results_scvtf_x[fbits]);
+    CHECK_EQUAL_FP32(expected_ucvtf, results_ucvtf_x[fbits]);
   }
 
   TEARDOWN();
 }
 
 
 TEST(scvtf_ucvtf_float) {
   INIT_V8();
   // Simple conversions of positive numbers which require no rounding; the
   // results should not depened on the rounding mode, and ucvtf and scvtf should
@@ skipping 83 matching lines @@
   __ Adds(w0, w2, w2);
   __ Mrs(x5, NZCV);
 
   // Read the default FPCR.
   __ Mrs(x6, FPCR);
   END();
 
   RUN();
 
   // NZCV
-  ASSERT_EQUAL_32(ZCFlag, w3);
-  ASSERT_EQUAL_32(NFlag, w4);
-  ASSERT_EQUAL_32(ZCVFlag, w5);
+  CHECK_EQUAL_32(ZCFlag, w3);
+  CHECK_EQUAL_32(NFlag, w4);
+  CHECK_EQUAL_32(ZCVFlag, w5);
 
   // FPCR
   // The default FPCR on Linux-based platforms is 0.
-  ASSERT_EQUAL_32(0, w6);
+  CHECK_EQUAL_32(0, w6);
 
   TEARDOWN();
 }
 
 
 TEST(system_msr) {
   INIT_V8();
   // All FPCR fields that must be implemented: AHP, DN, FZ, RMode
   const uint64_t fpcr_core = 0x07c00000;
 
@@ skipping 47 matching lines @@
   // for the simulator.
   __ Mov(x10, ~fpcr_all);
   __ Msr(FPCR, x10);
   __ Mrs(x10, FPCR);
 
   END();
 
   RUN();
 
   // We should have incremented x7 (from 0) exactly 8 times.
-  ASSERT_EQUAL_64(8, x7);
+  CHECK_EQUAL_64(8, x7);
 
-  ASSERT_EQUAL_64(fpcr_core, x8);
-  ASSERT_EQUAL_64(fpcr_core, x9);
-  ASSERT_EQUAL_64(0, x10);
+  CHECK_EQUAL_64(fpcr_core, x8);
+  CHECK_EQUAL_64(fpcr_core, x9);
+  CHECK_EQUAL_64(0, x10);
 
   TEARDOWN();
 }
 
 
 TEST(system_nop) {
   INIT_V8();
   SETUP();
   RegisterDump before;
 
   START();
   before.Dump(&masm);
   __ Nop();
   END();
 
   RUN();
 
-  ASSERT_EQUAL_REGISTERS(before);
-  ASSERT_EQUAL_NZCV(before.flags_nzcv());
+  CHECK_EQUAL_REGISTERS(before);
+  CHECK_EQUAL_NZCV(before.flags_nzcv());
 
   TEARDOWN();
 }
 
 
 TEST(zero_dest) {
   INIT_V8();
   SETUP();
   RegisterDump before;
 
@@ skipping 45 matching lines @@
   __ Mov(x29, x30);
   __ Mov(x30, csp);
   __ Mov(csp, x29);
   // We used x29 as a scratch register, so reset it to make sure it doesn't
   // trigger a test failure.
   __ Add(x29, x28, x1);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_REGISTERS(before);
-  ASSERT_EQUAL_NZCV(before.flags_nzcv());
+  CHECK_EQUAL_REGISTERS(before);
+  CHECK_EQUAL_NZCV(before.flags_nzcv());
 
   TEARDOWN();
 }
 
 
 TEST(zero_dest_setflags) {
   INIT_V8();
   SETUP();
   RegisterDump before;
 
@@ skipping 43 matching lines @@
   __ Mov(x29, x30);
   __ Mov(x30, csp);
   __ Mov(csp, x29);
   // We used x29 as a scratch register, so reset it to make sure it doesn't
   // trigger a test failure.
   __ Add(x29, x28, x1);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_REGISTERS(before);
+  CHECK_EQUAL_REGISTERS(before);
 
   TEARDOWN();
 }
 
 
 TEST(register_bit) {
   // No code generation takes place in this test, so no need to setup and
   // teardown.
 
   // Simple tests.
@@ skipping 92 matching lines @@
   __ Peek(w10, 0);
   __ Peek(w11, 4);
   __ Peek(w12, 8);
   __ Peek(w13, 12);
 
   __ Drop(4);
 
   END();
   RUN();
 
-  ASSERT_EQUAL_64(literal_base * 1, x0);
-  ASSERT_EQUAL_64(literal_base * 2, x1);
-  ASSERT_EQUAL_64(literal_base * 3, x2);
-  ASSERT_EQUAL_64(literal_base * 4, x3);
+  CHECK_EQUAL_64(literal_base * 1, x0);
+  CHECK_EQUAL_64(literal_base * 2, x1);
+  CHECK_EQUAL_64(literal_base * 3, x2);
+  CHECK_EQUAL_64(literal_base * 4, x3);
 
-  ASSERT_EQUAL_64((literal_base * 1) & 0xffffffff, x10);
-  ASSERT_EQUAL_64((literal_base * 2) & 0xffffffff, x11);
-  ASSERT_EQUAL_64((literal_base * 3) & 0xffffffff, x12);
-  ASSERT_EQUAL_64((literal_base * 4) & 0xffffffff, x13);
+  CHECK_EQUAL_64((literal_base * 1) & 0xffffffff, x10);
+  CHECK_EQUAL_64((literal_base * 2) & 0xffffffff, x11);
+  CHECK_EQUAL_64((literal_base * 3) & 0xffffffff, x12);
+  CHECK_EQUAL_64((literal_base * 4) & 0xffffffff, x13);
 
   TEARDOWN();
 }
 
 
 TEST(peek_poke_unaligned) {
   INIT_V8();
   SETUP();
   START();
 
@@ skipping 49 matching lines @@
   __ Peek(w11, 2);
   __ Poke(w2, 3);
   Clobber(&masm, w12.Bit());
   __ Peek(w12, 3);
 
   __ Drop(4);
 
   END();
   RUN();
 
-  ASSERT_EQUAL_64(literal_base * 1, x0);
-  ASSERT_EQUAL_64(literal_base * 2, x1);
-  ASSERT_EQUAL_64(literal_base * 3, x2);
-  ASSERT_EQUAL_64(literal_base * 4, x3);
-  ASSERT_EQUAL_64(literal_base * 5, x4);
-  ASSERT_EQUAL_64(literal_base * 6, x5);
-  ASSERT_EQUAL_64(literal_base * 7, x6);
+  CHECK_EQUAL_64(literal_base * 1, x0);
+  CHECK_EQUAL_64(literal_base * 2, x1);
+  CHECK_EQUAL_64(literal_base * 3, x2);
+  CHECK_EQUAL_64(literal_base * 4, x3);
+  CHECK_EQUAL_64(literal_base * 5, x4);
+  CHECK_EQUAL_64(literal_base * 6, x5);
+  CHECK_EQUAL_64(literal_base * 7, x6);
 
-  ASSERT_EQUAL_64((literal_base * 1) & 0xffffffff, x10);
-  ASSERT_EQUAL_64((literal_base * 2) & 0xffffffff, x11);
-  ASSERT_EQUAL_64((literal_base * 3) & 0xffffffff, x12);
+  CHECK_EQUAL_64((literal_base * 1) & 0xffffffff, x10);
+  CHECK_EQUAL_64((literal_base * 2) & 0xffffffff, x11);
+  CHECK_EQUAL_64((literal_base * 3) & 0xffffffff, x12);
 
   TEARDOWN();
 }
 
 
 TEST(peek_poke_endianness) {
   INIT_V8();
   SETUP();
   START();
 
@@ skipping 26 matching lines @@
 
   END();
   RUN();
 
   uint64_t x0_expected = literal_base * 1;
   uint64_t x1_expected = literal_base * 2;
   uint64_t x4_expected = (x0_expected << 32) | (x0_expected >> 32);
   uint64_t x5_expected = ((x1_expected << 16) & 0xffff0000) |
                          ((x1_expected >> 16) & 0x0000ffff);
 
-  ASSERT_EQUAL_64(x0_expected, x0);
-  ASSERT_EQUAL_64(x1_expected, x1);
-  ASSERT_EQUAL_64(x4_expected, x4);
-  ASSERT_EQUAL_64(x5_expected, x5);
+  CHECK_EQUAL_64(x0_expected, x0);
+  CHECK_EQUAL_64(x1_expected, x1);
+  CHECK_EQUAL_64(x4_expected, x4);
+  CHECK_EQUAL_64(x5_expected, x5);
 
   TEARDOWN();
 }
 
 
 TEST(peek_poke_mixed) {
   INIT_V8();
   SETUP();
   START();
 
@@ skipping 13 matching lines @@
   __ Claim(4);
 
   // Mix with other stack operations.
   //  After this section:
   //    x0-x3 should be unchanged.
   //    x6 should match x1[31:0]:x0[63:32]
   //    w7 should match x1[15:0]:x0[63:48]
   __ Poke(x1, 8);
   __ Poke(x0, 0);
   {
-    ASSERT(__ StackPointer().Is(csp));
+    DCHECK(__ StackPointer().Is(csp));
     __ Mov(x4, __ StackPointer());
     __ SetStackPointer(x4);
 
     __ Poke(wzr, 0);    // Clobber the space we're about to drop.
     __ Drop(1, kWRegSize);
     __ Peek(x6, 0);
     __ Claim(1);
     __ Peek(w7, 10);
     __ Poke(x3, 28);
     __ Poke(xzr, 0);    // Clobber the space we're about to drop.
@@ skipping 11 matching lines @@
   RUN();
 
   uint64_t x0_expected = literal_base * 1;
   uint64_t x1_expected = literal_base * 2;
   uint64_t x2_expected = literal_base * 3;
   uint64_t x3_expected = literal_base * 4;
   uint64_t x6_expected = (x1_expected << 32) | (x0_expected >> 32);
   uint64_t x7_expected = ((x1_expected << 16) & 0xffff0000) |
                          ((x0_expected >> 48) & 0x0000ffff);
 
-  ASSERT_EQUAL_64(x0_expected, x0);
-  ASSERT_EQUAL_64(x1_expected, x1);
-  ASSERT_EQUAL_64(x2_expected, x2);
-  ASSERT_EQUAL_64(x3_expected, x3);
-  ASSERT_EQUAL_64(x6_expected, x6);
-  ASSERT_EQUAL_64(x7_expected, x7);
+  CHECK_EQUAL_64(x0_expected, x0);
+  CHECK_EQUAL_64(x1_expected, x1);
+  CHECK_EQUAL_64(x2_expected, x2);
+  CHECK_EQUAL_64(x3_expected, x3);
+  CHECK_EQUAL_64(x6_expected, x6);
+  CHECK_EQUAL_64(x7_expected, x7);
 
   TEARDOWN();
 }
 
 
 // This enum is used only as an argument to the push-pop test helpers.
 enum PushPopMethod {
   // Push or Pop using the Push and Pop methods, with blocks of up to four
   // registers. (Smaller blocks will be used if necessary.)
   PushPopByFour,
@@ skipping 39 matching lines @@
                                        allowed);
 
   // The literal base is chosen to have two useful properties:
   //  * When multiplied by small values (such as a register index), this value
   //    is clearly readable in the result.
   //  * The value is not formed from repeating fixed-size smaller values, so it
   //    can be used to detect endianness-related errors.
   uint64_t literal_base = 0x0100001000100101UL;
 
   {
-    ASSERT(__ StackPointer().Is(csp));
+    DCHECK(__ StackPointer().Is(csp));
     __ Mov(jssp, __ StackPointer());
     __ SetStackPointer(jssp);
 
     int i;
 
     // Initialize the registers.
     for (i = 0; i < reg_count; i++) {
       // Always write into the X register, to ensure that the upper word is
       // properly ignored by Push when testing W registers.
       if (!x[i].IsZero()) {
         __ Mov(x[i], literal_base * i);
       }
     }
 
     // Claim memory first, as requested.
     __ Claim(claim, kByteSizeInBytes);
 
     switch (push_method) {
       case PushPopByFour:
         // Push high-numbered registers first (to the highest addresses).
         for (i = reg_count; i >= 4; i -= 4) {
           __ Push(r[i-1], r[i-2], r[i-3], r[i-4]);
         }
         // Finish off the leftovers.
         switch (i) {
           case 3:  __ Push(r[2], r[1], r[0]); break;
           case 2:  __ Push(r[1], r[0]);       break;
           case 1:  __ Push(r[0]);             break;
-          default: ASSERT(i == 0);            break;
+          default: DCHECK(i == 0);            break;
         }
         break;
       case PushPopRegList:
         __ PushSizeRegList(list, reg_size);
         break;
     }
 
     // Clobber all the registers, to ensure that they get repopulated by Pop.
     Clobber(&masm, list);
 
     switch (pop_method) {
       case PushPopByFour:
         // Pop low-numbered registers first (from the lowest addresses).
         for (i = 0; i <= (reg_count-4); i += 4) {
           __ Pop(r[i], r[i+1], r[i+2], r[i+3]);
         }
         // Finish off the leftovers.
         switch (reg_count - i) {
           case 3:  __ Pop(r[i], r[i+1], r[i+2]); break;
           case 2:  __ Pop(r[i], r[i+1]);         break;
           case 1:  __ Pop(r[i]);                 break;
-          default: ASSERT(i == reg_count);       break;
+          default: DCHECK(i == reg_count);       break;
         }
         break;
       case PushPopRegList:
         __ PopSizeRegList(list, reg_size);
         break;
     }
 
     // Drop memory to restore jssp.
     __ Drop(claim, kByteSizeInBytes);
 
     __ Mov(csp, __ StackPointer());
     __ SetStackPointer(csp);
   }
 
   END();
 
   RUN();
 
   // Check that the register contents were preserved.
-  // Always use ASSERT_EQUAL_64, even when testing W registers, so we can test
+  // Always use CHECK_EQUAL_64, even when testing W registers, so we can test
   // that the upper word was properly cleared by Pop.
   literal_base &= (0xffffffffffffffffUL >> (64-reg_size));
   for (int i = 0; i < reg_count; i++) {
     if (x[i].IsZero()) {
-      ASSERT_EQUAL_64(0, x[i]);
+      CHECK_EQUAL_64(0, x[i]);
     } else {
-      ASSERT_EQUAL_64(literal_base * i, x[i]);
+      CHECK_EQUAL_64(literal_base * i, x[i]);
     }
   }
 
   TEARDOWN();
 }
 
 
 TEST(push_pop_jssp_simple_32) {
   INIT_V8();
   for (int claim = 0; claim <= 8; claim++) {
@@ skipping 83 matching lines @@
   // The literal base is chosen to have two useful properties:
   //  * When multiplied (using an integer) by small values (such as a register
   //    index), this value is clearly readable in the result.
   //  * The value is not formed from repeating fixed-size smaller values, so it
   //    can be used to detect endianness-related errors.
   //  * It is never a floating-point NaN, and will therefore always compare
   //    equal to itself.
   uint64_t literal_base = 0x0100001000100101UL;
 
   {
-    ASSERT(__ StackPointer().Is(csp));
+    DCHECK(__ StackPointer().Is(csp));
     __ Mov(jssp, __ StackPointer());
     __ SetStackPointer(jssp);
 
     int i;
 
     // Initialize the registers, using X registers to load the literal.
     __ Mov(x0, 0);
     __ Mov(x1, literal_base);
     for (i = 0; i < reg_count; i++) {
       // Always write into the D register, to ensure that the upper word is
@@ skipping 10 matching lines @@
       case PushPopByFour:
         // Push high-numbered registers first (to the highest addresses).
         for (i = reg_count; i >= 4; i -= 4) {
           __ Push(v[i-1], v[i-2], v[i-3], v[i-4]);
         }
         // Finish off the leftovers.
         switch (i) {
           case 3:  __ Push(v[2], v[1], v[0]); break;
           case 2:  __ Push(v[1], v[0]);       break;
           case 1:  __ Push(v[0]);             break;
-          default: ASSERT(i == 0);            break;
+          default: DCHECK(i == 0);            break;
         }
         break;
       case PushPopRegList:
         __ PushSizeRegList(list, reg_size, CPURegister::kFPRegister);
         break;
     }
 
     // Clobber all the registers, to ensure that they get repopulated by Pop.
     ClobberFP(&masm, list);
 
     switch (pop_method) {
       case PushPopByFour:
         // Pop low-numbered registers first (from the lowest addresses).
         for (i = 0; i <= (reg_count-4); i += 4) {
           __ Pop(v[i], v[i+1], v[i+2], v[i+3]);
         }
         // Finish off the leftovers.
         switch (reg_count - i) {
           case 3:  __ Pop(v[i], v[i+1], v[i+2]); break;
           case 2:  __ Pop(v[i], v[i+1]);         break;
           case 1:  __ Pop(v[i]);                 break;
-          default: ASSERT(i == reg_count);       break;
+          default: DCHECK(i == reg_count);       break;
         }
         break;
       case PushPopRegList:
         __ PopSizeRegList(list, reg_size, CPURegister::kFPRegister);
         break;
     }
 
     // Drop memory to restore jssp.
     __ Drop(claim, kByteSizeInBytes);
 
     __ Mov(csp, __ StackPointer());
     __ SetStackPointer(csp);
   }
 
   END();
 
   RUN();
 
   // Check that the register contents were preserved.
-  // Always use ASSERT_EQUAL_FP64, even when testing S registers, so we can
+  // Always use CHECK_EQUAL_FP64, even when testing S registers, so we can
   // test that the upper word was properly cleared by Pop.
   literal_base &= (0xffffffffffffffffUL >> (64-reg_size));
   for (int i = 0; i < reg_count; i++) {
     uint64_t literal = literal_base * i;
     double expected;
     memcpy(&expected, &literal, sizeof(expected));
-    ASSERT_EQUAL_FP64(expected, d[i]);
+    CHECK_EQUAL_FP64(expected, d[i]);
   }
 
   TEARDOWN();
 }
 
 
 TEST(push_pop_fp_jssp_simple_32) {
   INIT_V8();
   for (int claim = 0; claim <= 8; claim++) {
     for (int count = 0; count <= 8; count++) {
@@ skipping 76 matching lines @@
 
   // The literal base is chosen to have two useful properties:
   //  * When multiplied by small values (such as a register index), this value
   //    is clearly readable in the result.
   //  * The value is not formed from repeating fixed-size smaller values, so it
   //    can be used to detect endianness-related errors.
   uint64_t literal_base = 0x0100001000100101UL;
 
   START();
   {
-    ASSERT(__ StackPointer().Is(csp));
+    DCHECK(__ StackPointer().Is(csp));
     __ Mov(jssp, __ StackPointer());
     __ SetStackPointer(jssp);
 
     // Claim memory first, as requested.
     __ Claim(claim, kByteSizeInBytes);
 
     __ Mov(x[3], literal_base * 3);
     __ Mov(x[2], literal_base * 2);
     __ Mov(x[1], literal_base * 1);
     __ Mov(x[0], literal_base * 0);
@@ skipping 15 matching lines @@
     __ Drop(claim, kByteSizeInBytes);
 
     __ Mov(csp, __ StackPointer());
     __ SetStackPointer(csp);
   }
 
   END();
 
   RUN();
 
-  // Always use ASSERT_EQUAL_64, even when testing W registers, so we can test
+  // Always use CHECK_EQUAL_64, even when testing W registers, so we can test
   // that the upper word was properly cleared by Pop.
   literal_base &= (0xffffffffffffffffUL >> (64-reg_size));
 
-  ASSERT_EQUAL_64(literal_base * 3, x[9]);
-  ASSERT_EQUAL_64(literal_base * 2, x[8]);
-  ASSERT_EQUAL_64(literal_base * 0, x[7]);
-  ASSERT_EQUAL_64(literal_base * 3, x[6]);
-  ASSERT_EQUAL_64(literal_base * 1, x[5]);
-  ASSERT_EQUAL_64(literal_base * 2, x[4]);
+  CHECK_EQUAL_64(literal_base * 3, x[9]);
+  CHECK_EQUAL_64(literal_base * 2, x[8]);
+  CHECK_EQUAL_64(literal_base * 0, x[7]);
+  CHECK_EQUAL_64(literal_base * 3, x[6]);
+  CHECK_EQUAL_64(literal_base * 1, x[5]);
+  CHECK_EQUAL_64(literal_base * 2, x[4]);
 
   TEARDOWN();
 }
 
 
 TEST(push_pop_jssp_mixed_methods_64) {
   INIT_V8();
   for (int claim = 0; claim <= 8; claim++) {
     PushPopJsspMixedMethodsHelper(claim, kXRegSizeInBits);
   }
@@ skipping 39 matching lines @@
   //    is clearly readable in the result.
   //  * The value is not formed from repeating fixed-size smaller values, so it
   //    can be used to detect endianness-related errors.
   static uint64_t const literal_base = 0x0100001000100101UL;
   static uint64_t const literal_base_hi = literal_base >> 32;
   static uint64_t const literal_base_lo = literal_base & 0xffffffff;
   static uint64_t const literal_base_w = literal_base & 0xffffffff;
 
   START();
   {
-    ASSERT(__ StackPointer().Is(csp));
+    DCHECK(__ StackPointer().Is(csp));
     __ Mov(jssp, __ StackPointer());
     __ SetStackPointer(jssp);
 
     // Initialize the registers.
     for (int i = 0; i < reg_count; i++) {
       // Always write into the X register, to ensure that the upper word is
       // properly ignored by Push when testing W registers.
       if (!x[i].IsZero()) {
         __ Mov(x[i], literal_base * i);
       }
@@ skipping 27 matching lines @@
     // where i is the register number.
     // Registers are popped starting with the higher numbers one-by-one,
     // alternating between x and w registers, but only popping one at a time.
     //
     // This pattern provides a wide variety of alignment effects and overlaps.
 
     // ---- Push ----
 
     int active_w_slots = 0;
     for (int i = 0; active_w_slots < requested_w_slots; i++) {
-      ASSERT(i < reg_count);
+      DCHECK(i < reg_count);
       // In order to test various arguments to PushMultipleTimes, and to try to
       // exercise different alignment and overlap effects, we push each
       // register a different number of times.
       int times = i % 4 + 1;
       if (i & 1) {
         // Push odd-numbered registers as W registers.
         if (i & 2) {
           __ PushMultipleTimes(w[i], times);
         } else {
           // Use a register to specify the count.
@@ skipping 52 matching lines @@
     for (int i = reg_count-1; i >= 0; i--) {
       if (next_is_64) {
         __ Pop(x[i]);
         active_w_slots -= 2;
       } else {
         __ Pop(w[i]);
         active_w_slots -= 1;
       }
       next_is_64 = !next_is_64;
     }
-    ASSERT(active_w_slots == 0);
+    DCHECK(active_w_slots == 0);
 
     // Drop memory to restore jssp.
     __ Drop(claim, kByteSizeInBytes);
 
     __ Mov(csp, __ StackPointer());
     __ SetStackPointer(csp);
   }
 
   END();
 
   RUN();
 
   int slot = 0;
   for (int i = 0; i < reg_count; i++) {
     // Even-numbered registers were written as W registers.
     // Odd-numbered registers were written as X registers.
     bool expect_64 = (i & 1);
     uint64_t expected;
 
     if (expect_64) {
       uint64_t hi = stack[slot++];
       uint64_t lo = stack[slot++];
       expected = (hi << 32) | lo;
     } else {
       expected = stack[slot++];
     }
 
-    // Always use ASSERT_EQUAL_64, even when testing W registers, so we can
+    // Always use CHECK_EQUAL_64, even when testing W registers, so we can
     // test that the upper word was properly cleared by Pop.
     if (x[i].IsZero()) {
-      ASSERT_EQUAL_64(0, x[i]);
+      CHECK_EQUAL_64(0, x[i]);
     } else {
-      ASSERT_EQUAL_64(expected, x[i]);
+      CHECK_EQUAL_64(expected, x[i]);
     }
   }
-  ASSERT(slot == requested_w_slots);
+  DCHECK(slot == requested_w_slots);
 
   TEARDOWN();
 }
 
 
 TEST(push_pop_jssp_wx_overlap) {
   INIT_V8();
   for (int claim = 0; claim <= 8; claim++) {
     for (int count = 1; count <= 8; count++) {
       PushPopJsspWXOverlapHelper(count, claim);
       PushPopJsspWXOverlapHelper(count, claim);
       PushPopJsspWXOverlapHelper(count, claim);
       PushPopJsspWXOverlapHelper(count, claim);
     }
     // Test with the maximum number of registers.
     PushPopJsspWXOverlapHelper(kPushPopJsspMaxRegCount, claim);
     PushPopJsspWXOverlapHelper(kPushPopJsspMaxRegCount, claim);
     PushPopJsspWXOverlapHelper(kPushPopJsspMaxRegCount, claim);
     PushPopJsspWXOverlapHelper(kPushPopJsspMaxRegCount, claim);
   }
 }
 
 
 TEST(push_pop_csp) {
   INIT_V8();
   SETUP();
 
   START();
 
-  ASSERT(csp.Is(__ StackPointer()));
+  DCHECK(csp.Is(__ StackPointer()));
 
   __ Mov(x3, 0x3333333333333333UL);
   __ Mov(x2, 0x2222222222222222UL);
   __ Mov(x1, 0x1111111111111111UL);
   __ Mov(x0, 0x0000000000000000UL);
   __ Claim(2);
   __ PushXRegList(x0.Bit() | x1.Bit() | x2.Bit() | x3.Bit());
   __ Push(x3, x2);
   __ PopXRegList(x0.Bit() | x1.Bit() | x2.Bit() | x3.Bit());
   __ Push(x2, x1, x3, x0);
@@ skipping 24 matching lines @@
   __ PushXRegList(0);
   __ PopXRegList(0);
   __ PushXRegList(0xffffffff);
   __ PopXRegList(0xffffffff);
   __ Drop(12);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1111111111111111UL, x3);
-  ASSERT_EQUAL_64(0x0000000000000000UL, x2);
-  ASSERT_EQUAL_64(0x3333333333333333UL, x1);
-  ASSERT_EQUAL_64(0x2222222222222222UL, x0);
-  ASSERT_EQUAL_64(0x3333333333333333UL, x9);
-  ASSERT_EQUAL_64(0x2222222222222222UL, x8);
-  ASSERT_EQUAL_64(0x0000000000000000UL, x7);
-  ASSERT_EQUAL_64(0x3333333333333333UL, x6);
-  ASSERT_EQUAL_64(0x1111111111111111UL, x5);
-  ASSERT_EQUAL_64(0x2222222222222222UL, x4);
+  CHECK_EQUAL_64(0x1111111111111111UL, x3);
+  CHECK_EQUAL_64(0x0000000000000000UL, x2);
+  CHECK_EQUAL_64(0x3333333333333333UL, x1);
+  CHECK_EQUAL_64(0x2222222222222222UL, x0);
+  CHECK_EQUAL_64(0x3333333333333333UL, x9);
+  CHECK_EQUAL_64(0x2222222222222222UL, x8);
+  CHECK_EQUAL_64(0x0000000000000000UL, x7);
+  CHECK_EQUAL_64(0x3333333333333333UL, x6);
+  CHECK_EQUAL_64(0x1111111111111111UL, x5);
+  CHECK_EQUAL_64(0x2222222222222222UL, x4);
 
-  ASSERT_EQUAL_32(0x11111111U, w13);
-  ASSERT_EQUAL_32(0x33333333U, w12);
-  ASSERT_EQUAL_32(0x00000000U, w11);
-  ASSERT_EQUAL_32(0x22222222U, w10);
-  ASSERT_EQUAL_32(0x11111111U, w17);
-  ASSERT_EQUAL_32(0x00000000U, w16);
-  ASSERT_EQUAL_32(0x33333333U, w15);
-  ASSERT_EQUAL_32(0x22222222U, w14);
+  CHECK_EQUAL_32(0x11111111U, w13);
+  CHECK_EQUAL_32(0x33333333U, w12);
+  CHECK_EQUAL_32(0x00000000U, w11);
+  CHECK_EQUAL_32(0x22222222U, w10);
+  CHECK_EQUAL_32(0x11111111U, w17);
+  CHECK_EQUAL_32(0x00000000U, w16);
+  CHECK_EQUAL_32(0x33333333U, w15);
+  CHECK_EQUAL_32(0x22222222U, w14);
 
-  ASSERT_EQUAL_32(0x11111111U, w18);
-  ASSERT_EQUAL_32(0x11111111U, w19);
-  ASSERT_EQUAL_32(0x11111111U, w20);
-  ASSERT_EQUAL_32(0x11111111U, w21);
-  ASSERT_EQUAL_64(0x3333333333333333UL, x22);
-  ASSERT_EQUAL_64(0x0000000000000000UL, x23);
+  CHECK_EQUAL_32(0x11111111U, w18);
+  CHECK_EQUAL_32(0x11111111U, w19);
+  CHECK_EQUAL_32(0x11111111U, w20);
+  CHECK_EQUAL_32(0x11111111U, w21);
+  CHECK_EQUAL_64(0x3333333333333333UL, x22);
+  CHECK_EQUAL_64(0x0000000000000000UL, x23);
 
-  ASSERT_EQUAL_64(0x3333333333333333UL, x24);
-  ASSERT_EQUAL_64(0x3333333333333333UL, x26);
+  CHECK_EQUAL_64(0x3333333333333333UL, x24);
+  CHECK_EQUAL_64(0x3333333333333333UL, x26);
 
-  ASSERT_EQUAL_32(0x33333333U, w25);
-  ASSERT_EQUAL_32(0x00000000U, w27);
-  ASSERT_EQUAL_32(0x22222222U, w28);
-  ASSERT_EQUAL_32(0x33333333U, w29);
+  CHECK_EQUAL_32(0x33333333U, w25);
+  CHECK_EQUAL_32(0x00000000U, w27);
+  CHECK_EQUAL_32(0x22222222U, w28);
+  CHECK_EQUAL_32(0x33333333U, w29);
   TEARDOWN();
 }
 
 
 TEST(push_queued) {
   INIT_V8();
   SETUP();
 
   START();
 
-  ASSERT(__ StackPointer().Is(csp));
+  DCHECK(__ StackPointer().Is(csp));
   __ Mov(jssp, __ StackPointer());
   __ SetStackPointer(jssp);
 
   MacroAssembler::PushPopQueue queue(&masm);
 
   // Queue up registers.
   queue.Queue(x0);
   queue.Queue(x1);
   queue.Queue(x2);
   queue.Queue(x3);
@@ skipping 30 matching lines @@
   __ Pop(w6, w5, w4);
   __ Pop(x3, x2, x1, x0);
 
   __ Mov(csp, __ StackPointer());
   __ SetStackPointer(csp);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1234000000000000, x0);
-  ASSERT_EQUAL_64(0x1234000100010001, x1);
-  ASSERT_EQUAL_64(0x1234000200020002, x2);
-  ASSERT_EQUAL_64(0x1234000300030003, x3);
+  CHECK_EQUAL_64(0x1234000000000000, x0);
+  CHECK_EQUAL_64(0x1234000100010001, x1);
+  CHECK_EQUAL_64(0x1234000200020002, x2);
+  CHECK_EQUAL_64(0x1234000300030003, x3);
 
-  ASSERT_EQUAL_32(0x12340004, w4);
-  ASSERT_EQUAL_32(0x12340005, w5);
-  ASSERT_EQUAL_32(0x12340006, w6);
+  CHECK_EQUAL_32(0x12340004, w4);
+  CHECK_EQUAL_32(0x12340005, w5);
+  CHECK_EQUAL_32(0x12340006, w6);
 
-  ASSERT_EQUAL_FP64(123400.0, d0);
-  ASSERT_EQUAL_FP64(123401.0, d1);
+  CHECK_EQUAL_FP64(123400.0, d0);
+  CHECK_EQUAL_FP64(123401.0, d1);
 
-  ASSERT_EQUAL_FP32(123402.0, s2);
+  CHECK_EQUAL_FP32(123402.0, s2);
 
   TEARDOWN();
 }
 
 
 TEST(pop_queued) {
   INIT_V8();
   SETUP();
 
   START();
 
-  ASSERT(__ StackPointer().Is(csp));
+  DCHECK(__ StackPointer().Is(csp));
   __ Mov(jssp, __ StackPointer());
   __ SetStackPointer(jssp);
 
   MacroAssembler::PushPopQueue queue(&masm);
 
   __ Mov(x0, 0x1234000000000000);
   __ Mov(x1, 0x1234000100010001);
   __ Mov(x2, 0x1234000200020002);
   __ Mov(x3, 0x1234000300030003);
   __ Mov(w4, 0x12340004);
@@ skipping 30 matching lines @@
   // Actually pop them.
   queue.PopQueued();
 
   __ Mov(csp, __ StackPointer());
   __ SetStackPointer(csp);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x1234000000000000, x0);
-  ASSERT_EQUAL_64(0x1234000100010001, x1);
-  ASSERT_EQUAL_64(0x1234000200020002, x2);
-  ASSERT_EQUAL_64(0x1234000300030003, x3);
+  CHECK_EQUAL_64(0x1234000000000000, x0);
+  CHECK_EQUAL_64(0x1234000100010001, x1);
+  CHECK_EQUAL_64(0x1234000200020002, x2);
+  CHECK_EQUAL_64(0x1234000300030003, x3);
 
-  ASSERT_EQUAL_64(0x0000000012340004, x4);
-  ASSERT_EQUAL_64(0x0000000012340005, x5);
-  ASSERT_EQUAL_64(0x0000000012340006, x6);
+  CHECK_EQUAL_64(0x0000000012340004, x4);
+  CHECK_EQUAL_64(0x0000000012340005, x5);
+  CHECK_EQUAL_64(0x0000000012340006, x6);
 
-  ASSERT_EQUAL_FP64(123400.0, d0);
-  ASSERT_EQUAL_FP64(123401.0, d1);
+  CHECK_EQUAL_FP64(123400.0, d0);
+  CHECK_EQUAL_FP64(123401.0, d1);
 
-  ASSERT_EQUAL_FP32(123402.0, s2);
+  CHECK_EQUAL_FP32(123402.0, s2);
 
   TEARDOWN();
 }
 
 
 TEST(jump_both_smi) {
   INIT_V8();
   SETUP();
 
   Label cond_pass_00, cond_pass_01, cond_pass_10, cond_pass_11;
@@ skipping 45 matching lines @@
   __ B(&done);
   __ Bind(&cond_pass_11);
   __ Mov(x7, 1);
 
   __ Bind(&done);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x5555555500000001UL, x0);
-  ASSERT_EQUAL_64(0xaaaaaaaa00000001UL, x1);
-  ASSERT_EQUAL_64(0x1234567800000000UL, x2);
-  ASSERT_EQUAL_64(0x8765432100000000UL, x3);
-  ASSERT_EQUAL_64(0, x4);
-  ASSERT_EQUAL_64(0, x5);
-  ASSERT_EQUAL_64(0, x6);
-  ASSERT_EQUAL_64(1, x7);
+  CHECK_EQUAL_64(0x5555555500000001UL, x0);
+  CHECK_EQUAL_64(0xaaaaaaaa00000001UL, x1);
+  CHECK_EQUAL_64(0x1234567800000000UL, x2);
+  CHECK_EQUAL_64(0x8765432100000000UL, x3);
+  CHECK_EQUAL_64(0, x4);
+  CHECK_EQUAL_64(0, x5);
+  CHECK_EQUAL_64(0, x6);
+  CHECK_EQUAL_64(1, x7);
 
   TEARDOWN();
 }
 
 
 TEST(jump_either_smi) {
   INIT_V8();
   SETUP();
 
   Label cond_pass_00, cond_pass_01, cond_pass_10, cond_pass_11;
@@ skipping 45 matching lines @@
   __ B(&done);
   __ Bind(&cond_pass_11);
   __ Mov(x7, 1);
 
   __ Bind(&done);
 
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0x5555555500000001UL, x0);
-  ASSERT_EQUAL_64(0xaaaaaaaa00000001UL, x1);
-  ASSERT_EQUAL_64(0x1234567800000000UL, x2);
-  ASSERT_EQUAL_64(0x8765432100000000UL, x3);
-  ASSERT_EQUAL_64(0, x4);
-  ASSERT_EQUAL_64(1, x5);
-  ASSERT_EQUAL_64(1, x6);
-  ASSERT_EQUAL_64(1, x7);
+  CHECK_EQUAL_64(0x5555555500000001UL, x0);
+  CHECK_EQUAL_64(0xaaaaaaaa00000001UL, x1);
+  CHECK_EQUAL_64(0x1234567800000000UL, x2);
+  CHECK_EQUAL_64(0x8765432100000000UL, x3);
+  CHECK_EQUAL_64(0, x4);
+  CHECK_EQUAL_64(1, x5);
+  CHECK_EQUAL_64(1, x6);
+  CHECK_EQUAL_64(1, x7);
 
   TEARDOWN();
 }
 
 
 TEST(noreg) {
   // This test doesn't generate any code, but it verifies some invariants
   // related to NoReg.
   CHECK(NoReg.Is(NoFPReg));
   CHECK(NoFPReg.Is(NoReg));
@@ skipping 391 matching lines @@
   __ Printf("Test %%s: %s\n", x2);
   __ Printf("w3(uint32): %" PRIu32 "\nw4(int32): %" PRId32 "\n"
             "x5(uint64): %" PRIu64 "\nx6(int64): %" PRId64 "\n",
             w3, w4, x5, x6);
   __ Printf("%%f: %f\n%%g: %g\n%%e: %e\n%%E: %E\n", s1, s2, d3, d4);
   __ Printf("0x%" PRIx32 ", 0x%" PRIx64 "\n", w28, x28);
   __ Printf("%g\n", d10);
   __ Printf("%%%%%s%%%c%%\n", x2, w13);
 
   // Print the stack pointer (csp).
-  ASSERT(csp.Is(__ StackPointer()));
+  DCHECK(csp.Is(__ StackPointer()));
   __ Printf("StackPointer(csp): 0x%016" PRIx64 ", 0x%08" PRIx32 "\n",
             __ StackPointer(), __ StackPointer().W());
 
   // Test with a different stack pointer.
   const Register old_stack_pointer = __ StackPointer();
   __ Mov(x29, old_stack_pointer);
   __ SetStackPointer(x29);
   // Print the stack pointer (not csp).
   __ Printf("StackPointer(not csp): 0x%016" PRIx64 ", 0x%08" PRIx32 "\n",
             __ StackPointer(), __ StackPointer().W());
   __ Mov(old_stack_pointer, __ StackPointer());
   __ SetStackPointer(old_stack_pointer);
 
   // Test with three arguments.
   __ Printf("3=%u, 4=%u, 5=%u\n", x10, x11, x12);
 
   // Mixed argument types.
   __ Printf("w3: %" PRIu32 ", s1: %f, x5: %" PRIu64 ", d3: %f\n",
             w3, s1, x5, d3);
   __ Printf("s1: %f, d3: %f, w3: %" PRId32 ", x5: %" PRId64 "\n",
             s1, d3, w3, x5);
 
   END();
   RUN();
 
   // We cannot easily test the output of the Printf sequences, and because
   // Printf preserves all registers by default, we can't look at the number of
   // bytes that were printed. However, the printf_no_preserve test should check
   // that, and here we just test that we didn't clobber any registers.
-  ASSERT_EQUAL_REGISTERS(before);
+  CHECK_EQUAL_REGISTERS(before);
 
   TEARDOWN();
 }
 
 
 TEST(printf_no_preserve) {
   INIT_V8();
   SETUP();
   START();
 
@@ skipping 73 matching lines @@
                       w3, s1, x5, d3);
   __ Mov(x29, x0);
 
   END();
   RUN();
 
   // We cannot easily test the exact output of the Printf sequences, but we can
   // use the return code to check that the string length was correct.
 
   // Printf with no arguments.
-  ASSERT_EQUAL_64(strlen(test_plain_string), x19);
+  CHECK_EQUAL_64(strlen(test_plain_string), x19);
   // x0: 1234, x1: 0x00001234
-  ASSERT_EQUAL_64(25, x20);
+  CHECK_EQUAL_64(25, x20);
   // d0: 1.234000
-  ASSERT_EQUAL_64(13, x21);
+  CHECK_EQUAL_64(13, x21);
   // Test %s: 'This is a substring.'
-  ASSERT_EQUAL_64(32, x22);
+  CHECK_EQUAL_64(32, x22);
   // w3(uint32): 4294967295
   // w4(int32): -1
   // x5(uint64): 18446744073709551615
   // x6(int64): -1
-  ASSERT_EQUAL_64(23 + 14 + 33 + 14, x23);
+  CHECK_EQUAL_64(23 + 14 + 33 + 14, x23);
   // %f: 1.234000
   // %g: 2.345
   // %e: 3.456000e+00
   // %E: 4.567000E+00
-  ASSERT_EQUAL_64(13 + 10 + 17 + 17, x24);
+  CHECK_EQUAL_64(13 + 10 + 17 + 17, x24);
   // 0x89abcdef, 0x123456789abcdef
-  ASSERT_EQUAL_64(30, x25);
+  CHECK_EQUAL_64(30, x25);
   // 42
-  ASSERT_EQUAL_64(3, x26);
+  CHECK_EQUAL_64(3, x26);
   // StackPointer(not csp): 0x00007fb037ae2370, 0x37ae2370
   // Note: This is an example value, but the field width is fixed here so the
   // string length is still predictable.
-  ASSERT_EQUAL_64(54, x27);
+  CHECK_EQUAL_64(54, x27);
   // 3=3, 4=40, 5=500
-  ASSERT_EQUAL_64(17, x28);
+  CHECK_EQUAL_64(17, x28);
   // w3: 4294967295, s1: 1.234000, x5: 18446744073709551615, d3: 3.456000
-  ASSERT_EQUAL_64(69, x29);
+  CHECK_EQUAL_64(69, x29);
 
   TEARDOWN();
 }
 
 
 // This is a V8-specific test.
 static void CopyFieldsHelper(CPURegList temps) {
   static const uint64_t kLiteralBase = 0x0100001000100101UL;
   static const uint64_t src[] = {kLiteralBase * 1,
                                  kLiteralBase * 2,
@@ skipping 76 matching lines @@
   __ Bind(&slow);
   __ Mov(x2, 0xbad);
 
   __ Bind(&end);
   END();
 
   RUN();
 
   if (must_fail) {
     // We tested an invalid conversion. The code must have jump on slow.
-    ASSERT_EQUAL_64(0xbad, x2);
+    CHECK_EQUAL_64(0xbad, x2);
   } else {
     // The conversion is valid, check the result.
     int32_t result = (value >= 0) ? value : -value;
-    ASSERT_EQUAL_64(result, x1);
+    CHECK_EQUAL_64(result, x1);
 
     // Check that we didn't jump on slow.
-    ASSERT_EQUAL_64(0xc001c0de, x2);
+    CHECK_EQUAL_64(0xc001c0de, x2);
   }
 
   TEARDOWN();
 }
 
 
 TEST(smi_abs) {
   INIT_V8();
   // Simple and edge cases.
   DoSmiAbsTest(0);
@@ skipping 26 matching lines @@
   __ B(&end);
 
   __ Bind(&target);
   __ Mov(x0, 0xc001c0de);
 
   __ Bind(&end);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(0xc001c0de, x0);
+  CHECK_EQUAL_64(0xc001c0de, x0);
 
   TEARDOWN();
 }
 
 
 TEST(barriers) {
   // Generate all supported barriers, this is just a smoke test
   INIT_V8();
   SETUP();
 
@@ skipping 50 matching lines @@
 
   TEARDOWN();
 }
 
 
 TEST(process_nan_double) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   double sn = rawbits_to_double(0x7ff5555511111111);
   double qn = rawbits_to_double(0x7ffaaaaa11111111);
-  ASSERT(IsSignallingNaN(sn));
-  ASSERT(IsQuietNaN(qn));
+  DCHECK(IsSignallingNaN(sn));
+  DCHECK(IsQuietNaN(qn));
 
   // The input NaNs after passing through ProcessNaN.
   double sn_proc = rawbits_to_double(0x7ffd555511111111);
   double qn_proc = qn;
-  ASSERT(IsQuietNaN(sn_proc));
-  ASSERT(IsQuietNaN(qn_proc));
+  DCHECK(IsQuietNaN(sn_proc));
+  DCHECK(IsQuietNaN(qn_proc));
 
   SETUP();
   START();
 
   // Execute a number of instructions which all use ProcessNaN, and check that
   // they all handle the NaN correctly.
   __ Fmov(d0, sn);
   __ Fmov(d10, qn);
 
   // Operations that always propagate NaNs unchanged, even signalling NaNs.
@@ skipping 20 matching lines @@
 
   // The behaviour of fcvt is checked in TEST(fcvt_sd).
 
   END();
   RUN();
 
   uint64_t qn_raw = double_to_rawbits(qn);
   uint64_t sn_raw = double_to_rawbits(sn);
 
   //   - Signalling NaN
-  ASSERT_EQUAL_FP64(sn, d1);
-  ASSERT_EQUAL_FP64(rawbits_to_double(sn_raw & ~kDSignMask), d2);
-  ASSERT_EQUAL_FP64(rawbits_to_double(sn_raw ^ kDSignMask), d3);
+  CHECK_EQUAL_FP64(sn, d1);
+  CHECK_EQUAL_FP64(rawbits_to_double(sn_raw & ~kDSignMask), d2);
+  CHECK_EQUAL_FP64(rawbits_to_double(sn_raw ^ kDSignMask), d3);
   //   - Quiet NaN
-  ASSERT_EQUAL_FP64(qn, d11);
-  ASSERT_EQUAL_FP64(rawbits_to_double(qn_raw & ~kDSignMask), d12);
-  ASSERT_EQUAL_FP64(rawbits_to_double(qn_raw ^ kDSignMask), d13);
+  CHECK_EQUAL_FP64(qn, d11);
+  CHECK_EQUAL_FP64(rawbits_to_double(qn_raw & ~kDSignMask), d12);
+  CHECK_EQUAL_FP64(rawbits_to_double(qn_raw ^ kDSignMask), d13);
 
   //   - Signalling NaN
-  ASSERT_EQUAL_FP64(sn_proc, d4);
-  ASSERT_EQUAL_FP64(sn_proc, d5);
-  ASSERT_EQUAL_FP64(sn_proc, d6);
-  ASSERT_EQUAL_FP64(sn_proc, d7);
+  CHECK_EQUAL_FP64(sn_proc, d4);
+  CHECK_EQUAL_FP64(sn_proc, d5);
+  CHECK_EQUAL_FP64(sn_proc, d6);
+  CHECK_EQUAL_FP64(sn_proc, d7);
   //   - Quiet NaN
-  ASSERT_EQUAL_FP64(qn_proc, d14);
-  ASSERT_EQUAL_FP64(qn_proc, d15);
-  ASSERT_EQUAL_FP64(qn_proc, d16);
-  ASSERT_EQUAL_FP64(qn_proc, d17);
+  CHECK_EQUAL_FP64(qn_proc, d14);
+  CHECK_EQUAL_FP64(qn_proc, d15);
+  CHECK_EQUAL_FP64(qn_proc, d16);
+  CHECK_EQUAL_FP64(qn_proc, d17);
 
   TEARDOWN();
 }
 
 
 TEST(process_nan_float) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   float sn = rawbits_to_float(0x7f951111);
   float qn = rawbits_to_float(0x7fea1111);
-  ASSERT(IsSignallingNaN(sn));
-  ASSERT(IsQuietNaN(qn));
+  DCHECK(IsSignallingNaN(sn));
+  DCHECK(IsQuietNaN(qn));
 
   // The input NaNs after passing through ProcessNaN.
   float sn_proc = rawbits_to_float(0x7fd51111);
   float qn_proc = qn;
-  ASSERT(IsQuietNaN(sn_proc));
-  ASSERT(IsQuietNaN(qn_proc));
+  DCHECK(IsQuietNaN(sn_proc));
+  DCHECK(IsQuietNaN(qn_proc));
 
   SETUP();
   START();
 
   // Execute a number of instructions which all use ProcessNaN, and check that
   // they all handle the NaN correctly.
   __ Fmov(s0, sn);
   __ Fmov(s10, qn);
 
   // Operations that always propagate NaNs unchanged, even signalling NaNs.
@@ skipping 20 matching lines @@
 
   // The behaviour of fcvt is checked in TEST(fcvt_sd).
 
   END();
   RUN();
 
   uint32_t qn_raw = float_to_rawbits(qn);
   uint32_t sn_raw = float_to_rawbits(sn);
 
   //   - Signalling NaN
-  ASSERT_EQUAL_FP32(sn, s1);
-  ASSERT_EQUAL_FP32(rawbits_to_float(sn_raw & ~kSSignMask), s2);
-  ASSERT_EQUAL_FP32(rawbits_to_float(sn_raw ^ kSSignMask), s3);
+  CHECK_EQUAL_FP32(sn, s1);
+  CHECK_EQUAL_FP32(rawbits_to_float(sn_raw & ~kSSignMask), s2);
+  CHECK_EQUAL_FP32(rawbits_to_float(sn_raw ^ kSSignMask), s3);
   //   - Quiet NaN
-  ASSERT_EQUAL_FP32(qn, s11);
-  ASSERT_EQUAL_FP32(rawbits_to_float(qn_raw & ~kSSignMask), s12);
-  ASSERT_EQUAL_FP32(rawbits_to_float(qn_raw ^ kSSignMask), s13);
+  CHECK_EQUAL_FP32(qn, s11);
+  CHECK_EQUAL_FP32(rawbits_to_float(qn_raw & ~kSSignMask), s12);
+  CHECK_EQUAL_FP32(rawbits_to_float(qn_raw ^ kSSignMask), s13);
 
   //   - Signalling NaN
-  ASSERT_EQUAL_FP32(sn_proc, s4);
-  ASSERT_EQUAL_FP32(sn_proc, s5);
-  ASSERT_EQUAL_FP32(sn_proc, s6);
-  ASSERT_EQUAL_FP32(sn_proc, s7);
+  CHECK_EQUAL_FP32(sn_proc, s4);
+  CHECK_EQUAL_FP32(sn_proc, s5);
+  CHECK_EQUAL_FP32(sn_proc, s6);
+  CHECK_EQUAL_FP32(sn_proc, s7);
   //   - Quiet NaN
-  ASSERT_EQUAL_FP32(qn_proc, s14);
-  ASSERT_EQUAL_FP32(qn_proc, s15);
-  ASSERT_EQUAL_FP32(qn_proc, s16);
-  ASSERT_EQUAL_FP32(qn_proc, s17);
+  CHECK_EQUAL_FP32(qn_proc, s14);
+  CHECK_EQUAL_FP32(qn_proc, s15);
+  CHECK_EQUAL_FP32(qn_proc, s16);
+  CHECK_EQUAL_FP32(qn_proc, s17);
 
   TEARDOWN();
 }
 
 
 static void ProcessNaNsHelper(double n, double m, double expected) {
-  ASSERT(std::isnan(n) || std::isnan(m));
-  ASSERT(std::isnan(expected));
+  DCHECK(std::isnan(n) || std::isnan(m));
+  DCHECK(std::isnan(expected));
 
   SETUP();
   START();
 
   // Execute a number of instructions which all use ProcessNaNs, and check that
   // they all propagate NaNs correctly.
   __ Fmov(d0, n);
   __ Fmov(d1, m);
 
   __ Fadd(d2, d0, d1);
   __ Fsub(d3, d0, d1);
   __ Fmul(d4, d0, d1);
   __ Fdiv(d5, d0, d1);
   __ Fmax(d6, d0, d1);
   __ Fmin(d7, d0, d1);
 
   END();
   RUN();
 
-  ASSERT_EQUAL_FP64(expected, d2);
-  ASSERT_EQUAL_FP64(expected, d3);
-  ASSERT_EQUAL_FP64(expected, d4);
-  ASSERT_EQUAL_FP64(expected, d5);
-  ASSERT_EQUAL_FP64(expected, d6);
-  ASSERT_EQUAL_FP64(expected, d7);
+  CHECK_EQUAL_FP64(expected, d2);
+  CHECK_EQUAL_FP64(expected, d3);
+  CHECK_EQUAL_FP64(expected, d4);
+  CHECK_EQUAL_FP64(expected, d5);
+  CHECK_EQUAL_FP64(expected, d6);
+  CHECK_EQUAL_FP64(expected, d7);
 
   TEARDOWN();
 }
 
 
 TEST(process_nans_double) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   double sn = rawbits_to_double(0x7ff5555511111111);
   double sm = rawbits_to_double(0x7ff5555522222222);
   double qn = rawbits_to_double(0x7ffaaaaa11111111);
   double qm = rawbits_to_double(0x7ffaaaaa22222222);
-  ASSERT(IsSignallingNaN(sn));
-  ASSERT(IsSignallingNaN(sm));
-  ASSERT(IsQuietNaN(qn));
-  ASSERT(IsQuietNaN(qm));
+  DCHECK(IsSignallingNaN(sn));
+  DCHECK(IsSignallingNaN(sm));
+  DCHECK(IsQuietNaN(qn));
+  DCHECK(IsQuietNaN(qm));
 
   // The input NaNs after passing through ProcessNaN.
   double sn_proc = rawbits_to_double(0x7ffd555511111111);
   double sm_proc = rawbits_to_double(0x7ffd555522222222);
   double qn_proc = qn;
   double qm_proc = qm;
-  ASSERT(IsQuietNaN(sn_proc));
-  ASSERT(IsQuietNaN(sm_proc));
-  ASSERT(IsQuietNaN(qn_proc));
-  ASSERT(IsQuietNaN(qm_proc));
+  DCHECK(IsQuietNaN(sn_proc));
+  DCHECK(IsQuietNaN(sm_proc));
+  DCHECK(IsQuietNaN(qn_proc));
+  DCHECK(IsQuietNaN(qm_proc));
 
   // Quiet NaNs are propagated.
   ProcessNaNsHelper(qn, 0, qn_proc);
   ProcessNaNsHelper(0, qm, qm_proc);
   ProcessNaNsHelper(qn, qm, qn_proc);
 
   // Signalling NaNs are propagated, and made quiet.
   ProcessNaNsHelper(sn, 0, sn_proc);
   ProcessNaNsHelper(0, sm, sm_proc);
   ProcessNaNsHelper(sn, sm, sn_proc);
 
   // Signalling NaNs take precedence over quiet NaNs.
   ProcessNaNsHelper(sn, qm, sn_proc);
   ProcessNaNsHelper(qn, sm, sm_proc);
   ProcessNaNsHelper(sn, sm, sn_proc);
 }
 
 
 static void ProcessNaNsHelper(float n, float m, float expected) {
-  ASSERT(std::isnan(n) || std::isnan(m));
-  ASSERT(std::isnan(expected));
+  DCHECK(std::isnan(n) || std::isnan(m));
+  DCHECK(std::isnan(expected));
 
   SETUP();
   START();
 
   // Execute a number of instructions which all use ProcessNaNs, and check that
   // they all propagate NaNs correctly.
   __ Fmov(s0, n);
   __ Fmov(s1, m);
 
   __ Fadd(s2, s0, s1);
   __ Fsub(s3, s0, s1);
   __ Fmul(s4, s0, s1);
   __ Fdiv(s5, s0, s1);
   __ Fmax(s6, s0, s1);
   __ Fmin(s7, s0, s1);
 
   END();
   RUN();
 
-  ASSERT_EQUAL_FP32(expected, s2);
-  ASSERT_EQUAL_FP32(expected, s3);
-  ASSERT_EQUAL_FP32(expected, s4);
-  ASSERT_EQUAL_FP32(expected, s5);
-  ASSERT_EQUAL_FP32(expected, s6);
-  ASSERT_EQUAL_FP32(expected, s7);
+  CHECK_EQUAL_FP32(expected, s2);
+  CHECK_EQUAL_FP32(expected, s3);
+  CHECK_EQUAL_FP32(expected, s4);
+  CHECK_EQUAL_FP32(expected, s5);
+  CHECK_EQUAL_FP32(expected, s6);
+  CHECK_EQUAL_FP32(expected, s7);
 
   TEARDOWN();
 }
 
 
 TEST(process_nans_float) {
   INIT_V8();
   // Make sure that NaN propagation works correctly.
   float sn = rawbits_to_float(0x7f951111);
   float sm = rawbits_to_float(0x7f952222);
   float qn = rawbits_to_float(0x7fea1111);
   float qm = rawbits_to_float(0x7fea2222);
-  ASSERT(IsSignallingNaN(sn));
-  ASSERT(IsSignallingNaN(sm));
-  ASSERT(IsQuietNaN(qn));
-  ASSERT(IsQuietNaN(qm));
+  DCHECK(IsSignallingNaN(sn));
+  DCHECK(IsSignallingNaN(sm));
+  DCHECK(IsQuietNaN(qn));
+  DCHECK(IsQuietNaN(qm));
 
   // The input NaNs after passing through ProcessNaN.
   float sn_proc = rawbits_to_float(0x7fd51111);
   float sm_proc = rawbits_to_float(0x7fd52222);
   float qn_proc = qn;
   float qm_proc = qm;
-  ASSERT(IsQuietNaN(sn_proc));
-  ASSERT(IsQuietNaN(sm_proc));
-  ASSERT(IsQuietNaN(qn_proc));
-  ASSERT(IsQuietNaN(qm_proc));
+  DCHECK(IsQuietNaN(sn_proc));
+  DCHECK(IsQuietNaN(sm_proc));
+  DCHECK(IsQuietNaN(qn_proc));
+  DCHECK(IsQuietNaN(qm_proc));
 
   // Quiet NaNs are propagated.
   ProcessNaNsHelper(qn, 0, qn_proc);
   ProcessNaNsHelper(0, qm, qm_proc);
   ProcessNaNsHelper(qn, qm, qn_proc);
 
   // Signalling NaNs are propagated, and made quiet.
   ProcessNaNsHelper(sn, 0, sn_proc);
   ProcessNaNsHelper(0, sm, sm_proc);
   ProcessNaNsHelper(sn, sm, sn_proc);
 
   // Signalling NaNs take precedence over quiet NaNs.
   ProcessNaNsHelper(sn, qm, sn_proc);
   ProcessNaNsHelper(qn, sm, sm_proc);
   ProcessNaNsHelper(sn, sm, sn_proc);
 }
 
 
 static void DefaultNaNHelper(float n, float m, float a) {
-  ASSERT(std::isnan(n) || std::isnan(m) || std::isnan(a));
+  DCHECK(std::isnan(n) || std::isnan(m) || std::isnan(a));
 
   bool test_1op = std::isnan(n);
   bool test_2op = std::isnan(n) || std::isnan(m);
 
   SETUP();
   START();
 
   // Enable Default-NaN mode in the FPCR.
   __ Mrs(x0, FPCR);
   __ Orr(x1, x0, DN_mask);
@@ skipping 36 matching lines @@
   __ Fnmsub(s27, s0, s1, s2);
 
   // Restore FPCR.
   __ Msr(FPCR, x0);
 
   END();
   RUN();
 
   if (test_1op) {
     uint32_t n_raw = float_to_rawbits(n);
-    ASSERT_EQUAL_FP32(n, s10);
-    ASSERT_EQUAL_FP32(rawbits_to_float(n_raw & ~kSSignMask), s11);
-    ASSERT_EQUAL_FP32(rawbits_to_float(n_raw ^ kSSignMask), s12);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s13);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s14);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s15);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s16);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d17);
+    CHECK_EQUAL_FP32(n, s10);
+    CHECK_EQUAL_FP32(rawbits_to_float(n_raw & ~kSSignMask), s11);
+    CHECK_EQUAL_FP32(rawbits_to_float(n_raw ^ kSSignMask), s12);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s13);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s14);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s15);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s16);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d17);
   }
 
   if (test_2op) {
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s18);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s19);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s20);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s21);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s22);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s23);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s18);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s19);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s20);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s21);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s22);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s23);
   }
 
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s24);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s25);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s26);
-  ASSERT_EQUAL_FP32(kFP32DefaultNaN, s27);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s24);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s25);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s26);
+  CHECK_EQUAL_FP32(kFP32DefaultNaN, s27);
 
   TEARDOWN();
 }
 
 
 TEST(default_nan_float) {
   INIT_V8();
   float sn = rawbits_to_float(0x7f951111);
   float sm = rawbits_to_float(0x7f952222);
   float sa = rawbits_to_float(0x7f95aaaa);
   float qn = rawbits_to_float(0x7fea1111);
   float qm = rawbits_to_float(0x7fea2222);
   float qa = rawbits_to_float(0x7feaaaaa);
-  ASSERT(IsSignallingNaN(sn));
-  ASSERT(IsSignallingNaN(sm));
-  ASSERT(IsSignallingNaN(sa));
-  ASSERT(IsQuietNaN(qn));
-  ASSERT(IsQuietNaN(qm));
-  ASSERT(IsQuietNaN(qa));
+  DCHECK(IsSignallingNaN(sn));
+  DCHECK(IsSignallingNaN(sm));
+  DCHECK(IsSignallingNaN(sa));
+  DCHECK(IsQuietNaN(qn));
+  DCHECK(IsQuietNaN(qm));
+  DCHECK(IsQuietNaN(qa));
 
   //   - Signalling NaNs
   DefaultNaNHelper(sn, 0.0f, 0.0f);
   DefaultNaNHelper(0.0f, sm, 0.0f);
   DefaultNaNHelper(0.0f, 0.0f, sa);
   DefaultNaNHelper(sn, sm, 0.0f);
   DefaultNaNHelper(0.0f, sm, sa);
   DefaultNaNHelper(sn, 0.0f, sa);
   DefaultNaNHelper(sn, sm, sa);
   //   - Quiet NaNs
   DefaultNaNHelper(qn, 0.0f, 0.0f);
   DefaultNaNHelper(0.0f, qm, 0.0f);
   DefaultNaNHelper(0.0f, 0.0f, qa);
   DefaultNaNHelper(qn, qm, 0.0f);
   DefaultNaNHelper(0.0f, qm, qa);
   DefaultNaNHelper(qn, 0.0f, qa);
   DefaultNaNHelper(qn, qm, qa);
   //   - Mixed NaNs
   DefaultNaNHelper(qn, sm, sa);
   DefaultNaNHelper(sn, qm, sa);
   DefaultNaNHelper(sn, sm, qa);
   DefaultNaNHelper(qn, qm, sa);
   DefaultNaNHelper(sn, qm, qa);
   DefaultNaNHelper(qn, sm, qa);
   DefaultNaNHelper(qn, qm, qa);
 }
 
 
 static void DefaultNaNHelper(double n, double m, double a) {
-  ASSERT(std::isnan(n) || std::isnan(m) || std::isnan(a));
+  DCHECK(std::isnan(n) || std::isnan(m) || std::isnan(a));
 
   bool test_1op = std::isnan(n);
   bool test_2op = std::isnan(n) || std::isnan(m);
 
   SETUP();
   START();
 
   // Enable Default-NaN mode in the FPCR.
   __ Mrs(x0, FPCR);
   __ Orr(x1, x0, DN_mask);
@@ skipping 36 matching lines @@
   __ Fnmsub(d27, d0, d1, d2);
 
   // Restore FPCR.
   __ Msr(FPCR, x0);
 
   END();
   RUN();
 
   if (test_1op) {
     uint64_t n_raw = double_to_rawbits(n);
-    ASSERT_EQUAL_FP64(n, d10);
-    ASSERT_EQUAL_FP64(rawbits_to_double(n_raw & ~kDSignMask), d11);
-    ASSERT_EQUAL_FP64(rawbits_to_double(n_raw ^ kDSignMask), d12);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d13);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d14);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d15);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d16);
-    ASSERT_EQUAL_FP32(kFP32DefaultNaN, s17);
+    CHECK_EQUAL_FP64(n, d10);
+    CHECK_EQUAL_FP64(rawbits_to_double(n_raw & ~kDSignMask), d11);
+    CHECK_EQUAL_FP64(rawbits_to_double(n_raw ^ kDSignMask), d12);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d13);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d14);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d15);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d16);
+    CHECK_EQUAL_FP32(kFP32DefaultNaN, s17);
   }
 
   if (test_2op) {
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d18);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d19);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d20);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d21);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d22);
-    ASSERT_EQUAL_FP64(kFP64DefaultNaN, d23);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d18);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d19);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d20);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d21);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d22);
+    CHECK_EQUAL_FP64(kFP64DefaultNaN, d23);
   }
 
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d24);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d25);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d26);
-  ASSERT_EQUAL_FP64(kFP64DefaultNaN, d27);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d24);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d25);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d26);
+  CHECK_EQUAL_FP64(kFP64DefaultNaN, d27);
 
   TEARDOWN();
 }
 
 
 TEST(default_nan_double) {
   INIT_V8();
   double sn = rawbits_to_double(0x7ff5555511111111);
   double sm = rawbits_to_double(0x7ff5555522222222);
   double sa = rawbits_to_double(0x7ff55555aaaaaaaa);
   double qn = rawbits_to_double(0x7ffaaaaa11111111);
   double qm = rawbits_to_double(0x7ffaaaaa22222222);
   double qa = rawbits_to_double(0x7ffaaaaaaaaaaaaa);
-  ASSERT(IsSignallingNaN(sn));
-  ASSERT(IsSignallingNaN(sm));
-  ASSERT(IsSignallingNaN(sa));
-  ASSERT(IsQuietNaN(qn));
-  ASSERT(IsQuietNaN(qm));
-  ASSERT(IsQuietNaN(qa));
+  DCHECK(IsSignallingNaN(sn));
+  DCHECK(IsSignallingNaN(sm));
+  DCHECK(IsSignallingNaN(sa));
+  DCHECK(IsQuietNaN(qn));
+  DCHECK(IsQuietNaN(qm));
+  DCHECK(IsQuietNaN(qa));
 
   //   - Signalling NaNs
   DefaultNaNHelper(sn, 0.0, 0.0);
   DefaultNaNHelper(0.0, sm, 0.0);
   DefaultNaNHelper(0.0, 0.0, sa);
   DefaultNaNHelper(sn, sm, 0.0);
   DefaultNaNHelper(0.0, sm, sa);
   DefaultNaNHelper(sn, 0.0, sa);
   DefaultNaNHelper(sn, sm, sa);
   //   - Quiet NaNs
@@ skipping 40 matching lines @@
     Assembler::BlockConstPoolScope scope(&masm);
     call_start = buf + __ pc_offset();
     __ Call(buf + function.pos(), RelocInfo::NONE64);
     return_address = buf + __ pc_offset();
   }
   __ Pop(xzr, lr);
   END();
 
   RUN();
 
-  ASSERT_EQUAL_64(1, x0);
+  CHECK_EQUAL_64(1, x0);
 
   // The return_address_from_call_start function doesn't currently encounter any
   // non-relocatable sequences, so we check it here to make sure it works.
   // TODO(jbramley): Once Crankshaft is complete, decide if we need to support
   // non-relocatable calls at all.
   CHECK(return_address ==
         Assembler::return_address_from_call_start(call_start));
 
   TEARDOWN();
 }
@@ skipping 36 matching lines @@
   }
 
   __ Bind(&fail);
   __ Mov(x0, -1);
 
   __ Bind(&done);
 
   END();
   RUN();
 
-  ASSERT_EQUAL_64(0, x0);
-  ASSERT_EQUAL_64(value, x1);
-  ASSERT_EQUAL_64(expected, x10);
-  ASSERT_EQUAL_64(expected, x11);
-  ASSERT_EQUAL_64(expected, x12);
-  ASSERT_EQUAL_64(expected, x13);
+  CHECK_EQUAL_64(0, x0);
+  CHECK_EQUAL_64(value, x1);
+  CHECK_EQUAL_64(expected, x10);
+  CHECK_EQUAL_64(expected, x11);
+  CHECK_EQUAL_64(expected, x12);
+  CHECK_EQUAL_64(expected, x13);
 
   TEARDOWN();
 }
 
 
 static void AbsHelperW(int32_t value) {
   int32_t expected;
 
   SETUP();
   START();
@@ skipping 31 matching lines @@
   }
 
   __ Bind(&fail);
   __ Mov(w0, -1);
 
   __ Bind(&done);
 
   END();
   RUN();
 
-  ASSERT_EQUAL_32(0, w0);
-  ASSERT_EQUAL_32(value, w1);
-  ASSERT_EQUAL_32(expected, w10);
-  ASSERT_EQUAL_32(expected, w11);
-  ASSERT_EQUAL_32(expected, w12);
-  ASSERT_EQUAL_32(expected, w13);
+  CHECK_EQUAL_32(0, w0);
+  CHECK_EQUAL_32(value, w1);
+  CHECK_EQUAL_32(expected, w10);
+  CHECK_EQUAL_32(expected, w11);
+  CHECK_EQUAL_32(expected, w12);
+  CHECK_EQUAL_32(expected, w13);
 
   TEARDOWN();
 }
 
 
 TEST(abs) {
   INIT_V8();
   AbsHelperX(0);
   AbsHelperX(42);
   AbsHelperX(-42);
@@ skipping 37 matching lines @@
   CodeDesc desc;
   masm.GetCode(&desc);
   Handle<Code> code = isolate->factory()->NewCode(desc, 0, masm.CodeObject());
 
   unsigned pool_count = 0;
   int pool_mask = RelocInfo::ModeMask(RelocInfo::CONST_POOL) |
                   RelocInfo::ModeMask(RelocInfo::VENEER_POOL);
   for (RelocIterator it(*code, pool_mask); !it.done(); it.next()) {
     RelocInfo* info = it.rinfo();
     if (RelocInfo::IsConstPool(info->rmode())) {
-      ASSERT(info->data() == constant_pool_size);
+      DCHECK(info->data() == constant_pool_size);
       ++pool_count;
     }
     if (RelocInfo::IsVeneerPool(info->rmode())) {
-      ASSERT(info->data() == veneer_pool_size);
+      DCHECK(info->data() == veneer_pool_size);
       ++pool_count;
     }
   }
 
-  ASSERT(pool_count == 2);
+  DCHECK(pool_count == 2);
 
   TEARDOWN();
 }