Rename ASSERT* to DCHECK*.

src/x64/assembler-x64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_X64
 
 #include "src/macro-assembler.h"
 #include "src/serialize.h"
@@ skipping 39 matching lines @@
   Label check_codesize;
   patcher.masm()->bind(&check_codesize);
 #endif
 
   // Patch the code.
   patcher.masm()->movp(kScratchRegister, reinterpret_cast<void*>(target),
                        Assembler::RelocInfoNone());
   patcher.masm()->call(kScratchRegister);
 
   // Check that the size of the code generated is as expected.
-  ASSERT_EQ(Assembler::kCallSequenceLength,
+  DCHECK_EQ(Assembler::kCallSequenceLength,
             patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
 
   // Add the requested number of int3 instructions after the call.
   for (int i = 0; i < guard_bytes; i++) {
     patcher.masm()->int3();
   }
 }
 
 
 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
@@ skipping 40 matching lines @@
     set_modrm(2, base);
     set_disp32(disp);
   }
 }
 
 
 Operand::Operand(Register base,
                  Register index,
                  ScaleFactor scale,
                  int32_t disp) : rex_(0) {
-  ASSERT(!index.is(rsp));
+  DCHECK(!index.is(rsp));
   len_ = 1;
   set_sib(scale, index, base);
   if (disp == 0 && !base.is(rbp) && !base.is(r13)) {
     // This call to set_modrm doesn't overwrite the REX.B (or REX.X) bits
     // possibly set by set_sib.
     set_modrm(0, rsp);
   } else if (is_int8(disp)) {
     set_modrm(1, rsp);
     set_disp8(disp);
   } else {
     set_modrm(2, rsp);
     set_disp32(disp);
   }
 }
 
 
 Operand::Operand(Register index,
                  ScaleFactor scale,
                  int32_t disp) : rex_(0) {
-  ASSERT(!index.is(rsp));
+  DCHECK(!index.is(rsp));
   len_ = 1;
   set_modrm(0, rsp);
   set_sib(scale, index, rbp);
   set_disp32(disp);
 }
 
 
 Operand::Operand(const Operand& operand, int32_t offset) {
-  ASSERT(operand.len_ >= 1);
+  DCHECK(operand.len_ >= 1);
   // Operand encodes REX ModR/M [SIB] [Disp].
   byte modrm = operand.buf_[0];
-  ASSERT(modrm < 0xC0);  // Disallow mode 3 (register target).
+  DCHECK(modrm < 0xC0);  // Disallow mode 3 (register target).
   bool has_sib = ((modrm & 0x07) == 0x04);
   byte mode = modrm & 0xC0;
   int disp_offset = has_sib ? 2 : 1;
   int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
   // Mode 0 with rbp/r13 as ModR/M or SIB base register always has a 32-bit
   // displacement.
   bool is_baseless = (mode == 0) && (base_reg == 0x05);  // No base or RIP base.
   int32_t disp_value = 0;
   if (mode == 0x80 || is_baseless) {
     // Mode 2 or mode 0 with rbp/r13 as base: Word displacement.
     disp_value = *BitCast<const int32_t*>(&operand.buf_[disp_offset]);
   } else if (mode == 0x40) {
     // Mode 1: Byte displacement.
     disp_value = static_cast<signed char>(operand.buf_[disp_offset]);
   }
 
   // Write new operand with same registers, but with modified displacement.
-  ASSERT(offset >= 0 ? disp_value + offset > disp_value
+  DCHECK(offset >= 0 ? disp_value + offset > disp_value
                      : disp_value + offset < disp_value);  // No overflow.
   disp_value += offset;
   rex_ = operand.rex_;
   if (!is_int8(disp_value) || is_baseless) {
     // Need 32 bits of displacement, mode 2 or mode 1 with register rbp/r13.
     buf_[0] = (modrm & 0x3f) | (is_baseless ? 0x00 : 0x80);
     len_ = disp_offset + 4;
     Memory::int32_at(&buf_[disp_offset]) = disp_value;
   } else if (disp_value != 0 || (base_reg == 0x05)) {
     // Need 8 bits of displacement.
     buf_[0] = (modrm & 0x3f) | 0x40;  // Mode 1.
     len_ = disp_offset + 1;
     buf_[disp_offset] = static_cast<byte>(disp_value);
   } else {
     // Need no displacement.
     buf_[0] = (modrm & 0x3f);  // Mode 0.
     len_ = disp_offset;
   }
   if (has_sib) {
     buf_[1] = operand.buf_[1];
   }
 }
 
 
 bool Operand::AddressUsesRegister(Register reg) const {
   int code = reg.code();
-  ASSERT((buf_[0] & 0xC0) != 0xC0);  // Always a memory operand.
+  DCHECK((buf_[0] & 0xC0) != 0xC0);  // Always a memory operand.
   // Start with only low three bits of base register. Initial decoding doesn't
   // distinguish on the REX.B bit.
   int base_code = buf_[0] & 0x07;
   if (base_code == rsp.code()) {
     // SIB byte present in buf_[1].
     // Check the index register from the SIB byte + REX.X prefix.
     int index_code = ((buf_[1] >> 3) & 0x07) | ((rex_ & 0x02) << 2);
     // Index code (including REX.X) of 0x04 (rsp) means no index register.
     if (index_code != rsp.code() && index_code == code) return true;
     // Add REX.B to get the full base register code.
@@ skipping 36 matching lines @@
 
 #ifdef GENERATED_CODE_COVERAGE
   InitCoverageLog();
 #endif
 }
 
 
 void Assembler::GetCode(CodeDesc* desc) {
   // Finalize code (at this point overflow() may be true, but the gap ensures
   // that we are still not overlapping instructions and relocation info).
-  ASSERT(pc_ <= reloc_info_writer.pos());  // No overlap.
+  DCHECK(pc_ <= reloc_info_writer.pos());  // No overlap.
   // Set up code descriptor.
   desc->buffer = buffer_;
   desc->buffer_size = buffer_size_;
   desc->instr_size = pc_offset();
-  ASSERT(desc->instr_size > 0);  // Zero-size code objects upset the system.
+  DCHECK(desc->instr_size > 0);  // Zero-size code objects upset the system.
   desc->reloc_size =
       static_cast<int>((buffer_ + buffer_size_) - reloc_info_writer.pos());
   desc->origin = this;
 }
 
 
 void Assembler::Align(int m) {
-  ASSERT(IsPowerOf2(m));
+  DCHECK(IsPowerOf2(m));
   int delta = (m - (pc_offset() & (m - 1))) & (m - 1);
   Nop(delta);
 }
 
 
 void Assembler::CodeTargetAlign() {
   Align(16);  // Preferred alignment of jump targets on x64.
 }
 
 
 bool Assembler::IsNop(Address addr) {
   Address a = addr;
   while (*a == 0x66) a++;
   if (*a == 0x90) return true;
   if (a[0] == 0xf && a[1] == 0x1f) return true;
   return false;
 }
 
 
 void Assembler::bind_to(Label* L, int pos) {
-  ASSERT(!L->is_bound());  // Label may only be bound once.
-  ASSERT(0 <= pos && pos <= pc_offset());  // Position must be valid.
+  DCHECK(!L->is_bound());  // Label may only be bound once.
+  DCHECK(0 <= pos && pos <= pc_offset());  // Position must be valid.
   if (L->is_linked()) {
     int current = L->pos();
     int next = long_at(current);
     while (next != current) {
       // Relative address, relative to point after address.
       int imm32 = pos - (current + sizeof(int32_t));
       long_at_put(current, imm32);
       current = next;
       next = long_at(next);
     }
     // Fix up last fixup on linked list.
     int last_imm32 = pos - (current + sizeof(int32_t));
     long_at_put(current, last_imm32);
   }
   while (L->is_near_linked()) {
     int fixup_pos = L->near_link_pos();
     int offset_to_next =
         static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
-    ASSERT(offset_to_next <= 0);
+    DCHECK(offset_to_next <= 0);
     int disp = pos - (fixup_pos + sizeof(int8_t));
     CHECK(is_int8(disp));
     set_byte_at(fixup_pos, disp);
     if (offset_to_next < 0) {
       L->link_to(fixup_pos + offset_to_next, Label::kNear);
     } else {
       L->UnuseNear();
     }
   }
   L->bind_to(pos);
 }
 
 
 void Assembler::bind(Label* L) {
   bind_to(L, pc_offset());
 }
 
 
 void Assembler::GrowBuffer() {
-  ASSERT(buffer_overflow());
+  DCHECK(buffer_overflow());
   if (!own_buffer_) FATAL("external code buffer is too small");
 
   // Compute new buffer size.
   CodeDesc desc;  // the new buffer
   if (buffer_size_ < 4*KB) {
     desc.buffer_size = 4*KB;
   } else {
     desc.buffer_size = 2*buffer_size_;
   }
   // Some internal data structures overflow for very large buffers,
@@ skipping 41 matching lines @@
   for (RelocIterator it(desc); !it.done(); it.next()) {
     RelocInfo::Mode rmode = it.rinfo()->rmode();
     if (rmode == RelocInfo::INTERNAL_REFERENCE) {
       intptr_t* p = reinterpret_cast<intptr_t*>(it.rinfo()->pc());
       if (*p != 0) {  // 0 means uninitialized.
         *p += pc_delta;
       }
     }
   }
 
-  ASSERT(!buffer_overflow());
+  DCHECK(!buffer_overflow());
 }
 
 
 void Assembler::emit_operand(int code, const Operand& adr) {
-  ASSERT(is_uint3(code));
+  DCHECK(is_uint3(code));
   const unsigned length = adr.len_;
-  ASSERT(length > 0);
+  DCHECK(length > 0);
 
   // Emit updated ModR/M byte containing the given register.
-  ASSERT((adr.buf_[0] & 0x38) == 0);
+  DCHECK((adr.buf_[0] & 0x38) == 0);
   pc_[0] = adr.buf_[0] | code << 3;
 
   // Emit the rest of the encoded operand.
   for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
   pc_ += length;
 }
 
 
 // Assembler Instruction implementations.
 
 void Assembler::arithmetic_op(byte opcode,
                               Register reg,
                               const Operand& op,
                               int size) {
   EnsureSpace ensure_space(this);
   emit_rex(reg, op, size);
   emit(opcode);
   emit_operand(reg, op);
 }
 
 
 void Assembler::arithmetic_op(byte opcode,
                               Register reg,
                               Register rm_reg,
                               int size) {
   EnsureSpace ensure_space(this);
-  ASSERT((opcode & 0xC6) == 2);
+  DCHECK((opcode & 0xC6) == 2);
   if (rm_reg.low_bits() == 4)  {  // Forces SIB byte.
     // Swap reg and rm_reg and change opcode operand order.
     emit_rex(rm_reg, reg, size);
     emit(opcode ^ 0x02);
     emit_modrm(rm_reg, reg);
   } else {
     emit_rex(reg, rm_reg, size);
     emit(opcode);
     emit_modrm(reg, rm_reg);
   }
 }
 
 
 void Assembler::arithmetic_op_16(byte opcode, Register reg, Register rm_reg) {
   EnsureSpace ensure_space(this);
-  ASSERT((opcode & 0xC6) == 2);
+  DCHECK((opcode & 0xC6) == 2);
   if (rm_reg.low_bits() == 4) {  // Forces SIB byte.
     // Swap reg and rm_reg and change opcode operand order.
     emit(0x66);
     emit_optional_rex_32(rm_reg, reg);
     emit(opcode ^ 0x02);
     emit_modrm(rm_reg, reg);
   } else {
     emit(0x66);
     emit_optional_rex_32(reg, rm_reg);
     emit(opcode);
@@ skipping 19 matching lines @@
     // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
     emit_rex_32(reg);
   }
   emit(opcode);
   emit_operand(reg, op);
 }
 
 
 void Assembler::arithmetic_op_8(byte opcode, Register reg, Register rm_reg) {
   EnsureSpace ensure_space(this);
-  ASSERT((opcode & 0xC6) == 2);
+  DCHECK((opcode & 0xC6) == 2);
   if (rm_reg.low_bits() == 4)  {  // Forces SIB byte.
     // Swap reg and rm_reg and change opcode operand order.
     if (!rm_reg.is_byte_register() || !reg.is_byte_register()) {
       // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
       emit_rex_32(rm_reg, reg);
     }
     emit(opcode ^ 0x02);
     emit_modrm(rm_reg, reg);
   } else {
     if (!reg.is_byte_register() || !rm_reg.is_byte_register()) {
@@ skipping 81 matching lines @@
     emitw(src.value_);
   }
 }
 
 
 void Assembler::immediate_arithmetic_op_8(byte subcode,
                                           const Operand& dst,
                                           Immediate src) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(dst);
-  ASSERT(is_int8(src.value_) || is_uint8(src.value_));
+  DCHECK(is_int8(src.value_) || is_uint8(src.value_));
   emit(0x80);
   emit_operand(subcode, dst);
   emit(src.value_);
 }
 
 
 void Assembler::immediate_arithmetic_op_8(byte subcode,
                                           Register dst,
                                           Immediate src) {
   EnsureSpace ensure_space(this);
   if (!dst.is_byte_register()) {
     // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
     emit_rex_32(dst);
   }
-  ASSERT(is_int8(src.value_) || is_uint8(src.value_));
+  DCHECK(is_int8(src.value_) || is_uint8(src.value_));
   emit(0x80);
   emit_modrm(subcode, dst);
   emit(src.value_);
 }
 
 
 void Assembler::shift(Register dst,
                       Immediate shift_amount,
                       int subcode,
                       int size) {
   EnsureSpace ensure_space(this);
-  ASSERT(size == kInt64Size ? is_uint6(shift_amount.value_)
+  DCHECK(size == kInt64Size ? is_uint6(shift_amount.value_)
                             : is_uint5(shift_amount.value_));
   if (shift_amount.value_ == 1) {
     emit_rex(dst, size);
     emit(0xD1);
     emit_modrm(subcode, dst);
   } else {
     emit_rex(dst, size);
     emit(0xC1);
     emit_modrm(subcode, dst);
     emit(shift_amount.value_);
@@ skipping 36 matching lines @@
 }
 
 
 void Assembler::call(Label* L) {
   positions_recorder()->WriteRecordedPositions();
   EnsureSpace ensure_space(this);
   // 1110 1000 #32-bit disp.
   emit(0xE8);
   if (L->is_bound()) {
     int offset = L->pos() - pc_offset() - sizeof(int32_t);
-    ASSERT(offset <= 0);
+    DCHECK(offset <= 0);
     emitl(offset);
   } else if (L->is_linked()) {
     emitl(L->pos());
     L->link_to(pc_offset() - sizeof(int32_t));
   } else {
-    ASSERT(L->is_unused());
+    DCHECK(L->is_unused());
     int32_t current = pc_offset();
     emitl(current);
     L->link_to(current);
   }
 }
 
 
 void Assembler::call(Address entry, RelocInfo::Mode rmode) {
-  ASSERT(RelocInfo::IsRuntimeEntry(rmode));
+  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
   positions_recorder()->WriteRecordedPositions();
   EnsureSpace ensure_space(this);
   // 1110 1000 #32-bit disp.
   emit(0xE8);
   emit_runtime_entry(entry, rmode);
 }
 
 
 void Assembler::call(Handle<Code> target,
                      RelocInfo::Mode rmode,
@@ skipping 30 matching lines @@
 // Should only ever be used in Code objects for calls within the
 // same Code object. Should not be used when generating new code (use labels),
 // but only when patching existing code.
 void Assembler::call(Address target) {
   positions_recorder()->WriteRecordedPositions();
   EnsureSpace ensure_space(this);
   // 1110 1000 #32-bit disp.
   emit(0xE8);
   Address source = pc_ + 4;
   intptr_t displacement = target - source;
-  ASSERT(is_int32(displacement));
+  DCHECK(is_int32(displacement));
   emitl(static_cast<int32_t>(displacement));
 }
 
 
 void Assembler::clc() {
   EnsureSpace ensure_space(this);
   emit(0xF8);
 }
 
 
@@ skipping 10 matching lines @@
 
 
 void Assembler::cmovq(Condition cc, Register dst, Register src) {
   if (cc == always) {
     movq(dst, src);
   } else if (cc == never) {
     return;
   }
   // No need to check CpuInfo for CMOV support, it's a required part of the
   // 64-bit architecture.
-  ASSERT(cc >= 0);  // Use mov for unconditional moves.
+  DCHECK(cc >= 0);  // Use mov for unconditional moves.
   EnsureSpace ensure_space(this);
   // Opcode: REX.W 0f 40 + cc /r.
   emit_rex_64(dst, src);
   emit(0x0f);
   emit(0x40 + cc);
   emit_modrm(dst, src);
 }
 
 
 void Assembler::cmovq(Condition cc, Register dst, const Operand& src) {
   if (cc == always) {
     movq(dst, src);
   } else if (cc == never) {
     return;
   }
-  ASSERT(cc >= 0);
+  DCHECK(cc >= 0);
   EnsureSpace ensure_space(this);
   // Opcode: REX.W 0f 40 + cc /r.
   emit_rex_64(dst, src);
   emit(0x0f);
   emit(0x40 + cc);
   emit_operand(dst, src);
 }
 
 
 void Assembler::cmovl(Condition cc, Register dst, Register src) {
   if (cc == always) {
     movl(dst, src);
   } else if (cc == never) {
     return;
   }
-  ASSERT(cc >= 0);
+  DCHECK(cc >= 0);
   EnsureSpace ensure_space(this);
   // Opcode: 0f 40 + cc /r.
   emit_optional_rex_32(dst, src);
   emit(0x0f);
   emit(0x40 + cc);
   emit_modrm(dst, src);
 }
 
 
 void Assembler::cmovl(Condition cc, Register dst, const Operand& src) {
   if (cc == always) {
     movl(dst, src);
   } else if (cc == never) {
     return;
   }
-  ASSERT(cc >= 0);
+  DCHECK(cc >= 0);
   EnsureSpace ensure_space(this);
   // Opcode: 0f 40 + cc /r.
   emit_optional_rex_32(dst, src);
   emit(0x0f);
   emit(0x40 + cc);
   emit_operand(dst, src);
 }
 
 
 void Assembler::cmpb_al(Immediate imm8) {
-  ASSERT(is_int8(imm8.value_) || is_uint8(imm8.value_));
+  DCHECK(is_int8(imm8.value_) || is_uint8(imm8.value_));
   EnsureSpace ensure_space(this);
   emit(0x3c);
   emit(imm8.value_);
 }
 
 
 void Assembler::cpuid() {
   EnsureSpace ensure_space(this);
   emit(0x0F);
   emit(0xA2);
@@ skipping 136 matching lines @@
 
 
 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
   if (cc == always) {
     jmp(L);
     return;
   } else if (cc == never) {
     return;
   }
   EnsureSpace ensure_space(this);
-  ASSERT(is_uint4(cc));
+  DCHECK(is_uint4(cc));
   if (L->is_bound()) {
     const int short_size = 2;
     const int long_size  = 6;
     int offs = L->pos() - pc_offset();
-    ASSERT(offs <= 0);
+    DCHECK(offs <= 0);
     // Determine whether we can use 1-byte offsets for backwards branches,
     // which have a max range of 128 bytes.
 
     // We also need to check predictable_code_size() flag here, because on x64,
     // when the full code generator recompiles code for debugging, some places
     // need to be padded out to a certain size. The debugger is keeping track of
     // how often it did this so that it can adjust return addresses on the
     // stack, but if the size of jump instructions can also change, that's not
     // enough and the calculated offsets would be incorrect.
     if (is_int8(offs - short_size) && !predictable_code_size()) {
       // 0111 tttn #8-bit disp.
       emit(0x70 | cc);
       emit((offs - short_size) & 0xFF);
     } else {
       // 0000 1111 1000 tttn #32-bit disp.
       emit(0x0F);
       emit(0x80 | cc);
       emitl(offs - long_size);
     }
   } else if (distance == Label::kNear) {
     // 0111 tttn #8-bit disp
     emit(0x70 | cc);
     byte disp = 0x00;
     if (L->is_near_linked()) {
       int offset = L->near_link_pos() - pc_offset();
-      ASSERT(is_int8(offset));
+      DCHECK(is_int8(offset));
       disp = static_cast<byte>(offset & 0xFF);
     }
     L->link_to(pc_offset(), Label::kNear);
     emit(disp);
   } else if (L->is_linked()) {
     // 0000 1111 1000 tttn #32-bit disp.
     emit(0x0F);
     emit(0x80 | cc);
     emitl(L->pos());
     L->link_to(pc_offset() - sizeof(int32_t));
   } else {
-    ASSERT(L->is_unused());
+    DCHECK(L->is_unused());
     emit(0x0F);
     emit(0x80 | cc);
     int32_t current = pc_offset();
     emitl(current);
     L->link_to(current);
   }
 }
 
 
 void Assembler::j(Condition cc, Address entry, RelocInfo::Mode rmode) {
-  ASSERT(RelocInfo::IsRuntimeEntry(rmode));
+  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
   EnsureSpace ensure_space(this);
-  ASSERT(is_uint4(cc));
+  DCHECK(is_uint4(cc));
   emit(0x0F);
   emit(0x80 | cc);
   emit_runtime_entry(entry, rmode);
 }
 
 
 void Assembler::j(Condition cc,
                   Handle<Code> target,
                   RelocInfo::Mode rmode) {
   EnsureSpace ensure_space(this);
-  ASSERT(is_uint4(cc));
+  DCHECK(is_uint4(cc));
   // 0000 1111 1000 tttn #32-bit disp.
   emit(0x0F);
   emit(0x80 | cc);
   emit_code_target(target, rmode);
 }
 
 
 void Assembler::jmp(Label* L, Label::Distance distance) {
   EnsureSpace ensure_space(this);
   const int short_size = sizeof(int8_t);
   const int long_size = sizeof(int32_t);
   if (L->is_bound()) {
     int offs = L->pos() - pc_offset() - 1;
-    ASSERT(offs <= 0);
+    DCHECK(offs <= 0);
     if (is_int8(offs - short_size) && !predictable_code_size()) {
       // 1110 1011 #8-bit disp.
       emit(0xEB);
       emit((offs - short_size) & 0xFF);
     } else {
       // 1110 1001 #32-bit disp.
       emit(0xE9);
       emitl(offs - long_size);
     }
   } else if (distance == Label::kNear) {
     emit(0xEB);
     byte disp = 0x00;
     if (L->is_near_linked()) {
       int offset = L->near_link_pos() - pc_offset();
-      ASSERT(is_int8(offset));
+      DCHECK(is_int8(offset));
       disp = static_cast<byte>(offset & 0xFF);
     }
     L->link_to(pc_offset(), Label::kNear);
     emit(disp);
   } else if (L->is_linked()) {
     // 1110 1001 #32-bit disp.
     emit(0xE9);
     emitl(L->pos());
     L->link_to(pc_offset() - long_size);
   } else {
     // 1110 1001 #32-bit disp.
-    ASSERT(L->is_unused());
+    DCHECK(L->is_unused());
     emit(0xE9);
     int32_t current = pc_offset();
     emitl(current);
     L->link_to(current);
   }
 }
 
 
 void Assembler::jmp(Handle<Code> target, RelocInfo::Mode rmode) {
   EnsureSpace ensure_space(this);
   // 1110 1001 #32-bit disp.
   emit(0xE9);
   emit_code_target(target, rmode);
 }
 
 
 void Assembler::jmp(Address entry, RelocInfo::Mode rmode) {
-  ASSERT(RelocInfo::IsRuntimeEntry(rmode));
+  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
   EnsureSpace ensure_space(this);
-  ASSERT(RelocInfo::IsRuntimeEntry(rmode));
+  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
   emit(0xE9);
   emit_runtime_entry(entry, rmode);
 }
 
 
 void Assembler::jmp(Register target) {
   EnsureSpace ensure_space(this);
   // Opcode FF/4 r64.
   emit_optional_rex_32(target);
   emit(0xFF);
@@ skipping 18 matching lines @@
 }
 
 
 void Assembler::load_rax(void* value, RelocInfo::Mode mode) {
   EnsureSpace ensure_space(this);
   if (kPointerSize == kInt64Size) {
     emit(0x48);  // REX.W
     emit(0xA1);
     emitp(value, mode);
   } else {
-    ASSERT(kPointerSize == kInt32Size);
+    DCHECK(kPointerSize == kInt32Size);
     emit(0xA1);
     emitp(value, mode);
     // In 64-bit mode, need to zero extend the operand to 8 bytes.
     // See 2.2.1.4 in Intel64 and IA32 Architectures Software
     // Developer's Manual Volume 2.
     emitl(0);
   }
 }
 
 
@@ skipping 111 matching lines @@
 }
 
 
 void Assembler::emit_mov(Register dst, Immediate value, int size) {
   EnsureSpace ensure_space(this);
   emit_rex(dst, size);
   if (size == kInt64Size) {
     emit(0xC7);
     emit_modrm(0x0, dst);
   } else {
-    ASSERT(size == kInt32Size);
+    DCHECK(size == kInt32Size);
     emit(0xB8 + dst.low_bits());
   }
   emit(value);
 }
 
 
 void Assembler::emit_mov(const Operand& dst, Immediate value, int size) {
   EnsureSpace ensure_space(this);
   emit_rex(dst, size);
   emit(0xC7);
@@ skipping 25 matching lines @@
 
 // Loads the ip-relative location of the src label into the target location
 // (as a 32-bit offset sign extended to 64-bit).
 void Assembler::movl(const Operand& dst, Label* src) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(dst);
   emit(0xC7);
   emit_operand(0, dst);
   if (src->is_bound()) {
     int offset = src->pos() - pc_offset() - sizeof(int32_t);
-    ASSERT(offset <= 0);
+    DCHECK(offset <= 0);
     emitl(offset);
   } else if (src->is_linked()) {
     emitl(src->pos());
     src->link_to(pc_offset() - sizeof(int32_t));
   } else {
-    ASSERT(src->is_unused());
+    DCHECK(src->is_unused());
     int32_t current = pc_offset();
     emitl(current);
     src->link_to(current);
   }
 }
 
 
 void Assembler::movsxbl(Register dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(dst, src);
@@ skipping 292 matching lines @@
 
 
 void Assembler::pushfq() {
   EnsureSpace ensure_space(this);
   emit(0x9C);
 }
 
 
 void Assembler::ret(int imm16) {
   EnsureSpace ensure_space(this);
-  ASSERT(is_uint16(imm16));
+  DCHECK(is_uint16(imm16));
   if (imm16 == 0) {
     emit(0xC3);
   } else {
     emit(0xC2);
     emit(imm16 & 0xFF);
     emit((imm16 >> 8) & 0xFF);
   }
 }
 
 
 void Assembler::setcc(Condition cc, Register reg) {
   if (cc > last_condition) {
     movb(reg, Immediate(cc == always ? 1 : 0));
     return;
   }
   EnsureSpace ensure_space(this);
-  ASSERT(is_uint4(cc));
+  DCHECK(is_uint4(cc));
   if (!reg.is_byte_register()) {  // Use x64 byte registers, where different.
     emit_rex_32(reg);
   }
   emit(0x0F);
   emit(0x90 | cc);
   emit_modrm(0x0, reg);
 }
 
 
 void Assembler::shld(Register dst, Register src) {
@@ skipping 40 matching lines @@
 }
 
 
 void Assembler::store_rax(void* dst, RelocInfo::Mode mode) {
   EnsureSpace ensure_space(this);
   if (kPointerSize == kInt64Size) {
     emit(0x48);  // REX.W
     emit(0xA3);
     emitp(dst, mode);
   } else {
-    ASSERT(kPointerSize == kInt32Size);
+    DCHECK(kPointerSize == kInt32Size);
     emit(0xA3);
     emitp(dst, mode);
     // In 64-bit mode, need to zero extend the operand to 8 bytes.
     // See 2.2.1.4 in Intel64 and IA32 Architectures Software
     // Developer's Manual Volume 2.
     emitl(0);
   }
 }
 
 
@@ skipping 13 matching lines @@
       // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
       emit_rex_32(dst, src);
     }
     emit(0x84);
     emit_modrm(dst, src);
   }
 }
 
 
 void Assembler::testb(Register reg, Immediate mask) {
-  ASSERT(is_int8(mask.value_) || is_uint8(mask.value_));
+  DCHECK(is_int8(mask.value_) || is_uint8(mask.value_));
   EnsureSpace ensure_space(this);
   if (reg.is(rax)) {
     emit(0xA8);
     emit(mask.value_);  // Low byte emitted.
   } else {
     if (!reg.is_byte_register()) {
       // Register is not one of al, bl, cl, dl.  Its encoding needs REX.
       emit_rex_32(reg);
     }
     emit(0xF6);
     emit_modrm(0x0, reg);
     emit(mask.value_);  // Low byte emitted.
   }
 }
 
 
 void Assembler::testb(const Operand& op, Immediate mask) {
-  ASSERT(is_int8(mask.value_) || is_uint8(mask.value_));
+  DCHECK(is_int8(mask.value_) || is_uint8(mask.value_));
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(rax, op);
   emit(0xF6);
   emit_operand(rax, op);  // Operation code 0
   emit(mask.value_);  // Low byte emitted.
 }
 
 
 void Assembler::testb(const Operand& op, Register reg) {
   EnsureSpace ensure_space(this);
@@ skipping 127 matching lines @@
 
 void Assembler::fstp_d(const Operand& adr) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(adr);
   emit(0xDD);
   emit_operand(3, adr);
 }
 
 
 void Assembler::fstp(int index) {
-  ASSERT(is_uint3(index));
+  DCHECK(is_uint3(index));
   EnsureSpace ensure_space(this);
   emit_farith(0xDD, 0xD8, index);
 }
 
 
 void Assembler::fild_s(const Operand& adr) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(adr);
   emit(0xDB);
   emit_operand(0, adr);
@@ skipping 10 matching lines @@
 
 void Assembler::fistp_s(const Operand& adr) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(adr);
   emit(0xDB);
   emit_operand(3, adr);
 }
 
 
 void Assembler::fisttp_s(const Operand& adr) {
-  ASSERT(IsEnabled(SSE3));
+  DCHECK(IsEnabled(SSE3));
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(adr);
   emit(0xDB);
   emit_operand(1, adr);
 }
 
 
 void Assembler::fisttp_d(const Operand& adr) {
-  ASSERT(IsEnabled(SSE3));
+  DCHECK(IsEnabled(SSE3));
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(adr);
   emit(0xDD);
   emit_operand(1, adr);
 }
 
 
 void Assembler::fist_s(const Operand& adr) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(adr);
@@ skipping 232 matching lines @@
 void Assembler::fnclex() {
   EnsureSpace ensure_space(this);
   emit(0xDB);
   emit(0xE2);
 }
 
 
 void Assembler::sahf() {
   // TODO(X64): Test for presence. Not all 64-bit intel CPU's have sahf
   // in 64-bit mode. Test CpuID.
-  ASSERT(IsEnabled(SAHF));
+  DCHECK(IsEnabled(SAHF));
   EnsureSpace ensure_space(this);
   emit(0x9E);
 }
 
 
 void Assembler::emit_farith(int b1, int b2, int i) {
-  ASSERT(is_uint8(b1) && is_uint8(b2));  // wrong opcode
-  ASSERT(is_uint3(i));  // illegal stack offset
+  DCHECK(is_uint8(b1) && is_uint8(b2));  // wrong opcode
+  DCHECK(is_uint3(i));  // illegal stack offset
   emit(b1);
   emit(b2 + i);
 }
 
 
 // SSE operations.
 
 void Assembler::andps(XMMRegister dst, XMMRegister src) {
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(dst, src);
@@ skipping 215 matching lines @@
   EnsureSpace ensure_space(this);
   emit(0xF3);
   emit_rex_64(dst, src);
   emit(0x0F);
   emit(0x6F);
   emit_sse_operand(dst, src);
 }
 
 
 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
-  ASSERT(IsEnabled(SSE4_1));
-  ASSERT(is_uint8(imm8));
+  DCHECK(IsEnabled(SSE4_1));
+  DCHECK(is_uint8(imm8));
   EnsureSpace ensure_space(this);
   emit(0x66);
   emit_optional_rex_32(src, dst);
   emit(0x0F);
   emit(0x3A);
   emit(0x17);
   emit_sse_operand(src, dst);
   emit(imm8);
 }
 
@@ skipping 39 matching lines @@
   } else {
     emit_optional_rex_32(dst, src);
     emit(0x0F);
     emit(0x28);
     emit_sse_operand(dst, src);
   }
 }
 
 
 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
-  ASSERT(is_uint8(imm8));
+  DCHECK(is_uint8(imm8));
   EnsureSpace ensure_space(this);
   emit_optional_rex_32(src, dst);
   emit(0x0F);
   emit(0xC6);
   emit_sse_operand(dst, src);
   emit(imm8);
 }
 
 
 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
@@ skipping 321 matching lines @@
   emit_optional_rex_32(dst, src);
   emit(0x0F);
   emit(0xC2);
   emit_sse_operand(dst, src);
   emit(0x01);  // LT == 1
 }
 
 
 void Assembler::roundsd(XMMRegister dst, XMMRegister src,
                         Assembler::RoundingMode mode) {
-  ASSERT(IsEnabled(SSE4_1));
+  DCHECK(IsEnabled(SSE4_1));
   EnsureSpace ensure_space(this);
   emit(0x66);
   emit_optional_rex_32(dst, src);
   emit(0x0f);
   emit(0x3a);
   emit(0x0b);
   emit_sse_operand(dst, src);
   // Mask precision exeption.
   emit(static_cast<byte>(mode) | 0x8);
 }
@@ skipping 47 matching lines @@
 
 void Assembler::dd(uint32_t data) {
   EnsureSpace ensure_space(this);
   emitl(data);
 }
 
 
 // Relocation information implementations.
 
 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
-  ASSERT(!RelocInfo::IsNone(rmode));
+  DCHECK(!RelocInfo::IsNone(rmode));
   // Don't record external references unless the heap will be serialized.
   if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
       !serializer_enabled() && !emit_debug_code()) {
     return;
   } else if (rmode == RelocInfo::CODE_AGE_SEQUENCE) {
     // Don't record psuedo relocation info for code age sequence mode.
     return;
   }
   RelocInfo rinfo(pc_, rmode, data, NULL);
   reloc_info_writer.Write(&rinfo);
@@ skipping 17 matching lines @@
 void Assembler::RecordComment(const char* msg, bool force) {
   if (FLAG_code_comments || force) {
     EnsureSpace ensure_space(this);
     RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
   }
 }
 
 
 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
   // No out-of-line constant pool support.
-  ASSERT(!FLAG_enable_ool_constant_pool);
+  DCHECK(!FLAG_enable_ool_constant_pool);
   return isolate->factory()->empty_constant_pool_array();
 }
 
 
 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
   // No out-of-line constant pool support.
-  ASSERT(!FLAG_enable_ool_constant_pool);
+  DCHECK(!FLAG_enable_ool_constant_pool);
   return;
 }
 
 
 const int RelocInfo::kApplyMask = RelocInfo::kCodeTargetMask |
     1 << RelocInfo::RUNTIME_ENTRY |
     1 << RelocInfo::INTERNAL_REFERENCE |
     1 << RelocInfo::CODE_AGE_SEQUENCE;
 
 
 bool RelocInfo::IsCodedSpecially() {
   // The deserializer needs to know whether a pointer is specially coded.  Being
   // specially coded on x64 means that it is a relative 32 bit address, as used
   // by branch instructions.
   return (1 << rmode_) & kApplyMask;
 }
 
 
 bool RelocInfo::IsInConstantPool() {
   return false;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_X64