Rename ASSERT* to DCHECK*.

src/mips64/simulator-mips64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #include "src/v8.h"
@@ skipping 106 matching lines @@
 }
 
 
 void MipsDebugger::Stop(Instruction* instr) {
   // Get the stop code.
   uint32_t code = instr->Bits(25, 6);
   // Retrieve the encoded address, which comes just after this stop.
   char** msg_address =
     reinterpret_cast<char**>(sim_->get_pc() + Instr::kInstrSize);
   char* msg = *msg_address;
-  ASSERT(msg != NULL);
+  DCHECK(msg != NULL);
 
   // Update this stop description.
   if (!watched_stops_[code].desc) {
     watched_stops_[code].desc = msg;
   }
 
   if (strlen(msg) > 0) {
     if (coverage_log != NULL) {
       fprintf(coverage_log, "%s\n", str);
       fflush(coverage_log);
@@ skipping 625 matching lines @@
 
 #undef COMMAND_SIZE
 #undef ARG_SIZE
 
 #undef STR
 #undef XSTR
 }
 
 
 static bool ICacheMatch(void* one, void* two) {
-  ASSERT((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
-  ASSERT((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
+  DCHECK((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
+  DCHECK((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
   return one == two;
 }
 
 
 static uint32_t ICacheHash(void* key) {
   return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2;
 }
 
 
 static bool AllOnOnePage(uintptr_t start, int size) {
@@ skipping 16 matching lines @@
   int64_t intra_line = (start & CachePage::kLineMask);
   start -= intra_line;
   size += intra_line;
   size = ((size - 1) | CachePage::kLineMask) + 1;
   int offset = (start & CachePage::kPageMask);
   while (!AllOnOnePage(start, size - 1)) {
     int bytes_to_flush = CachePage::kPageSize - offset;
     FlushOnePage(i_cache, start, bytes_to_flush);
     start += bytes_to_flush;
     size -= bytes_to_flush;
-    ASSERT_EQ((uint64_t)0, start & CachePage::kPageMask);
+    DCHECK_EQ((uint64_t)0, start & CachePage::kPageMask);
     offset = 0;
   }
   if (size != 0) {
     FlushOnePage(i_cache, start, size);
   }
 }
 
 
 CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) {
   v8::internal::HashMap::Entry* entry = i_cache->Lookup(page,
                                                         ICacheHash(page),
                                                         true);
   if (entry->value == NULL) {
     CachePage* new_page = new CachePage();
     entry->value = new_page;
   }
   return reinterpret_cast<CachePage*>(entry->value);
 }
 
 
 // Flush from start up to and not including start + size.
 void Simulator::FlushOnePage(v8::internal::HashMap* i_cache,
                              intptr_t start,
                              int size) {
-  ASSERT(size <= CachePage::kPageSize);
-  ASSERT(AllOnOnePage(start, size - 1));
-  ASSERT((start & CachePage::kLineMask) == 0);
-  ASSERT((size & CachePage::kLineMask) == 0);
+  DCHECK(size <= CachePage::kPageSize);
+  DCHECK(AllOnOnePage(start, size - 1));
+  DCHECK((start & CachePage::kLineMask) == 0);
+  DCHECK((size & CachePage::kLineMask) == 0);
   void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
   int offset = (start & CachePage::kPageMask);
   CachePage* cache_page = GetCachePage(i_cache, page);
   char* valid_bytemap = cache_page->ValidityByte(offset);
   memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
 }
 
 
 void Simulator::CheckICache(v8::internal::HashMap* i_cache,
                             Instruction* instr) {
@@ skipping 139 matching lines @@
                                            ExternalReference::Type type) {
   Redirection* redirection = Redirection::Get(external_function, type);
   return redirection->address_of_swi_instruction();
 }
 
 
 // Get the active Simulator for the current thread.
 Simulator* Simulator::current(Isolate* isolate) {
   v8::internal::Isolate::PerIsolateThreadData* isolate_data =
        isolate->FindOrAllocatePerThreadDataForThisThread();
-  ASSERT(isolate_data != NULL);
-  ASSERT(isolate_data != NULL);
+  DCHECK(isolate_data != NULL);
+  DCHECK(isolate_data != NULL);
 
   Simulator* sim = isolate_data->simulator();
   if (sim == NULL) {
     // TODO(146): delete the simulator object when a thread/isolate goes away.
     sim = new Simulator(isolate);
     isolate_data->set_simulator(sim);
   }
   return sim;
 }
 
 
 // Sets the register in the architecture state. It will also deal with updating
 // Simulator internal state for special registers such as PC.
 void Simulator::set_register(int reg, int64_t value) {
-  ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
+  DCHECK((reg >= 0) && (reg < kNumSimuRegisters));
   if (reg == pc) {
     pc_modified_ = true;
   }
 
   // Zero register always holds 0.
   registers_[reg] = (reg == 0) ? 0 : value;
 }
 
 
 void Simulator::set_dw_register(int reg, const int* dbl) {
-  ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
+  DCHECK((reg >= 0) && (reg < kNumSimuRegisters));
   registers_[reg] = dbl[1];
   registers_[reg] = registers_[reg] << 32;
   registers_[reg] += dbl[0];
 }
 
 
 void Simulator::set_fpu_register(int fpureg, int64_t value) {
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   FPUregisters_[fpureg] = value;
 }
 
 
 void Simulator::set_fpu_register_word(int fpureg, int32_t value) {
   // Set ONLY lower 32-bits, leaving upper bits untouched.
   // TODO(plind): big endian issue.
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   int32_t *pword = reinterpret_cast<int32_t*>(&FPUregisters_[fpureg]);
   *pword = value;
 }
 
 
 void Simulator::set_fpu_register_hi_word(int fpureg, int32_t value) {
   // Set ONLY upper 32-bits, leaving lower bits untouched.
   // TODO(plind): big endian issue.
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   int32_t *phiword = (reinterpret_cast<int32_t*>(&FPUregisters_[fpureg])) + 1;
   *phiword = value;
 }
 
 
 void Simulator::set_fpu_register_float(int fpureg, float value) {
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   *BitCast<float*>(&FPUregisters_[fpureg]) = value;
 }
 
 
 void Simulator::set_fpu_register_double(int fpureg, double value) {
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   *BitCast<double*>(&FPUregisters_[fpureg]) = value;
 }
 
 
 // Get the register from the architecture state. This function does handle
 // the special case of accessing the PC register.
 int64_t Simulator::get_register(int reg) const {
-  ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
+  DCHECK((reg >= 0) && (reg < kNumSimuRegisters));
   if (reg == 0)
     return 0;
   else
     return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0);
 }
 
 
 double Simulator::get_double_from_register_pair(int reg) {
   // TODO(plind): bad ABI stuff, refactor or remove.
-  ASSERT((reg >= 0) && (reg < kNumSimuRegisters) && ((reg % 2) == 0));
+  DCHECK((reg >= 0) && (reg < kNumSimuRegisters) && ((reg % 2) == 0));
 
   double dm_val = 0.0;
   // Read the bits from the unsigned integer register_[] array
   // into the double precision floating point value and return it.
   char buffer[sizeof(registers_[0])];
   memcpy(buffer, &registers_[reg], sizeof(registers_[0]));
   memcpy(&dm_val, buffer, sizeof(registers_[0]));
   return(dm_val);
 }
 
 
 int64_t Simulator::get_fpu_register(int fpureg) const {
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   return FPUregisters_[fpureg];
 }
 
 
 int32_t Simulator::get_fpu_register_word(int fpureg) const {
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff);
 }
 
 
 int32_t Simulator::get_fpu_register_signed_word(int fpureg) const {
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   return static_cast<int32_t>(FPUregisters_[fpureg] & 0xffffffff);
 }
 
 
 uint32_t Simulator::get_fpu_register_hi_word(int fpureg) const {
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   return static_cast<uint32_t>((FPUregisters_[fpureg] >> 32) & 0xffffffff);
 }
 
 
 float Simulator::get_fpu_register_float(int fpureg) const {
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   return *BitCast<float*>(
       const_cast<int64_t*>(&FPUregisters_[fpureg]));
 }
 
 
 double Simulator::get_fpu_register_double(int fpureg) const {
-  ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
+  DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters));
   return *BitCast<double*>(&FPUregisters_[fpureg]);
 }
 
 
 // Runtime FP routines take up to two double arguments and zero
 // or one integer arguments. All are constructed here,
 // from a0-a3 or f12 and f13 (n64), or f14 (O32).
 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) {
   if (!IsMipsSoftFloatABI) {
     const int fparg2 = (kMipsAbi == kN64) ? 13 : 14;
@@ skipping 712 matching lines @@
 
 
 bool Simulator::IsStopInstruction(Instruction* instr) {
   int32_t func = instr->FunctionFieldRaw();
   uint32_t code = static_cast<uint32_t>(instr->Bits(25, 6));
   return (func == BREAK) && code > kMaxWatchpointCode && code <= kMaxStopCode;
 }
 
 
 bool Simulator::IsEnabledStop(uint64_t code) {
-  ASSERT(code <= kMaxStopCode);
-  ASSERT(code > kMaxWatchpointCode);
+  DCHECK(code <= kMaxStopCode);
+  DCHECK(code > kMaxWatchpointCode);
   return !(watched_stops_[code].count & kStopDisabledBit);
 }
 
 
 void Simulator::EnableStop(uint64_t code) {
   if (!IsEnabledStop(code)) {
     watched_stops_[code].count &= ~kStopDisabledBit;
   }
 }
 
 
 void Simulator::DisableStop(uint64_t code) {
   if (IsEnabledStop(code)) {
     watched_stops_[code].count |= kStopDisabledBit;
   }
 }
 
 
 void Simulator::IncreaseStopCounter(uint64_t code) {
-  ASSERT(code <= kMaxStopCode);
+  DCHECK(code <= kMaxStopCode);
   if ((watched_stops_[code].count & ~(1 << 31)) == 0x7fffffff) {
     PrintF("Stop counter for code %ld has overflowed.\n"
            "Enabling this code and reseting the counter to 0.\n", code);
     watched_stops_[code].count = 0;
     EnableStop(code);
   } else {
     watched_stops_[code].count++;
   }
 }
 
@@ skipping 59 matching lines @@
 
   const int32_t  fs_reg = instr->FsValue();
 
 
   // ---------- Configuration.
   switch (op) {
     case COP1:    // Coprocessor instructions.
       switch (instr->RsFieldRaw()) {
         case CFC1:
           // At the moment only FCSR is supported.
-          ASSERT(fs_reg == kFCSRRegister);
+          DCHECK(fs_reg == kFCSRRegister);
           *alu_out = FCSR_;
           break;
         case MFC1:
           *alu_out = static_cast<int64_t>(get_fpu_register_word(fs_reg));
           break;
         case DMFC1:
           *alu_out = get_fpu_register(fs_reg);
           break;
         case MFHC1:
           *alu_out = get_fpu_register_hi_word(fs_reg);
@@ skipping 91 matching lines @@
           }
           break;
         case SRAV:
           *alu_out = (int32_t)rt >> rs;
           break;
         case DSRAV:
           *alu_out = rt >> rs;
           break;
         case MFHI:  // MFHI == CLZ on R6.
           if (kArchVariant != kMips64r6) {
-            ASSERT(instr->SaValue() == 0);
+            DCHECK(instr->SaValue() == 0);
             *alu_out = get_register(HI);
           } else {
             // MIPS spec: If no bits were set in GPR rs, the result written to
             // GPR rd is 32.
             // GCC __builtin_clz: If input is 0, the result is undefined.
-            ASSERT(instr->SaValue() == 1);
+            DCHECK(instr->SaValue() == 1);
             *alu_out =
                 rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u);
           }
           break;
         case MFLO:
           *alu_out = get_register(LO);
           break;
         case MULT:  // MULT == D_MUL_MUH.
           // TODO(plind) - Unify MULT/DMULT with single set of 64-bit HI/Lo
           // regs.
@@ skipping 233 matching lines @@
         case CFC1:
           set_register(rt_reg, alu_out);
           break;
         case MFC1:
         case DMFC1:
         case MFHC1:
           set_register(rt_reg, alu_out);
           break;
         case CTC1:
           // At the moment only FCSR is supported.
-          ASSERT(fs_reg == kFCSRRegister);
+          DCHECK(fs_reg == kFCSRRegister);
           FCSR_ = registers_[rt_reg];
           break;
         case MTC1:
           // Hardware writes upper 32-bits to zero on mtc1.
           set_fpu_register_hi_word(fs_reg, 0);
           set_fpu_register_word(fs_reg, registers_[rt_reg]);
           break;
         case DMTC1:
           set_fpu_register(fs_reg, registers_[rt_reg]);
           break;
@@ skipping 65 matching lines @@
               break;
             case C_OLE_D:
               set_fcsr_bit(fcsr_cc, (fs <= ft));
               break;
             case C_ULE_D:
               set_fcsr_bit(fcsr_cc,
                            (fs <= ft) || (std::isnan(fs) || std::isnan(ft)));
               break;
             case CVT_W_D:   // Convert double to word.
               // Rounding modes are not yet supported.
-              ASSERT((FCSR_ & 3) == 0);
+              DCHECK((FCSR_ & 3) == 0);
               // In rounding mode 0 it should behave like ROUND.
               // No break.
             case ROUND_W_D:  // Round double to word (round half to even).
               {
                 double rounded = std::floor(fs + 0.5);
                 int32_t result = static_cast<int32_t>(rounded);
                 if ((result & 1) != 0 && result - fs == 0.5) {
                   // If the number is halfway between two integers,
                   // round to the even one.
                   result--;
@@ skipping 32 matching lines @@
                 if (set_fcsr_round_error(fs, rounded)) {
                   set_fpu_register(fd_reg, kFPUInvalidResult);
                 }
               }
               break;
             case CVT_S_D:  // Convert double to float (single).
               set_fpu_register_float(fd_reg, static_cast<float>(fs));
               break;
             case CVT_L_D:   // Mips64r2: Truncate double to 64-bit long-word.
               // Rounding modes are not yet supported.
-              ASSERT((FCSR_ & 3) == 0);
+              DCHECK((FCSR_ & 3) == 0);
               // In rounding mode 0 it should behave like ROUND.
               // No break.
             case ROUND_L_D: {  // Mips64r2 instruction.
               // check error cases
               double rounded = fs > 0 ? floor(fs + 0.5) : ceil(fs - 0.5);
               int64_t result = static_cast<int64_t>(rounded);
               set_fpu_register(fd_reg, result);
               if (set_fcsr_round64_error(fs, rounded)) {
                 set_fpu_register(fd_reg, kFPU64InvalidResult);
               }
@@ skipping 867 matching lines @@
 }
 
 
 int64_t Simulator::Call(byte* entry, int argument_count, ...) {
   const int kRegisterPassedArguments = (kMipsAbi == kN64) ? 8 : 4;
   va_list parameters;
   va_start(parameters, argument_count);
   // Set up arguments.
 
   // First four arguments passed in registers in both ABI's.
-  ASSERT(argument_count >= 4);
+  DCHECK(argument_count >= 4);
   set_register(a0, va_arg(parameters, int64_t));
   set_register(a1, va_arg(parameters, int64_t));
   set_register(a2, va_arg(parameters, int64_t));
   set_register(a3, va_arg(parameters, int64_t));
 
   if (kMipsAbi == kN64) {
     // Up to eight arguments passed in registers in N64 ABI.
     // TODO(plind): N64 ABI calls these regs a4 - a7. Clarify this.
     if (argument_count >= 5) set_register(a4, va_arg(parameters, int64_t));
     if (argument_count >= 6) set_register(a5, va_arg(parameters, int64_t));
@@ skipping 32 matching lines @@
 }
 
 
 double Simulator::CallFP(byte* entry, double d0, double d1) {
   if (!IsMipsSoftFloatABI) {
     const FPURegister fparg2 = (kMipsAbi == kN64) ? f13 : f14;
     set_fpu_register_double(f12, d0);
     set_fpu_register_double(fparg2, d1);
   } else {
     int buffer[2];
-    ASSERT(sizeof(buffer[0]) * 2 == sizeof(d0));
+    DCHECK(sizeof(buffer[0]) * 2 == sizeof(d0));
     memcpy(buffer, &d0, sizeof(d0));
     set_dw_register(a0, buffer);
     memcpy(buffer, &d1, sizeof(d1));
     set_dw_register(a2, buffer);
   }
   CallInternal(entry);
   if (!IsMipsSoftFloatABI) {
     return get_fpu_register_double(f0);
   } else {
     return get_double_from_register_pair(v0);
@@ skipping 19 matching lines @@
 }
 
 
 #undef UNSUPPORTED
 
 } }  // namespace v8::internal
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS64