Rename ASSERT* to DCHECK*.

src/mips64/assembler-mips64.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 49 matching lines @@
   // compilation.
 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0
   answer |= 1u << FPU;
 #endif
 
   return answer;
 }
 
 
 const char* DoubleRegister::AllocationIndexToString(int index) {
-  ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
+  DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
   const char* const names[] = {
     "f0",
     "f2",
     "f4",
     "f6",
     "f8",
     "f10",
     "f12",
     "f14",
     "f16",
@@ skipping 24 matching lines @@
   if (cpu.has_fpu()) supported_ |= 1u << FPU;
 #endif
 }
 
 
 void CpuFeatures::PrintTarget() { }
 void CpuFeatures::PrintFeatures() { }
 
 
 int ToNumber(Register reg) {
-  ASSERT(reg.is_valid());
+  DCHECK(reg.is_valid());
   const int kNumbers[] = {
     0,    // zero_reg
     1,    // at
     2,    // v0
     3,    // v1
     4,    // a0
     5,    // a1
     6,    // a2
     7,    // a3
     8,    // a4
@@ skipping 19 matching lines @@
     28,   // gp
     29,   // sp
     30,   // fp
     31,   // ra
   };
   return kNumbers[reg.code()];
 }
 
 
 Register ToRegister(int num) {
-  ASSERT(num >= 0 && num < kNumRegisters);
+  DCHECK(num >= 0 && num < kNumRegisters);
   const Register kRegisters[] = {
     zero_reg,
     at,
     v0, v1,
     a0, a1, a2, a3, a4, a5, a6, a7,
     t0, t1, t2, t3,
     s0, s1, s2, s3, s4, s5, s6, s7,
     t8, t9,
     k0, k1,
     gp,
@@ skipping 49 matching lines @@
 // -----------------------------------------------------------------------------
 // Implementation of Operand and MemOperand.
 // See assembler-mips-inl.h for inlined constructors.
 
 Operand::Operand(Handle<Object> handle) {
   AllowDeferredHandleDereference using_raw_address;
   rm_ = no_reg;
   // Verify all Objects referred by code are NOT in new space.
   Object* obj = *handle;
   if (obj->IsHeapObject()) {
-    ASSERT(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));
+    DCHECK(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));
     imm64_ = reinterpret_cast<intptr_t>(handle.location());
     rmode_ = RelocInfo::EMBEDDED_OBJECT;
   } else {
     // No relocation needed.
     imm64_ = reinterpret_cast<intptr_t>(obj);
     rmode_ = RelocInfo::NONE64;
   }
 }
 
 
@@ skipping 64 matching lines @@
 
   trampoline_emitted_ = FLAG_force_long_branches;
   unbound_labels_count_ = 0;
   block_buffer_growth_ = false;
 
   ClearRecordedAstId();
 }
 
 
 void Assembler::GetCode(CodeDesc* desc) {
-  ASSERT(pc_ <= reloc_info_writer.pos());  // No overlap.
+  DCHECK(pc_ <= reloc_info_writer.pos());  // No overlap.
   // Set up code descriptor.
   desc->buffer = buffer_;
   desc->buffer_size = buffer_size_;
   desc->instr_size = pc_offset();
   desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
   desc->origin = this;
 }
 
 
 void Assembler::Align(int m) {
-  ASSERT(m >= 4 && IsPowerOf2(m));
+  DCHECK(m >= 4 && IsPowerOf2(m));
   while ((pc_offset() & (m - 1)) != 0) {
     nop();
   }
 }
 
 
 void Assembler::CodeTargetAlign() {
   // No advantage to aligning branch/call targets to more than
   // single instruction, that I am aware of.
   Align(4);
@@ skipping 218 matching lines @@
 
 bool Assembler::IsOri(Instr instr) {
   uint32_t opcode = GetOpcodeField(instr);
   // Checks if the instruction is a load upper immediate.
   return opcode == ORI;
 }
 
 
 bool Assembler::IsNop(Instr instr, unsigned int type) {
   // See Assembler::nop(type).
-  ASSERT(type < 32);
+  DCHECK(type < 32);
   uint32_t opcode = GetOpcodeField(instr);
   uint32_t function = GetFunctionField(instr);
   uint32_t rt = GetRt(instr);
   uint32_t rd = GetRd(instr);
   uint32_t sa = GetSa(instr);
 
   // Traditional mips nop == sll(zero_reg, zero_reg, 0)
   // When marking non-zero type, use sll(zero_reg, at, type)
   // to avoid use of mips ssnop and ehb special encodings
   // of the sll instruction.
 
   Register nop_rt_reg = (type == 0) ? zero_reg : at;
   bool ret = (opcode == SPECIAL && function == SLL &&
               rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
               rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) &&
               sa == type);
 
   return ret;
 }
 
 
 int32_t Assembler::GetBranchOffset(Instr instr) {
-  ASSERT(IsBranch(instr));
+  DCHECK(IsBranch(instr));
   return (static_cast<int16_t>(instr & kImm16Mask)) << 2;
 }
 
 
 bool Assembler::IsLw(Instr instr) {
   return ((instr & kOpcodeMask) == LW);
 }
 
 
 int16_t Assembler::GetLwOffset(Instr instr) {
-  ASSERT(IsLw(instr));
+  DCHECK(IsLw(instr));
   return ((instr & kImm16Mask));
 }
 
 
 Instr Assembler::SetLwOffset(Instr instr, int16_t offset) {
-  ASSERT(IsLw(instr));
+  DCHECK(IsLw(instr));
 
   // We actually create a new lw instruction based on the original one.
   Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask)
       | (offset & kImm16Mask);
 
   return temp_instr;
 }
 
 
 bool Assembler::IsSw(Instr instr) {
   return ((instr & kOpcodeMask) == SW);
 }
 
 
 Instr Assembler::SetSwOffset(Instr instr, int16_t offset) {
-  ASSERT(IsSw(instr));
+  DCHECK(IsSw(instr));
   return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
 }
 
 
 bool Assembler::IsAddImmediate(Instr instr) {
   return ((instr & kOpcodeMask) == ADDIU || (instr & kOpcodeMask) == DADDIU);
 }
 
 
 Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) {
-  ASSERT(IsAddImmediate(instr));
+  DCHECK(IsAddImmediate(instr));
   return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
 }
 
 
 bool Assembler::IsAndImmediate(Instr instr) {
   return GetOpcodeField(instr) == ANDI;
 }
 
 
 int64_t Assembler::target_at(int64_t pos) {
   Instr instr = instr_at(pos);
   if ((instr & ~kImm16Mask) == 0) {
     // Emitted label constant, not part of a branch.
     if (instr == 0) {
        return kEndOfChain;
      } else {
        int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
        return (imm18 + pos);
      }
   }
   // Check we have a branch or jump instruction.
-  ASSERT(IsBranch(instr) || IsJ(instr) || IsLui(instr));
+  DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr));
   // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming
   // the compiler uses arithmetic shifts for signed integers.
   if (IsBranch(instr)) {
     int32_t imm18 = ((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
     if (imm18 == kEndOfChain) {
       // EndOfChain sentinel is returned directly, not relative to pc or pos.
       return kEndOfChain;
     } else {
       return pos + kBranchPCOffset + imm18;
     }
   } else if (IsLui(instr)) {
     Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize);
     Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize);
     Instr instr_ori2 = instr_at(pos + 3 * Assembler::kInstrSize);
-    ASSERT(IsOri(instr_ori));
-    ASSERT(IsOri(instr_ori2));
+    DCHECK(IsOri(instr_ori));
+    DCHECK(IsOri(instr_ori2));
 
     // TODO(plind) create named constants for shift values.
     int64_t imm = static_cast<int64_t>(instr_lui & kImm16Mask) << 48;
     imm |= static_cast<int64_t>(instr_ori & kImm16Mask) << 32;
     imm |= static_cast<int64_t>(instr_ori2 & kImm16Mask) << 16;
     // Sign extend address;
     imm >>= 16;
 
     if (imm == kEndOfJumpChain) {
       // EndOfChain sentinel is returned directly, not relative to pc or pos.
       return kEndOfChain;
     } else {
       uint64_t instr_address = reinterpret_cast<int64_t>(buffer_ + pos);
       int64_t delta = instr_address - imm;
-      ASSERT(pos > delta);
+      DCHECK(pos > delta);
       return pos - delta;
     }
   } else {
     int32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2;
     if (imm28 == kEndOfJumpChain) {
       // EndOfChain sentinel is returned directly, not relative to pc or pos.
       return kEndOfChain;
     } else {
       uint64_t instr_address = reinterpret_cast<int64_t>(buffer_ + pos);
       instr_address &= kImm28Mask;
       int64_t delta = instr_address - imm28;
-      ASSERT(pos > delta);
+      DCHECK(pos > delta);
       return pos - delta;
     }
   }
 }
 
 
 void Assembler::target_at_put(int64_t pos, int64_t target_pos) {
   Instr instr = instr_at(pos);
   if ((instr & ~kImm16Mask) == 0) {
-    ASSERT(target_pos == kEndOfChain || target_pos >= 0);
+    DCHECK(target_pos == kEndOfChain || target_pos >= 0);
     // Emitted label constant, not part of a branch.
     // Make label relative to Code* of generated Code object.
     instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
     return;
   }
 
-  ASSERT(IsBranch(instr) || IsJ(instr) || IsLui(instr));
+  DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr));
   if (IsBranch(instr)) {
     int32_t imm18 = target_pos - (pos + kBranchPCOffset);
-    ASSERT((imm18 & 3) == 0);
+    DCHECK((imm18 & 3) == 0);
 
     instr &= ~kImm16Mask;
     int32_t imm16 = imm18 >> 2;
-    ASSERT(is_int16(imm16));
+    DCHECK(is_int16(imm16));
 
     instr_at_put(pos, instr | (imm16 & kImm16Mask));
   } else if (IsLui(instr)) {
     Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize);
     Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize);
     Instr instr_ori2 = instr_at(pos + 3 * Assembler::kInstrSize);
-    ASSERT(IsOri(instr_ori));
-    ASSERT(IsOri(instr_ori2));
+    DCHECK(IsOri(instr_ori));
+    DCHECK(IsOri(instr_ori2));
 
     uint64_t imm = reinterpret_cast<uint64_t>(buffer_) + target_pos;
-    ASSERT((imm & 3) == 0);
+    DCHECK((imm & 3) == 0);
 
     instr_lui &= ~kImm16Mask;
     instr_ori &= ~kImm16Mask;
     instr_ori2 &= ~kImm16Mask;
 
     instr_at_put(pos + 0 * Assembler::kInstrSize,
                  instr_lui | ((imm >> 32) & kImm16Mask));
     instr_at_put(pos + 1 * Assembler::kInstrSize,
                  instr_ori | ((imm >> 16) & kImm16Mask));
     instr_at_put(pos + 3 * Assembler::kInstrSize,
                  instr_ori2 | (imm & kImm16Mask));
   } else {
     uint64_t imm28 = reinterpret_cast<uint64_t>(buffer_) + target_pos;
     imm28 &= kImm28Mask;
-    ASSERT((imm28 & 3) == 0);
+    DCHECK((imm28 & 3) == 0);
 
     instr &= ~kImm26Mask;
     uint32_t imm26 = imm28 >> 2;
-    ASSERT(is_uint26(imm26));
+    DCHECK(is_uint26(imm26));
 
     instr_at_put(pos, instr | (imm26 & kImm26Mask));
   }
 }
 
 
 void Assembler::print(Label* L) {
   if (L->is_unused()) {
     PrintF("unused label\n");
   } else if (L->is_bound()) {
@@ skipping 11 matching lines @@
       }
       next(&l);
     }
   } else {
     PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
   }
 }
 
 
 void Assembler::bind_to(Label* L, int pos) {
-  ASSERT(0 <= pos && pos <= pc_offset());  // Must have valid binding position.
+  DCHECK(0 <= pos && pos <= pc_offset());  // Must have valid binding position.
   int32_t trampoline_pos = kInvalidSlotPos;
   if (L->is_linked() && !trampoline_emitted_) {
     unbound_labels_count_--;
     next_buffer_check_ += kTrampolineSlotsSize;
   }
 
   while (L->is_linked()) {
     int32_t fixup_pos = L->pos();
     int32_t dist = pos - fixup_pos;
     next(L);  // Call next before overwriting link with target at fixup_pos.
     Instr instr = instr_at(fixup_pos);
     if (IsBranch(instr)) {
       if (dist > kMaxBranchOffset) {
         if (trampoline_pos == kInvalidSlotPos) {
           trampoline_pos = get_trampoline_entry(fixup_pos);
           CHECK(trampoline_pos != kInvalidSlotPos);
         }
-        ASSERT((trampoline_pos - fixup_pos) <= kMaxBranchOffset);
+        DCHECK((trampoline_pos - fixup_pos) <= kMaxBranchOffset);
         target_at_put(fixup_pos, trampoline_pos);
         fixup_pos = trampoline_pos;
         dist = pos - fixup_pos;
       }
       target_at_put(fixup_pos, pos);
     } else {
-      ASSERT(IsJ(instr) || IsLui(instr) || IsEmittedConstant(instr));
+      DCHECK(IsJ(instr) || IsLui(instr) || IsEmittedConstant(instr));
       target_at_put(fixup_pos, pos);
     }
   }
   L->bind_to(pos);
 
   // Keep track of the last bound label so we don't eliminate any instructions
   // before a bound label.
   if (pos > last_bound_pos_)
     last_bound_pos_ = pos;
 }
 
 
 void Assembler::bind(Label* L) {
-  ASSERT(!L->is_bound());  // Label can only be bound once.
+  DCHECK(!L->is_bound());  // Label can only be bound once.
   bind_to(L, pc_offset());
 }
 
 
 void Assembler::next(Label* L) {
-  ASSERT(L->is_linked());
+  DCHECK(L->is_linked());
   int link = target_at(L->pos());
   if (link == kEndOfChain) {
     L->Unuse();
   } else {
-    ASSERT(link >= 0);
+    DCHECK(link >= 0);
     L->link_to(link);
   }
 }
 
 
 bool Assembler::is_near(Label* L) {
   if (L->is_bound()) {
     return ((pc_offset() - L->pos()) < kMaxBranchOffset - 4 * kInstrSize);
   }
   return false;
 }
 
 
 // We have to use a temporary register for things that can be relocated even
 // if they can be encoded in the MIPS's 16 bits of immediate-offset instruction
 // space.  There is no guarantee that the relocated location can be similarly
 // encoded.
 bool Assembler::MustUseReg(RelocInfo::Mode rmode) {
   return !RelocInfo::IsNone(rmode);
 }
 
 void Assembler::GenInstrRegister(Opcode opcode,
                                  Register rs,
                                  Register rt,
                                  Register rd,
                                  uint16_t sa,
                                  SecondaryField func) {
-  ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
+  DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
   Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
       | (rd.code() << kRdShift) | (sa << kSaShift) | func;
   emit(instr);
 }
 
 
 void Assembler::GenInstrRegister(Opcode opcode,
                                  Register rs,
                                  Register rt,
                                  uint16_t msb,
                                  uint16_t lsb,
                                  SecondaryField func) {
-  ASSERT(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));
+  DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));
   Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
       | (msb << kRdShift) | (lsb << kSaShift) | func;
   emit(instr);
 }
 
 
 void Assembler::GenInstrRegister(Opcode opcode,
                                  SecondaryField fmt,
                                  FPURegister ft,
                                  FPURegister fs,
                                  FPURegister fd,
                                  SecondaryField func) {
-  ASSERT(fd.is_valid() && fs.is_valid() && ft.is_valid());
+  DCHECK(fd.is_valid() && fs.is_valid() && ft.is_valid());
   Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift)
       | (fd.code() << kFdShift) | func;
   emit(instr);
 }
 
 
 void Assembler::GenInstrRegister(Opcode opcode,
                                  FPURegister fr,
                                  FPURegister ft,
                                  FPURegister fs,
                                  FPURegister fd,
                                  SecondaryField func) {
-  ASSERT(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid());
+  DCHECK(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid());
   Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift)
       | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
   emit(instr);
 }
 
 
 void Assembler::GenInstrRegister(Opcode opcode,
                                  SecondaryField fmt,
                                  Register rt,
                                  FPURegister fs,
                                  FPURegister fd,
                                  SecondaryField func) {
-  ASSERT(fd.is_valid() && fs.is_valid() && rt.is_valid());
+  DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid());
   Instr instr = opcode | fmt | (rt.code() << kRtShift)
       | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
   emit(instr);
 }
 
 
 void Assembler::GenInstrRegister(Opcode opcode,
                                  SecondaryField fmt,
                                  Register rt,
                                  FPUControlRegister fs,
                                  SecondaryField func) {
-  ASSERT(fs.is_valid() && rt.is_valid());
+  DCHECK(fs.is_valid() && rt.is_valid());
   Instr instr =
       opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
   emit(instr);
 }
 
 
 // Instructions with immediate value.
 // Registers are in the order of the instruction encoding, from left to right.
 void Assembler::GenInstrImmediate(Opcode opcode,
                                   Register rs,
                                   Register rt,
                                   int32_t j) {
-  ASSERT(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));
+  DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));
   Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
       | (j & kImm16Mask);
   emit(instr);
 }
 
 
 void Assembler::GenInstrImmediate(Opcode opcode,
                                   Register rs,
                                   SecondaryField SF,
                                   int32_t j) {
-  ASSERT(rs.is_valid() && (is_int16(j) || is_uint16(j)));
+  DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j)));
   Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
   emit(instr);
 }
 
 
 void Assembler::GenInstrImmediate(Opcode opcode,
                                   Register rs,
                                   FPURegister ft,
                                   int32_t j) {
-  ASSERT(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));
+  DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));
   Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift)
       | (j & kImm16Mask);
   emit(instr);
 }
 
 
 void Assembler::GenInstrJump(Opcode opcode,
                              uint32_t address) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
-  ASSERT(is_uint26(address));
+  DCHECK(is_uint26(address));
   Instr instr = opcode | address;
   emit(instr);
   BlockTrampolinePoolFor(1);  // For associated delay slot.
 }
 
 
 // Returns the next free trampoline entry.
 int32_t Assembler::get_trampoline_entry(int32_t pos) {
   int32_t trampoline_entry = kInvalidSlotPos;
   if (!internal_trampoline_exception_) {
@@ skipping 17 matching lines @@
     if (L->is_linked()) {
       target_pos = L->pos();  // L's link.
       L->link_to(pc_offset());
     } else {
       L->link_to(pc_offset());
       return kEndOfJumpChain;
     }
   }
 
   uint64_t imm = reinterpret_cast<uint64_t>(buffer_) + target_pos;
-  ASSERT((imm & 3) == 0);
+  DCHECK((imm & 3) == 0);
 
   return imm;
 }
 
 
 int32_t Assembler::branch_offset(Label* L, bool jump_elimination_allowed) {
   int32_t target_pos;
   if (L->is_bound()) {
     target_pos = L->pos();
   } else {
     if (L->is_linked()) {
       target_pos = L->pos();
       L->link_to(pc_offset());
     } else {
       L->link_to(pc_offset());
       if (!trampoline_emitted_) {
         unbound_labels_count_++;
         next_buffer_check_ -= kTrampolineSlotsSize;
       }
       return kEndOfChain;
     }
   }
 
   int32_t offset = target_pos - (pc_offset() + kBranchPCOffset);
-  ASSERT((offset & 3) == 0);
-  ASSERT(is_int16(offset >> 2));
+  DCHECK((offset & 3) == 0);
+  DCHECK(is_int16(offset >> 2));
 
   return offset;
 }
 
 
 int32_t Assembler::branch_offset_compact(Label* L,
     bool jump_elimination_allowed) {
   int32_t target_pos;
   if (L->is_bound()) {
     target_pos = L->pos();
   } else {
     if (L->is_linked()) {
       target_pos = L->pos();
       L->link_to(pc_offset());
     } else {
       L->link_to(pc_offset());
       if (!trampoline_emitted_) {
         unbound_labels_count_++;
         next_buffer_check_ -= kTrampolineSlotsSize;
       }
       return kEndOfChain;
     }
   }
 
   int32_t offset = target_pos - pc_offset();
-  ASSERT((offset & 3) == 0);
-  ASSERT(is_int16(offset >> 2));
+  DCHECK((offset & 3) == 0);
+  DCHECK(is_int16(offset >> 2));
 
   return offset;
 }
 
 
 int32_t Assembler::branch_offset21(Label* L, bool jump_elimination_allowed) {
   int32_t target_pos;
   if (L->is_bound()) {
     target_pos = L->pos();
   } else {
     if (L->is_linked()) {
       target_pos = L->pos();
       L->link_to(pc_offset());
     } else {
       L->link_to(pc_offset());
       if (!trampoline_emitted_) {
         unbound_labels_count_++;
         next_buffer_check_ -= kTrampolineSlotsSize;
       }
       return kEndOfChain;
     }
   }
 
   int32_t offset = target_pos - (pc_offset() + kBranchPCOffset);
-  ASSERT((offset & 3) == 0);
-  ASSERT(((offset >> 2) & 0xFFE00000) == 0);  // Offset is 21bit width.
+  DCHECK((offset & 3) == 0);
+  DCHECK(((offset >> 2) & 0xFFE00000) == 0);  // Offset is 21bit width.
 
   return offset;
 }
 
 
 int32_t Assembler::branch_offset21_compact(Label* L,
     bool jump_elimination_allowed) {
   int32_t target_pos;
   if (L->is_bound()) {
     target_pos = L->pos();
   } else {
     if (L->is_linked()) {
       target_pos = L->pos();
       L->link_to(pc_offset());
     } else {
       L->link_to(pc_offset());
       if (!trampoline_emitted_) {
         unbound_labels_count_++;
         next_buffer_check_ -= kTrampolineSlotsSize;
       }
       return kEndOfChain;
     }
   }
 
   int32_t offset = target_pos - pc_offset();
-  ASSERT((offset & 3) == 0);
-  ASSERT(((offset >> 2) & 0xFFE00000) == 0);  // Offset is 21bit width.
+  DCHECK((offset & 3) == 0);
+  DCHECK(((offset >> 2) & 0xFFE00000) == 0);  // Offset is 21bit width.
 
   return offset;
 }
 
 
 void Assembler::label_at_put(Label* L, int at_offset) {
   int target_pos;
   if (L->is_bound()) {
     target_pos = L->pos();
     instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
   } else {
     if (L->is_linked()) {
       target_pos = L->pos();  // L's link.
       int32_t imm18 = target_pos - at_offset;
-      ASSERT((imm18 & 3) == 0);
+      DCHECK((imm18 & 3) == 0);
       int32_t imm16 = imm18 >> 2;
-      ASSERT(is_int16(imm16));
+      DCHECK(is_int16(imm16));
       instr_at_put(at_offset, (imm16 & kImm16Mask));
     } else {
       target_pos = kEndOfChain;
       instr_at_put(at_offset, 0);
       if (!trampoline_emitted_) {
         unbound_labels_count_++;
         next_buffer_check_ -= kTrampolineSlotsSize;
       }
     }
     L->link_to(at_offset);
@@ skipping 22 matching lines @@
 
 
 void Assembler::bgez(Register rs, int16_t offset) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   GenInstrImmediate(REGIMM, rs, BGEZ, offset);
   BlockTrampolinePoolFor(1);  // For associated delay slot.
 }
 
 
 void Assembler::bgezc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(BLEZL, rt, rt, offset);
 }
 
 
 void Assembler::bgeuc(Register rs, Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rs.is(zero_reg)));
-  ASSERT(!(rt.is(zero_reg)));
-  ASSERT(rs.code() != rt.code());
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rs.is(zero_reg)));
+  DCHECK(!(rt.is(zero_reg)));
+  DCHECK(rs.code() != rt.code());
   GenInstrImmediate(BLEZ, rs, rt, offset);
 }
 
 
 void Assembler::bgec(Register rs, Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rs.is(zero_reg)));
-  ASSERT(!(rt.is(zero_reg)));
-  ASSERT(rs.code() != rt.code());
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rs.is(zero_reg)));
+  DCHECK(!(rt.is(zero_reg)));
+  DCHECK(rs.code() != rt.code());
   GenInstrImmediate(BLEZL, rs, rt, offset);
 }
 
 
 void Assembler::bgezal(Register rs, int16_t offset) {
-  ASSERT(kArchVariant != kMips64r6 || rs.is(zero_reg));
+  DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg));
   BlockTrampolinePoolScope block_trampoline_pool(this);
   positions_recorder()->WriteRecordedPositions();
   GenInstrImmediate(REGIMM, rs, BGEZAL, offset);
   BlockTrampolinePoolFor(1);  // For associated delay slot.
 }
 
 
 void Assembler::bgtz(Register rs, int16_t offset) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   GenInstrImmediate(BGTZ, rs, zero_reg, offset);
   BlockTrampolinePoolFor(1);  // For associated delay slot.
 }
 
 
 void Assembler::bgtzc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(BGTZL, zero_reg, rt, offset);
 }
 
 
 void Assembler::blez(Register rs, int16_t offset) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   GenInstrImmediate(BLEZ, rs, zero_reg, offset);
   BlockTrampolinePoolFor(1);  // For associated delay slot.
 }
 
 
 void Assembler::blezc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(BLEZL, zero_reg, rt, offset);
 }
 
 
 void Assembler::bltzc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(BGTZL, rt, rt, offset);
 }
 
 
 void Assembler::bltuc(Register rs, Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rs.is(zero_reg)));
-  ASSERT(!(rt.is(zero_reg)));
-  ASSERT(rs.code() != rt.code());
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rs.is(zero_reg)));
+  DCHECK(!(rt.is(zero_reg)));
+  DCHECK(rs.code() != rt.code());
   GenInstrImmediate(BGTZ, rs, rt, offset);
 }
 
 
 void Assembler::bltc(Register rs, Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rs.is(zero_reg)));
-  ASSERT(!(rt.is(zero_reg)));
-  ASSERT(rs.code() != rt.code());
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rs.is(zero_reg)));
+  DCHECK(!(rt.is(zero_reg)));
+  DCHECK(rs.code() != rt.code());
   GenInstrImmediate(BGTZL, rs, rt, offset);
 }
 
 
 void Assembler::bltz(Register rs, int16_t offset) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   GenInstrImmediate(REGIMM, rs, BLTZ, offset);
   BlockTrampolinePoolFor(1);  // For associated delay slot.
 }
 
 
 void Assembler::bltzal(Register rs, int16_t offset) {
-  ASSERT(kArchVariant != kMips64r6 || rs.is(zero_reg));
+  DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg));
   BlockTrampolinePoolScope block_trampoline_pool(this);
   positions_recorder()->WriteRecordedPositions();
   GenInstrImmediate(REGIMM, rs, BLTZAL, offset);
   BlockTrampolinePoolFor(1);  // For associated delay slot.
 }
 
 
 void Assembler::bne(Register rs, Register rt, int16_t offset) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   GenInstrImmediate(BNE, rs, rt, offset);
   BlockTrampolinePoolFor(1);  // For associated delay slot.
 }
 
 
 void Assembler::bovc(Register rs, Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rs.is(zero_reg)));
-  ASSERT(rs.code() >= rt.code());
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rs.is(zero_reg)));
+  DCHECK(rs.code() >= rt.code());
   GenInstrImmediate(ADDI, rs, rt, offset);
 }
 
 
 void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rs.is(zero_reg)));
-  ASSERT(rs.code() >= rt.code());
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rs.is(zero_reg)));
+  DCHECK(rs.code() >= rt.code());
   GenInstrImmediate(DADDI, rs, rt, offset);
 }
 
 
 void Assembler::blezalc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(BLEZ, zero_reg, rt, offset);
 }
 
 
 void Assembler::bgezalc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(BLEZ, rt, rt, offset);
 }
 
 
 void Assembler::bgezall(Register rs, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rs.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rs.is(zero_reg)));
   GenInstrImmediate(REGIMM, rs, BGEZALL, offset);
 }
 
 
 void Assembler::bltzalc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(BGTZ, rt, rt, offset);
 }
 
 
 void Assembler::bgtzalc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(BGTZ, zero_reg, rt, offset);
 }
 
 
 void Assembler::beqzalc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(ADDI, zero_reg, rt, offset);
 }
 
 
 void Assembler::bnezalc(Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rt.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rt.is(zero_reg)));
   GenInstrImmediate(DADDI, zero_reg, rt, offset);
 }
 
 
 void Assembler::beqc(Register rs, Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(rs.code() < rt.code());
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(rs.code() < rt.code());
   GenInstrImmediate(ADDI, rs, rt, offset);
 }
 
 
 void Assembler::beqzc(Register rs, int32_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rs.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rs.is(zero_reg)));
   Instr instr = BEQZC | (rs.code() << kRsShift) | offset;
   emit(instr);
 }
 
 
 void Assembler::bnec(Register rs, Register rt, int16_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(rs.code() < rt.code());
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(rs.code() < rt.code());
   GenInstrImmediate(DADDI, rs, rt, offset);
 }
 
 
 void Assembler::bnezc(Register rs, int32_t offset) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(!(rs.is(zero_reg)));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(!(rs.is(zero_reg)));
   Instr instr = BNEZC | (rs.code() << kRsShift) | offset;
   emit(instr);
 }
 
 
 void Assembler::j(int64_t target) {
 #if DEBUG
   // Get pc of delay slot.
   uint64_t ipc = reinterpret_cast<uint64_t>(pc_ + 1 * kInstrSize);
   bool in_range = (ipc ^ static_cast<uint64_t>(target) >>
                   (kImm26Bits + kImmFieldShift)) == 0;
-  ASSERT(in_range && ((target & 3) == 0));
+  DCHECK(in_range && ((target & 3) == 0));
 #endif
   GenInstrJump(J, target >> 2);
 }
 
 
 void Assembler::jr(Register rs) {
   if (kArchVariant != kMips64r6) {
     BlockTrampolinePoolScope block_trampoline_pool(this);
     if (rs.is(ra)) {
       positions_recorder()->WriteRecordedPositions();
     }
     GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
     BlockTrampolinePoolFor(1);  // For associated delay slot.
   } else {
     jalr(rs, zero_reg);
   }
 }
 
 
 void Assembler::jal(int64_t target) {
 #ifdef DEBUG
   // Get pc of delay slot.
   uint64_t ipc = reinterpret_cast<uint64_t>(pc_ + 1 * kInstrSize);
   bool in_range = (ipc ^ static_cast<uint64_t>(target) >>
                   (kImm26Bits + kImmFieldShift)) == 0;
-  ASSERT(in_range && ((target & 3) == 0));
+  DCHECK(in_range && ((target & 3) == 0));
 #endif
   positions_recorder()->WriteRecordedPositions();
   GenInstrJump(JAL, target >> 2);
 }
 
 
 void Assembler::jalr(Register rs, Register rd) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   positions_recorder()->WriteRecordedPositions();
   GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
@@ skipping 49 matching lines @@
 void Assembler::mul(Register rd, Register rs, Register rt) {
   if (kArchVariant == kMips64r6) {
       GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH);
   } else {
       GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
   }
 }
 
 
 void Assembler::muh(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH);
 }
 
 
 void Assembler::mulu(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U);
 }
 
 
 void Assembler::muhu(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U);
 }
 
 
 void Assembler::dmul(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH);
 }
 
 
 void Assembler::dmuh(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH);
 }
 
 
 void Assembler::dmulu(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH_U);
 }
 
 
 void Assembler::dmuhu(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH_U);
 }
 
 
 void Assembler::mult(Register rs, Register rt) {
-  ASSERT(kArchVariant != kMips64r6);
+  DCHECK(kArchVariant != kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT);
 }
 
 
 void Assembler::multu(Register rs, Register rt) {
-  ASSERT(kArchVariant != kMips64r6);
+  DCHECK(kArchVariant != kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU);
 }
 
 
 void Assembler::daddiu(Register rd, Register rs, int32_t j) {
   GenInstrImmediate(DADDIU, rs, rd, j);
 }
 
 
 void Assembler::div(Register rs, Register rt) {
   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV);
 }
 
 
 void Assembler::div(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD);
 }
 
 
 void Assembler::mod(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD);
 }
 
 
 void Assembler::divu(Register rs, Register rt) {
   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU);
 }
 
 
 void Assembler::divu(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U);
 }
 
 
 void Assembler::modu(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U);
 }
 
 
 void Assembler::daddu(Register rd, Register rs, Register rt) {
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, DADDU);
 }
 
 
 void Assembler::dsubu(Register rd, Register rs, Register rt) {
@@ skipping 10 matching lines @@
   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULTU);
 }
 
 
 void Assembler::ddiv(Register rs, Register rt) {
   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIV);
 }
 
 
 void Assembler::ddiv(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD);
 }
 
 
 void Assembler::dmod(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD);
 }
 
 
 void Assembler::ddivu(Register rs, Register rt) {
   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIVU);
 }
 
 
 void Assembler::ddivu(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U);
 }
 
 
 void Assembler::dmodu(Register rd, Register rs, Register rt) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD_U);
 }
 
 
 // Logical.
 
 void Assembler::and_(Register rd, Register rs, Register rt) {
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
 }
 
 
 void Assembler::andi(Register rt, Register rs, int32_t j) {
-  ASSERT(is_uint16(j));
+  DCHECK(is_uint16(j));
   GenInstrImmediate(ANDI, rs, rt, j);
 }
 
 
 void Assembler::or_(Register rd, Register rs, Register rt) {
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
 }
 
 
 void Assembler::ori(Register rt, Register rs, int32_t j) {
-  ASSERT(is_uint16(j));
+  DCHECK(is_uint16(j));
   GenInstrImmediate(ORI, rs, rt, j);
 }
 
 
 void Assembler::xor_(Register rd, Register rs, Register rt) {
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
 }
 
 
 void Assembler::xori(Register rt, Register rs, int32_t j) {
-  ASSERT(is_uint16(j));
+  DCHECK(is_uint16(j));
   GenInstrImmediate(XORI, rs, rt, j);
 }
 
 
 void Assembler::nor(Register rd, Register rs, Register rt) {
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
 }
 
 
 // Shifts.
 void Assembler::sll(Register rd,
                     Register rt,
                     uint16_t sa,
                     bool coming_from_nop) {
   // Don't allow nop instructions in the form sll zero_reg, zero_reg to be
   // generated using the sll instruction. They must be generated using
   // nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo
   // instructions.
-  ASSERT(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
+  DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
   GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
 }
 
 
 void Assembler::sllv(Register rd, Register rt, Register rs) {
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
 }
 
 
 void Assembler::srl(Register rd, Register rt, uint16_t sa) {
@@ skipping 11 matching lines @@
 }
 
 
 void Assembler::srav(Register rd, Register rt, Register rs) {
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
 }
 
 
 void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
   // Should be called via MacroAssembler::Ror.
-  ASSERT(rd.is_valid() && rt.is_valid() && is_uint5(sa));
-  ASSERT(kArchVariant == kMips64r2);
+  DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
+  DCHECK(kArchVariant == kMips64r2);
   Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift)
       | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
   emit(instr);
 }
 
 
 void Assembler::rotrv(Register rd, Register rt, Register rs) {
   // Should be called via MacroAssembler::Ror.
-  ASSERT(rd.is_valid() && rt.is_valid() && rs.is_valid() );
-  ASSERT(kArchVariant == kMips64r2);
+  DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
+  DCHECK(kArchVariant == kMips64r2);
   Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
      | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
   emit(instr);
 }
 
 
 void Assembler::dsll(Register rd, Register rt, uint16_t sa) {
   GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSLL);
 }
 
 
 void Assembler::dsllv(Register rd, Register rt, Register rs) {
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSLLV);
 }
 
 
 void Assembler::dsrl(Register rd, Register rt, uint16_t sa) {
   GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRL);
 }
 
 
 void Assembler::dsrlv(Register rd, Register rt, Register rs) {
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRLV);
 }
 
 
 void Assembler::drotr(Register rd, Register rt, uint16_t sa) {
-  ASSERT(rd.is_valid() && rt.is_valid() && is_uint5(sa));
+  DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
   Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift)
       | (rd.code() << kRdShift) | (sa << kSaShift) | DSRL;
   emit(instr);
 }
 
 
 void Assembler::drotrv(Register rd, Register rt, Register rs) {
-  ASSERT(rd.is_valid() && rt.is_valid() && rs.is_valid() );
+  DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
   Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
       | (rd.code() << kRdShift) | (1 << kSaShift) | DSRLV;
   emit(instr);
 }
 
 
 void Assembler::dsra(Register rd, Register rt, uint16_t sa) {
   GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRA);
 }
 
@@ skipping 15 matching lines @@
 
 void Assembler::dsra32(Register rd, Register rt, uint16_t sa) {
   GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRA32);
 }
 
 
 // ------------Memory-instructions-------------
 
 // Helper for base-reg + offset, when offset is larger than int16.
 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) {
-  ASSERT(!src.rm().is(at));
-  ASSERT(is_int32(src.offset_));
+  DCHECK(!src.rm().is(at));
+  DCHECK(is_int32(src.offset_));
   daddiu(at, zero_reg, (src.offset_ >> kLuiShift) & kImm16Mask);
   dsll(at, at, kLuiShift);
   ori(at, at, src.offset_ & kImm16Mask);  // Load 32-bit offset.
   daddu(at, at, src.rm());  // Add base register.
 }
 
 
 void Assembler::lb(Register rd, const MemOperand& rs) {
   if (is_int16(rs.offset_)) {
     GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
@@ skipping 98 matching lines @@
   GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
 }
 
 
 void Assembler::swr(Register rd, const MemOperand& rs) {
   GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
 }
 
 
 void Assembler::lui(Register rd, int32_t j) {
-  ASSERT(is_uint16(j));
+  DCHECK(is_uint16(j));
   GenInstrImmediate(LUI, zero_reg, rd, j);
 }
 
 
 void Assembler::aui(Register rs, Register rt, int32_t j) {
   // This instruction uses same opcode as 'lui'. The difference in encoding is
   // 'lui' has zero reg. for rs field.
-  ASSERT(is_uint16(j));
+  DCHECK(is_uint16(j));
   GenInstrImmediate(LUI, rs, rt, j);
 }
 
 
 void Assembler::daui(Register rs, Register rt, int32_t j) {
-  ASSERT(is_uint16(j));
+  DCHECK(is_uint16(j));
   GenInstrImmediate(DAUI, rs, rt, j);
 }
 
 
 void Assembler::dahi(Register rs, int32_t j) {
-  ASSERT(is_uint16(j));
+  DCHECK(is_uint16(j));
   GenInstrImmediate(REGIMM, rs, DAHI, j);
 }
 
 
 void Assembler::dati(Register rs, int32_t j) {
-  ASSERT(is_uint16(j));
+  DCHECK(is_uint16(j));
   GenInstrImmediate(REGIMM, rs, DATI, j);
 }
 
 
 void Assembler::ldl(Register rd, const MemOperand& rs) {
   GenInstrImmediate(LDL, rs.rm(), rd, rs.offset_);
 }
 
 
 void Assembler::ldr(Register rd, const MemOperand& rs) {
@@ skipping 28 matching lines @@
     LoadRegPlusOffsetToAt(rs);
     GenInstrImmediate(SD, at, rd, 0);  // Equiv to sw(rd, MemOperand(at, 0));
   }
 }
 
 
 // -------------Misc-instructions--------------
 
 // Break / Trap instructions.
 void Assembler::break_(uint32_t code, bool break_as_stop) {
-  ASSERT((code & ~0xfffff) == 0);
+  DCHECK((code & ~0xfffff) == 0);
   // We need to invalidate breaks that could be stops as well because the
   // simulator expects a char pointer after the stop instruction.
   // See constants-mips.h for explanation.
-  ASSERT((break_as_stop &&
+  DCHECK((break_as_stop &&
           code <= kMaxStopCode &&
           code > kMaxWatchpointCode) ||
          (!break_as_stop &&
           (code > kMaxStopCode ||
            code <= kMaxWatchpointCode)));
   Instr break_instr = SPECIAL | BREAK | (code << 6);
   emit(break_instr);
 }
 
 
 void Assembler::stop(const char* msg, uint32_t code) {
-  ASSERT(code > kMaxWatchpointCode);
-  ASSERT(code <= kMaxStopCode);
+  DCHECK(code > kMaxWatchpointCode);
+  DCHECK(code <= kMaxStopCode);
 #if defined(V8_HOST_ARCH_MIPS) || defined(V8_HOST_ARCH_MIPS64)
   break_(0x54321);
 #else  // V8_HOST_ARCH_MIPS
   BlockTrampolinePoolFor(3);
   // The Simulator will handle the stop instruction and get the message address.
   // On MIPS stop() is just a special kind of break_().
   break_(code, true);
   emit(reinterpret_cast<uint64_t>(msg));
 #endif
 }
 
 
 void Assembler::tge(Register rs, Register rt, uint16_t code) {
-  ASSERT(is_uint10(code));
+  DCHECK(is_uint10(code));
   Instr instr = SPECIAL | TGE | rs.code() << kRsShift
       | rt.code() << kRtShift | code << 6;
   emit(instr);
 }
 
 
 void Assembler::tgeu(Register rs, Register rt, uint16_t code) {
-  ASSERT(is_uint10(code));
+  DCHECK(is_uint10(code));
   Instr instr = SPECIAL | TGEU | rs.code() << kRsShift
       | rt.code() << kRtShift | code << 6;
   emit(instr);
 }
 
 
 void Assembler::tlt(Register rs, Register rt, uint16_t code) {
-  ASSERT(is_uint10(code));
+  DCHECK(is_uint10(code));
   Instr instr =
       SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
   emit(instr);
 }
 
 
 void Assembler::tltu(Register rs, Register rt, uint16_t code) {
-  ASSERT(is_uint10(code));
+  DCHECK(is_uint10(code));
   Instr instr =
       SPECIAL | TLTU | rs.code() << kRsShift
       | rt.code() << kRtShift | code << 6;
   emit(instr);
 }
 
 
 void Assembler::teq(Register rs, Register rt, uint16_t code) {
-  ASSERT(is_uint10(code));
+  DCHECK(is_uint10(code));
   Instr instr =
       SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
   emit(instr);
 }
 
 
 void Assembler::tne(Register rs, Register rt, uint16_t code) {
-  ASSERT(is_uint10(code));
+  DCHECK(is_uint10(code));
   Instr instr =
       SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
   emit(instr);
 }
 
 
 // Move from HI/LO register.
 
 void Assembler::mfhi(Register rd) {
   GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
@@ skipping 46 matching lines @@
 
 void Assembler::movf(Register rd, Register rs, uint16_t cc) {
   Register rt;
   rt.code_ = (cc & 0x0007) << 2 | 0;
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
 }
 
 
 void Assembler::sel(SecondaryField fmt, FPURegister fd,
     FPURegister ft, FPURegister fs, uint8_t sel) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(fmt == D);
-  ASSERT(fmt == S);
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(fmt == D);
+  DCHECK(fmt == S);
 
   Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift |
       fs.code() << kFsShift | fd.code() << kFdShift | SEL;
   emit(instr);
 }
 
 
 // GPR.
 void Assembler::seleqz(Register rs, Register rt, Register rd) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S);
 }
 
 
 // FPR.
 void Assembler::seleqz(SecondaryField fmt, FPURegister fd,
     FPURegister ft, FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(fmt == D);
-  ASSERT(fmt == S);
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(fmt == D);
+  DCHECK(fmt == S);
 
   Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift |
       fs.code() << kFsShift | fd.code() << kFdShift | SELEQZ_C;
   emit(instr);
 }
 
 
 // GPR.
 void Assembler::selnez(Register rs, Register rt, Register rd) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S);
 }
 
 
 // FPR.
 void Assembler::selnez(SecondaryField fmt, FPURegister fd,
     FPURegister ft, FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT(fmt == D);
-  ASSERT(fmt == S);
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK(fmt == D);
+  DCHECK(fmt == S);
 
   Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift |
       fs.code() << kFsShift | fd.code() << kFdShift | SELNEZ_C;
   emit(instr);
 }
 
 
 // Bit twiddling.
 void Assembler::clz(Register rd, Register rs) {
   if (kArchVariant != kMips64r6) {
     // Clz instr requires same GPR number in 'rd' and 'rt' fields.
     GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
   } else {
     GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6);
   }
 }
 
 
 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) {
   // Should be called via MacroAssembler::Ins.
   // Ins instr has 'rt' field as dest, and two uint5: msb, lsb.
-  ASSERT((kArchVariant == kMips64r2) || (kArchVariant == kMips64r6));
+  DCHECK((kArchVariant == kMips64r2) || (kArchVariant == kMips64r6));
   GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS);
 }
 
 
 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
   // Should be called via MacroAssembler::Ext.
   // Ext instr has 'rt' field as dest, and two uint5: msb, lsb.
-  ASSERT(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
   GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);
 }
 
 
 void Assembler::pref(int32_t hint, const MemOperand& rs) {
-  ASSERT(is_uint5(hint) && is_uint16(rs.offset_));
+  DCHECK(is_uint5(hint) && is_uint16(rs.offset_));
   Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift)
       | (rs.offset_);
   emit(instr);
 }
 
 
 // --------Coprocessor-instructions----------------
 
 // Load, store, move.
 void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
@@ skipping 159 matching lines @@
   GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S);
 }
 
 
 void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) {
   GenInstrRegister(COP1, D, f0, fs, fd, CEIL_W_D);
 }
 
 
 void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r2);
+  DCHECK(kArchVariant == kMips64r2);
   GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S);
 }
 
 
 void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r2);
+  DCHECK(kArchVariant == kMips64r2);
   GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D);
 }
 
 
 void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r2);
+  DCHECK(kArchVariant == kMips64r2);
   GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S);
 }
 
 
 void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r2);
+  DCHECK(kArchVariant == kMips64r2);
   GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D);
 }
 
 
 void Assembler::round_l_s(FPURegister fd, FPURegister fs) {
   GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S);
 }
 
 
 void Assembler::round_l_d(FPURegister fd, FPURegister fs) {
@@ skipping 16 matching lines @@
 }
 
 
 void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) {
   GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D);
 }
 
 
 void Assembler::min(SecondaryField fmt, FPURegister fd, FPURegister ft,
     FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT((fmt == D) || (fmt == S));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK((fmt == D) || (fmt == S));
   GenInstrRegister(COP1, fmt, ft, fs, fd, MIN);
 }
 
 
 void Assembler::mina(SecondaryField fmt, FPURegister fd, FPURegister ft,
     FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT((fmt == D) || (fmt == S));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK((fmt == D) || (fmt == S));
   GenInstrRegister(COP1, fmt, ft, fs, fd, MINA);
 }
 
 
 void Assembler::max(SecondaryField fmt, FPURegister fd, FPURegister ft,
     FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT((fmt == D) || (fmt == S));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK((fmt == D) || (fmt == S));
   GenInstrRegister(COP1, fmt, ft, fs, fd, MAX);
 }
 
 
 void Assembler::maxa(SecondaryField fmt, FPURegister fd, FPURegister ft,
     FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT((fmt == D) || (fmt == S));
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK((fmt == D) || (fmt == S));
   GenInstrRegister(COP1, fmt, ft, fs, fd, MAXA);
 }
 
 
 void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) {
   GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W);
 }
 
 
 void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r2);
+  DCHECK(kArchVariant == kMips64r2);
   GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L);
 }
 
 
 void Assembler::cvt_s_d(FPURegister fd, FPURegister fs) {
   GenInstrRegister(COP1, D, f0, fs, fd, CVT_S_D);
 }
 
 
 void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) {
   GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W);
 }
 
 
 void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) {
-  ASSERT(kArchVariant == kMips64r2);
+  DCHECK(kArchVariant == kMips64r2);
   GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L);
 }
 
 
 void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) {
   GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S);
 }
 
 
 // Conditions for >= MIPSr6.
 void Assembler::cmp(FPUCondition cond, SecondaryField fmt,
     FPURegister fd, FPURegister fs, FPURegister ft) {
-  ASSERT(kArchVariant == kMips64r6);
-  ASSERT((fmt & ~(31 << kRsShift)) == 0);
+  DCHECK(kArchVariant == kMips64r6);
+  DCHECK((fmt & ~(31 << kRsShift)) == 0);
   Instr instr = COP1 | fmt | ft.code() << kFtShift |
       fs.code() << kFsShift | fd.code() << kFdShift | (0 << 5) | cond;
   emit(instr);
 }
 
 
 void Assembler::bc1eqz(int16_t offset, FPURegister ft) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask);
   emit(instr);
 }
 
 
 void Assembler::bc1nez(int16_t offset, FPURegister ft) {
-  ASSERT(kArchVariant == kMips64r6);
+  DCHECK(kArchVariant == kMips64r6);
   Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask);
   emit(instr);
 }
 
 
 // Conditions for < MIPSr6.
 void Assembler::c(FPUCondition cond, SecondaryField fmt,
     FPURegister fs, FPURegister ft, uint16_t cc) {
-  ASSERT(kArchVariant != kMips64r6);
-  ASSERT(is_uint3(cc));
-  ASSERT((fmt & ~(31 << kRsShift)) == 0);
+  DCHECK(kArchVariant != kMips64r6);
+  DCHECK(is_uint3(cc));
+  DCHECK((fmt & ~(31 << kRsShift)) == 0);
   Instr instr = COP1 | fmt | ft.code() << kFtShift | fs.code() << kFsShift
       | cc << 8 | 3 << 4 | cond;
   emit(instr);
 }
 
 
 void Assembler::fcmp(FPURegister src1, const double src2,
       FPUCondition cond) {
-  ASSERT(src2 == 0.0);
+  DCHECK(src2 == 0.0);
   mtc1(zero_reg, f14);
   cvt_d_w(f14, f14);
   c(cond, D, src1, f14, 0);
 }
 
 
 void Assembler::bc1f(int16_t offset, uint16_t cc) {
-  ASSERT(is_uint3(cc));
+  DCHECK(is_uint3(cc));
   Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask);
   emit(instr);
 }
 
 
 void Assembler::bc1t(int16_t offset, uint16_t cc) {
-  ASSERT(is_uint3(cc));
+  DCHECK(is_uint3(cc));
   Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask);
   emit(instr);
 }
 
 
 // Debugging.
 void Assembler::RecordJSReturn() {
   positions_recorder()->WriteRecordedPositions();
   CheckBuffer();
   RecordRelocInfo(RelocInfo::JS_RETURN);
@@ skipping 10 matching lines @@
 void Assembler::RecordComment(const char* msg) {
   if (FLAG_code_comments) {
     CheckBuffer();
     RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
   }
 }
 
 
 int Assembler::RelocateInternalReference(byte* pc, intptr_t pc_delta) {
   Instr instr = instr_at(pc);
-  ASSERT(IsJ(instr) || IsLui(instr));
+  DCHECK(IsJ(instr) || IsLui(instr));
   if (IsLui(instr)) {
     Instr instr_lui = instr_at(pc + 0 * Assembler::kInstrSize);
     Instr instr_ori = instr_at(pc + 1 * Assembler::kInstrSize);
     Instr instr_ori2 = instr_at(pc + 3 * Assembler::kInstrSize);
-    ASSERT(IsOri(instr_ori));
-    ASSERT(IsOri(instr_ori2));
+    DCHECK(IsOri(instr_ori));
+    DCHECK(IsOri(instr_ori2));
     // TODO(plind): symbolic names for the shifts.
     int64_t imm = (instr_lui & static_cast<int64_t>(kImm16Mask)) << 48;
     imm |= (instr_ori & static_cast<int64_t>(kImm16Mask)) << 32;
     imm |= (instr_ori2 & static_cast<int64_t>(kImm16Mask)) << 16;
     // Sign extend address.
     imm >>= 16;
 
     if (imm == kEndOfJumpChain) {
       return 0;  // Number of instructions patched.
     }
     imm += pc_delta;
-    ASSERT((imm & 3) == 0);
+    DCHECK((imm & 3) == 0);
 
     instr_lui &= ~kImm16Mask;
     instr_ori &= ~kImm16Mask;
     instr_ori2 &= ~kImm16Mask;
 
     instr_at_put(pc + 0 * Assembler::kInstrSize,
                  instr_lui | ((imm >> 32) & kImm16Mask));
     instr_at_put(pc + 1 * Assembler::kInstrSize,
                  instr_ori | (imm >> 16 & kImm16Mask));
     instr_at_put(pc + 3 * Assembler::kInstrSize,
                  instr_ori2 | (imm & kImm16Mask));
     return 4;  // Number of instructions patched.
   } else {
     uint32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2;
     if (static_cast<int32_t>(imm28) == kEndOfJumpChain) {
       return 0;  // Number of instructions patched.
     }
 
     imm28 += pc_delta;
     imm28 &= kImm28Mask;
-    ASSERT((imm28 & 3) == 0);
+    DCHECK((imm28 & 3) == 0);
 
     instr &= ~kImm26Mask;
     uint32_t imm26 = imm28 >> 2;
-    ASSERT(is_uint26(imm26));
+    DCHECK(is_uint26(imm26));
 
     instr_at_put(pc, instr | (imm26 & kImm26Mask));
     return 1;  // Number of instructions patched.
   }
 }
 
 
 void Assembler::GrowBuffer() {
   if (!own_buffer_) FATAL("external code buffer is too small");
 
@@ skipping 32 matching lines @@
 
   // Relocate runtime entries.
   for (RelocIterator it(desc); !it.done(); it.next()) {
     RelocInfo::Mode rmode = it.rinfo()->rmode();
     if (rmode == RelocInfo::INTERNAL_REFERENCE) {
       byte* p = reinterpret_cast<byte*>(it.rinfo()->pc());
       RelocateInternalReference(p, pc_delta);
     }
   }
 
-  ASSERT(!overflow());
+  DCHECK(!overflow());
 }
 
 
 void Assembler::db(uint8_t data) {
   CheckBuffer();
   *reinterpret_cast<uint8_t*>(pc_) = data;
   pc_ += sizeof(uint8_t);
 }
 
 
@@ skipping 10 matching lines @@
       reinterpret_cast<uint64_t>(stub->instruction_start());
   pc_ += sizeof(uint64_t);
 }
 
 
 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
   // We do not try to reuse pool constants.
   RelocInfo rinfo(pc_, rmode, data, NULL);
   if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) {
     // Adjust code for new modes.
-    ASSERT(RelocInfo::IsDebugBreakSlot(rmode)
+    DCHECK(RelocInfo::IsDebugBreakSlot(rmode)
            || RelocInfo::IsJSReturn(rmode)
            || RelocInfo::IsComment(rmode)
            || RelocInfo::IsPosition(rmode));
     // These modes do not need an entry in the constant pool.
   }
   if (!RelocInfo::IsNone(rinfo.rmode())) {
     // Don't record external references unless the heap will be serialized.
     if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
         !serializer_enabled() && !emit_debug_code()) {
       return;
     }
-    ASSERT(buffer_space() >= kMaxRelocSize);  // Too late to grow buffer here.
+    DCHECK(buffer_space() >= kMaxRelocSize);  // Too late to grow buffer here.
     if (rmode == RelocInfo::CODE_TARGET_WITH_ID) {
       RelocInfo reloc_info_with_ast_id(pc_,
                                        rmode,
                                        RecordedAstId().ToInt(),
                                        NULL);
       ClearRecordedAstId();
       reloc_info_writer.Write(&reloc_info_with_ast_id);
     } else {
       reloc_info_writer.Write(&rinfo);
     }
@@ skipping 17 matching lines @@
     // Emission is currently blocked; make sure we try again as soon as
     // possible.
     if (trampoline_pool_blocked_nesting_ > 0) {
       next_buffer_check_ = pc_offset() + kInstrSize;
     } else {
       next_buffer_check_ = no_trampoline_pool_before_;
     }
     return;
   }
 
-  ASSERT(!trampoline_emitted_);
-  ASSERT(unbound_labels_count_ >= 0);
+  DCHECK(!trampoline_emitted_);
+  DCHECK(unbound_labels_count_ >= 0);
   if (unbound_labels_count_ > 0) {
     // First we emit jump (2 instructions), then we emit trampoline pool.
     { BlockTrampolinePoolScope block_trampoline_pool(this);
       Label after_pool;
       b(&after_pool);
       nop();
 
       int pool_start = pc_offset();
       for (int i = 0; i < unbound_labels_count_; i++) {
         uint64_t imm64;
@@ skipping 120 matching lines @@
   // Jump to label may follow at pc + 2 * kInstrSize.
   uint32_t* p = reinterpret_cast<uint32_t*>(pc);
 #ifdef DEBUG
   Instr instr1 = instr_at(pc);
 #endif
   Instr instr2 = instr_at(pc + 1 * kInstrSize);
   Instr instr3 = instr_at(pc + 6 * kInstrSize);
   bool patched = false;
 
   if (IsJal(instr3)) {
-    ASSERT(GetOpcodeField(instr1) == LUI);
-    ASSERT(GetOpcodeField(instr2) == ORI);
+    DCHECK(GetOpcodeField(instr1) == LUI);
+    DCHECK(GetOpcodeField(instr2) == ORI);
 
     uint32_t rs_field = GetRt(instr2) << kRsShift;
     uint32_t rd_field = ra.code() << kRdShift;  // Return-address (ra) reg.
     *(p+6) = SPECIAL | rs_field | rd_field | JALR;
     patched = true;
   } else if (IsJ(instr3)) {
-    ASSERT(GetOpcodeField(instr1) == LUI);
-    ASSERT(GetOpcodeField(instr2) == ORI);
+    DCHECK(GetOpcodeField(instr1) == LUI);
+    DCHECK(GetOpcodeField(instr2) == ORI);
 
     uint32_t rs_field = GetRt(instr2) << kRsShift;
     *(p+6) = SPECIAL | rs_field | JR;
     patched = true;
   }
 
   if (patched) {
       CpuFeatures::FlushICache(pc+6, sizeof(int32_t));
   }
 }
 
 
 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
   // No out-of-line constant pool support.
-  ASSERT(!FLAG_enable_ool_constant_pool);
+  DCHECK(!FLAG_enable_ool_constant_pool);
   return isolate->factory()->empty_constant_pool_array();
 }
 
 
 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
   // No out-of-line constant pool support.
-  ASSERT(!FLAG_enable_ool_constant_pool);
+  DCHECK(!FLAG_enable_ool_constant_pool);
   return;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS64