Rename ASSERT* to DCHECK*.

src/mips/ic-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_MIPS
 
@@ skipping 154 matching lines @@
   __ lw(map, FieldMemOperand(receiver, HeapObject::kMapOffset));
   // Check bit field.
   __ lbu(scratch, FieldMemOperand(map, Map::kBitFieldOffset));
   __ And(at, scratch,
          Operand((1 << Map::kIsAccessCheckNeeded) | (1 << interceptor_bit)));
   __ Branch(slow, ne, at, Operand(zero_reg));
   // Check that the object is some kind of JS object EXCEPT JS Value type.
   // In the case that the object is a value-wrapper object,
   // we enter the runtime system to make sure that indexing into string
   // objects work as intended.
-  ASSERT(JS_OBJECT_TYPE > JS_VALUE_TYPE);
+  DCHECK(JS_OBJECT_TYPE > JS_VALUE_TYPE);
   __ lbu(scratch, FieldMemOperand(map, Map::kInstanceTypeOffset));
   __ Branch(slow, lt, scratch, Operand(JS_OBJECT_TYPE));
 }
 
 
 // Loads an indexed element from a fast case array.
 // If not_fast_array is NULL, doesn't perform the elements map check.
 static void GenerateFastArrayLoad(MacroAssembler* masm,
                                   Register receiver,
                                   Register key,
@@ skipping 86 matching lines @@
   __ Branch(not_unique, ne, at, Operand(zero_reg));
 
   __ bind(&unique);
 }
 
 
 void LoadIC::GenerateMegamorphic(MacroAssembler* masm) {
   // The return address is in lr.
   Register receiver = ReceiverRegister();
   Register name = NameRegister();
-  ASSERT(receiver.is(a1));
-  ASSERT(name.is(a2));
+  DCHECK(receiver.is(a1));
+  DCHECK(name.is(a2));
 
   // Probe the stub cache.
   Code::Flags flags = Code::RemoveTypeAndHolderFromFlags(
       Code::ComputeHandlerFlags(Code::LOAD_IC));
   masm->isolate()->stub_cache()->GenerateProbe(
       masm, flags, receiver, name, a3, t0, t1, t2);
 
   // Cache miss: Jump to runtime.
   GenerateMiss(masm);
 }
 
 
 void LoadIC::GenerateNormal(MacroAssembler* masm) {
   Register dictionary = a0;
-  ASSERT(!dictionary.is(ReceiverRegister()));
-  ASSERT(!dictionary.is(NameRegister()));
+  DCHECK(!dictionary.is(ReceiverRegister()));
+  DCHECK(!dictionary.is(NameRegister()));
 
   Label slow;
 
   __ lw(dictionary,
         FieldMemOperand(ReceiverRegister(), JSObject::kPropertiesOffset));
   GenerateDictionaryLoad(masm, &slow, dictionary, NameRegister(), v0, a3, t0);
   __ Ret();
 
   // Dictionary load failed, go slow (but don't miss).
   __ bind(&slow);
@@ skipping 117 matching lines @@
           Operand(FixedArray::kHeaderSize - kHeapObjectTag));
   __ Addu(scratch, backing_store, scratch);
   return MemOperand(scratch);
 }
 
 
 void KeyedLoadIC::GenerateSloppyArguments(MacroAssembler* masm) {
   // The return address is in ra.
   Register receiver = ReceiverRegister();
   Register key = NameRegister();
-  ASSERT(receiver.is(a1));
-  ASSERT(key.is(a2));
+  DCHECK(receiver.is(a1));
+  DCHECK(key.is(a2));
 
   Label slow, notin;
   MemOperand mapped_location =
       GenerateMappedArgumentsLookup(
           masm, receiver, key, a0, a3, t0, &notin, &slow);
   __ Ret(USE_DELAY_SLOT);
   __ lw(v0, mapped_location);
   __ bind(&notin);
   // The unmapped lookup expects that the parameter map is in a0.
   MemOperand unmapped_location =
       GenerateUnmappedArgumentsLookup(masm, key, a0, a3, &slow);
   __ lw(a0, unmapped_location);
   __ LoadRoot(a3, Heap::kTheHoleValueRootIndex);
   __ Branch(&slow, eq, a0, Operand(a3));
   __ Ret(USE_DELAY_SLOT);
   __ mov(v0, a0);
   __ bind(&slow);
   GenerateMiss(masm);
 }
 
 
 void KeyedStoreIC::GenerateSloppyArguments(MacroAssembler* masm) {
   Register receiver = ReceiverRegister();
   Register key = NameRegister();
   Register value = ValueRegister();
-  ASSERT(value.is(a0));
+  DCHECK(value.is(a0));
 
   Label slow, notin;
   // Store address is returned in register (of MemOperand) mapped_location.
   MemOperand mapped_location = GenerateMappedArgumentsLookup(
       masm, receiver, key, a3, t0, t1, &notin, &slow);
   __ sw(value, mapped_location);
   __ mov(t5, value);
-  ASSERT_EQ(mapped_location.offset(), 0);
+  DCHECK_EQ(mapped_location.offset(), 0);
   __ RecordWrite(a3, mapped_location.rm(), t5,
                  kRAHasNotBeenSaved, kDontSaveFPRegs);
   __ Ret(USE_DELAY_SLOT);
   __ mov(v0, value);  // (In delay slot) return the value stored in v0.
   __ bind(&notin);
   // The unmapped lookup expects that the parameter map is in a3.
   // Store address is returned in register (of MemOperand) unmapped_location.
   MemOperand unmapped_location =
       GenerateUnmappedArgumentsLookup(masm, key, a3, t0, &slow);
   __ sw(value, unmapped_location);
   __ mov(t5, value);
-  ASSERT_EQ(unmapped_location.offset(), 0);
+  DCHECK_EQ(unmapped_location.offset(), 0);
   __ RecordWrite(a3, unmapped_location.rm(), t5,
                  kRAHasNotBeenSaved, kDontSaveFPRegs);
   __ Ret(USE_DELAY_SLOT);
   __ mov(v0, a0);  // (In delay slot) return the value stored in v0.
   __ bind(&slow);
   GenerateMiss(masm);
 }
 
 
 void KeyedLoadIC::GenerateMiss(MacroAssembler* masm) {
@@ skipping 11 matching lines @@
   __ TailCallExternalReference(ref, 2, 1);
 }
 
 
 // IC register specifications
 const Register LoadIC::ReceiverRegister() { return a1; }
 const Register LoadIC::NameRegister() { return a2; }
 
 
 const Register LoadIC::SlotRegister() {
-  ASSERT(FLAG_vector_ics);
+  DCHECK(FLAG_vector_ics);
   return a0;
 }
 
 
 const Register LoadIC::VectorRegister() {
-  ASSERT(FLAG_vector_ics);
+  DCHECK(FLAG_vector_ics);
   return a3;
 }
 
 
 const Register StoreIC::ReceiverRegister() { return a1; }
 const Register StoreIC::NameRegister() { return a2; }
 const Register StoreIC::ValueRegister() { return a0; }
 
 
 const Register KeyedStoreIC::MapRegister() {
@@ skipping 10 matching lines @@
 }
 
 
 void KeyedLoadIC::GenerateGeneric(MacroAssembler* masm) {
   // The return address is in ra.
   Label slow, check_name, index_smi, index_name, property_array_property;
   Label probe_dictionary, check_number_dictionary;
 
   Register key = NameRegister();
   Register receiver = ReceiverRegister();
-  ASSERT(key.is(a2));
-  ASSERT(receiver.is(a1));
+  DCHECK(key.is(a2));
+  DCHECK(receiver.is(a1));
 
   Isolate* isolate = masm->isolate();
 
   // Check that the key is a smi.
   __ JumpIfNotSmi(key, &check_name);
   __ bind(&index_smi);
   // Now the key is known to be a smi. This place is also jumped to from below
   // where a numeric string is converted to a smi.
 
   GenerateKeyedLoadReceiverCheck(
@@ skipping 149 matching lines @@
 
 
 void KeyedLoadIC::GenerateString(MacroAssembler* masm) {
   // Return address is in ra.
   Label miss;
 
   Register receiver = ReceiverRegister();
   Register index = NameRegister();
   Register scratch = a3;
   Register result = v0;
-  ASSERT(!scratch.is(receiver) && !scratch.is(index));
+  DCHECK(!scratch.is(receiver) && !scratch.is(index));
 
   StringCharAtGenerator char_at_generator(receiver,
                                           index,
                                           scratch,
                                           result,
                                           &miss,  // When not a string.
                                           &miss,  // When not a number.
                                           &miss,  // When index out of range.
                                           STRING_INDEX_IS_ARRAY_INDEX);
   char_at_generator.GenerateFast(masm);
@@ skipping 199 matching lines @@
   //  -- ra     : return address
   // -----------------------------------
   Label slow, fast_object, fast_object_grow;
   Label fast_double, fast_double_grow;
   Label array, extra, check_if_double_array;
 
   // Register usage.
   Register value = ValueRegister();
   Register key = NameRegister();
   Register receiver = ReceiverRegister();
-  ASSERT(value.is(a0));
+  DCHECK(value.is(a0));
   Register receiver_map = a3;
   Register elements_map = t2;
   Register elements = t3;  // Elements array of the receiver.
   // t0 and t1 are used as general scratch registers.
 
   // Check that the key is a smi.
   __ JumpIfNotSmi(key, &slow);
   // Check that the object isn't a smi.
   __ JumpIfSmi(receiver, &slow);
   // Get the map of the object.
@@ skipping 67 matching lines @@
 
 
 void KeyedLoadIC::GenerateIndexedInterceptor(MacroAssembler* masm) {
   // Return address is in ra.
   Label slow;
 
   Register receiver = ReceiverRegister();
   Register key = NameRegister();
   Register scratch1 = a3;
   Register scratch2 = t0;
-  ASSERT(!scratch1.is(receiver) && !scratch1.is(key));
-  ASSERT(!scratch2.is(receiver) && !scratch2.is(key));
+  DCHECK(!scratch1.is(receiver) && !scratch1.is(key));
+  DCHECK(!scratch2.is(receiver) && !scratch2.is(key));
 
   // Check that the receiver isn't a smi.
   __ JumpIfSmi(receiver, &slow);
 
   // Check that the key is an array index, that is Uint32.
   __ And(t0, key, Operand(kSmiTagMask | kSmiSignMask));
   __ Branch(&slow, ne, t0, Operand(zero_reg));
 
   // Get the map of the receiver.
   __ lw(scratch1, FieldMemOperand(receiver, HeapObject::kMapOffset));
@@ skipping 47 matching lines @@
   ExternalReference ref =
       ExternalReference(IC_Utility(kKeyedStoreIC_Slow), masm->isolate());
 
   __ TailCallExternalReference(ref, 3, 1);
 }
 
 
 void StoreIC::GenerateMegamorphic(MacroAssembler* masm) {
   Register receiver = ReceiverRegister();
   Register name = NameRegister();
-  ASSERT(receiver.is(a1));
-  ASSERT(name.is(a2));
-  ASSERT(ValueRegister().is(a0));
+  DCHECK(receiver.is(a1));
+  DCHECK(name.is(a2));
+  DCHECK(ValueRegister().is(a0));
 
   // Get the receiver from the stack and probe the stub cache.
   Code::Flags flags = Code::RemoveTypeAndHolderFromFlags(
       Code::ComputeHandlerFlags(Code::STORE_IC));
   masm->isolate()->stub_cache()->GenerateProbe(
       masm, flags, receiver, name, a3, t0, t1, t2);
 
   // Cache miss: Jump to runtime.
   GenerateMiss(masm);
 }
 
 
 void StoreIC::GenerateMiss(MacroAssembler* masm) {
   __ Push(ReceiverRegister(), NameRegister(), ValueRegister());
   // Perform tail call to the entry.
   ExternalReference ref = ExternalReference(IC_Utility(kStoreIC_Miss),
                                             masm->isolate());
   __ TailCallExternalReference(ref, 3, 1);
 }
 
 
 void StoreIC::GenerateNormal(MacroAssembler* masm) {
   Label miss;
   Register receiver = ReceiverRegister();
   Register name = NameRegister();
   Register value = ValueRegister();
   Register dictionary = a3;
-  ASSERT(receiver.is(a1));
-  ASSERT(name.is(a2));
-  ASSERT(value.is(a0));
+  DCHECK(receiver.is(a1));
+  DCHECK(name.is(a2));
+  DCHECK(value.is(a0));
 
   __ lw(dictionary, FieldMemOperand(receiver, JSObject::kPropertiesOffset));
 
   GenerateDictionaryStore(masm, &miss, dictionary, name, value, t0, t1);
   Counters* counters = masm->isolate()->counters();
   __ IncrementCounter(counters->store_normal_hit(), 1, t0, t1);
   __ Ret();
 
   __ bind(&miss);
   __ IncrementCounter(counters->store_normal_miss(), 1, t0, t1);
@@ skipping 85 matching lines @@
   // Enabling by changing from
   //   andi at, rx, 0
   //   Branch <target>, eq, at, Operand(zero_reg)
   // to:
   //   andi at, rx, #kSmiTagMask
   //   Branch <target>, ne, at, Operand(zero_reg)
   // and vice-versa to be disabled again.
   CodePatcher patcher(patch_address, 2);
   Register reg = Register::from_code(Assembler::GetRs(instr_at_patch));
   if (check == ENABLE_INLINED_SMI_CHECK) {
-    ASSERT(Assembler::IsAndImmediate(instr_at_patch));
-    ASSERT_EQ(0, Assembler::GetImmediate16(instr_at_patch));
+    DCHECK(Assembler::IsAndImmediate(instr_at_patch));
+    DCHECK_EQ(0, Assembler::GetImmediate16(instr_at_patch));
     patcher.masm()->andi(at, reg, kSmiTagMask);
   } else {
-    ASSERT(check == DISABLE_INLINED_SMI_CHECK);
-    ASSERT(Assembler::IsAndImmediate(instr_at_patch));
+    DCHECK(check == DISABLE_INLINED_SMI_CHECK);
+    DCHECK(Assembler::IsAndImmediate(instr_at_patch));
     patcher.masm()->andi(at, reg, 0);
   }
-  ASSERT(Assembler::IsBranch(branch_instr));
+  DCHECK(Assembler::IsBranch(branch_instr));
   if (Assembler::IsBeq(branch_instr)) {
     patcher.ChangeBranchCondition(ne);
   } else {
-    ASSERT(Assembler::IsBne(branch_instr));
+    DCHECK(Assembler::IsBne(branch_instr));
     patcher.ChangeBranchCondition(eq);
   }
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS