Rename ASSERT* to DCHECK*.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler-intrinsics.h"
 
 namespace v8 {
 namespace internal {
@@ skipping 267 matching lines @@
   if (cont->IsBranch()) {
     inputs[input_count++] = g.Label(cont->true_block());
     inputs[input_count++] = g.Label(cont->false_block());
   }
 
   outputs[output_count++] = g.DefineAsRegister(node);
   if (cont->IsSet()) {
     outputs[output_count++] = g.DefineAsRegister(cont->result());
   }
 
-  ASSERT_NE(0, input_count);
-  ASSERT_NE(0, output_count);
-  ASSERT_GE(ARRAY_SIZE(inputs), input_count);
-  ASSERT_GE(ARRAY_SIZE(outputs), output_count);
-  ASSERT_NE(kMode_None, AddressingModeField::decode(opcode));
+  DCHECK_NE(0, input_count);
+  DCHECK_NE(0, output_count);
+  DCHECK_GE(ARRAY_SIZE(inputs), input_count);
+  DCHECK_GE(ARRAY_SIZE(outputs), output_count);
+  DCHECK_NE(kMode_None, AddressingModeField::decode(opcode));
 
   Instruction* instr = selector->Emit(cont->Encode(opcode), output_count,
                                       outputs, input_count, inputs);
   if (cont->IsBranch()) instr->MarkAsControl();
 }
 
 
 static void VisitBinop(InstructionSelector* selector, Node* node,
                        InstructionCode opcode, InstructionCode reverse_opcode) {
   FlagsContinuation cont;
@@ skipping 46 matching lines @@
 
 void InstructionSelector::VisitStore(Node* node) {
   ArmOperandGenerator g(this);
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
   Node* value = node->InputAt(2);
 
   StoreRepresentation store_rep = OpParameter<StoreRepresentation>(node);
   MachineRepresentation rep = store_rep.rep;
   if (store_rep.write_barrier_kind == kFullWriteBarrier) {
-    ASSERT(rep == kMachineTagged);
+    DCHECK(rep == kMachineTagged);
     // TODO(dcarney): refactor RecordWrite function to take temp registers
     //                and pass them here instead of using fixed regs
     // TODO(dcarney): handle immediate indices.
     InstructionOperand* temps[] = {g.TempRegister(r5), g.TempRegister(r6)};
     Emit(kArmStoreWriteBarrier, NULL, g.UseFixed(base, r4),
          g.UseFixed(index, r5), g.UseFixed(value, r6), ARRAY_SIZE(temps),
          temps);
     return;
   }
-  ASSERT_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
+  DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
   InstructionOperand* val = rep == kMachineFloat64 ? g.UseDoubleRegister(value)
                                                    : g.UseRegister(value);
 
   ArchOpcode opcode;
   switch (rep) {
     case kMachineFloat64:
       opcode = kArmFloat64Store;
       break;
     case kMachineWord8:
       opcode = kArmStoreWord8;
@@ skipping 55 matching lines @@
     if (mright.right().Is(-1)) {
       EmitBic(this, node, m.left().node(), mright.left().node());
       return;
     }
   }
   if (CpuFeatures::IsSupported(ARMv7) && m.right().HasValue()) {
     uint32_t value = m.right().Value();
     uint32_t width = CompilerIntrinsics::CountSetBits(value);
     uint32_t msb = CompilerIntrinsics::CountLeadingZeros(value);
     if (width != 0 && msb + width == 32) {
-      ASSERT_EQ(0, CompilerIntrinsics::CountTrailingZeros(value));
+      DCHECK_EQ(0, CompilerIntrinsics::CountTrailingZeros(value));
       if (m.left().IsWord32Shr()) {
         Int32BinopMatcher mleft(m.left().node());
         if (mleft.right().IsInRange(0, 31)) {
           Emit(kArmUbfx, g.DefineAsRegister(node),
                g.UseRegister(mleft.left().node()),
                g.UseImmediate(mleft.right().node()), g.TempImmediate(width));
           return;
         }
       }
       Emit(kArmUbfx, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
@@ skipping 71 matching lines @@
   Int32BinopMatcher m(node);
   if (CpuFeatures::IsSupported(ARMv7) && m.left().IsWord32And() &&
       m.right().IsInRange(0, 31)) {
     int32_t lsb = m.right().Value();
     Int32BinopMatcher mleft(m.left().node());
     if (mleft.right().HasValue()) {
       uint32_t value = (mleft.right().Value() >> lsb) << lsb;
       uint32_t width = CompilerIntrinsics::CountSetBits(value);
       uint32_t msb = CompilerIntrinsics::CountLeadingZeros(value);
       if (msb + width + lsb == 32) {
-        ASSERT_EQ(lsb, CompilerIntrinsics::CountTrailingZeros(value));
+        DCHECK_EQ(lsb, CompilerIntrinsics::CountTrailingZeros(value));
         Emit(kArmUbfx, g.DefineAsRegister(node),
              g.UseRegister(mleft.left().node()), g.TempImmediate(lsb),
              g.TempImmediate(width));
         return;
       }
     }
   }
   VisitShift(this, node, TryMatchLSR);
 }
 
@@ skipping 262 matching lines @@
       return;
   }
 
   // Emit the call instruction.
   Instruction* call_instr =
       Emit(opcode, buffer.output_count, buffer.outputs,
            buffer.fixed_and_control_count(), buffer.fixed_and_control_args);
 
   call_instr->MarkAsCall();
   if (deoptimization != NULL) {
-    ASSERT(continuation != NULL);
+    DCHECK(continuation != NULL);
     call_instr->MarkAsControl();
   }
 
   // Caller clean up of stack for C-style calls.
   if (descriptor->kind() == CallDescriptor::kCallAddress &&
       buffer.pushed_count > 0) {
-    ASSERT(deoptimization == NULL && continuation == NULL);
+    DCHECK(deoptimization == NULL && continuation == NULL);
     Emit(kArmDrop | MiscField::encode(buffer.pushed_count), NULL);
   }
 }
 
 
 void InstructionSelector::VisitInt32AddWithOverflow(Node* node,
                                                     FlagsContinuation* cont) {
   VisitBinop(this, node, kArmAdd, kArmAdd, cont);
 }
 
@@ skipping 27 matching lines @@
   } else {
     opcode |= AddressingModeField::encode(kMode_Operand2_R);
     inputs[input_count++] = g.UseRegister(m.left().node());
     inputs[input_count++] = g.UseRegister(m.right().node());
   }
 
   if (cont->IsBranch()) {
     inputs[input_count++] = g.Label(cont->true_block());
     inputs[input_count++] = g.Label(cont->false_block());
   } else {
-    ASSERT(cont->IsSet());
+    DCHECK(cont->IsSet());
     outputs[output_count++] = g.DefineAsRegister(cont->result());
   }
 
-  ASSERT_NE(0, input_count);
-  ASSERT_GE(ARRAY_SIZE(inputs), input_count);
-  ASSERT_GE(ARRAY_SIZE(outputs), output_count);
+  DCHECK_NE(0, input_count);
+  DCHECK_GE(ARRAY_SIZE(inputs), input_count);
+  DCHECK_GE(ARRAY_SIZE(outputs), output_count);
 
   Instruction* instr = selector->Emit(cont->Encode(opcode), output_count,
                                       outputs, input_count, inputs);
   if (cont->IsBranch()) instr->MarkAsControl();
 }
 
 
 void InstructionSelector::VisitWord32Test(Node* node, FlagsContinuation* cont) {
   switch (node->opcode()) {
     case IrOpcode::kInt32Add:
@@ skipping 32 matching lines @@
 
 void InstructionSelector::VisitFloat64Compare(Node* node,
                                               FlagsContinuation* cont) {
   ArmOperandGenerator g(this);
   Float64BinopMatcher m(node);
   if (cont->IsBranch()) {
     Emit(cont->Encode(kArmVcmpF64), NULL, g.UseDoubleRegister(m.left().node()),
          g.UseDoubleRegister(m.right().node()), g.Label(cont->true_block()),
          g.Label(cont->false_block()))->MarkAsControl();
   } else {
-    ASSERT(cont->IsSet());
+    DCHECK(cont->IsSet());
     Emit(cont->Encode(kArmVcmpF64), g.DefineAsRegister(cont->result()),
          g.UseDoubleRegister(m.left().node()),
          g.UseDoubleRegister(m.right().node()));
   }
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8