Rename ASSERT* to DCHECK*.

src/arm64/simulator-arm64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_SIMULATOR_ARM64_H_
 #define V8_ARM64_SIMULATOR_ARM64_H_
 
 #include <stdarg.h>
 #include <vector>
 
@@ skipping 194 matching lines @@
 
   // A wrapper class that stores an argument for one of the above Call
   // functions.
   //
   // Only arguments up to 64 bits in size are supported.
   class CallArgument {
    public:
     template<typename T>
     explicit CallArgument(T argument) {
       bits_ = 0;
-      ASSERT(sizeof(argument) <= sizeof(bits_));
+      DCHECK(sizeof(argument) <= sizeof(bits_));
       memcpy(&bits_, &argument, sizeof(argument));
       type_ = X_ARG;
     }
 
     explicit CallArgument(double argument) {
-      ASSERT(sizeof(argument) == sizeof(bits_));
+      DCHECK(sizeof(argument) == sizeof(bits_));
       memcpy(&bits_, &argument, sizeof(argument));
       type_ = D_ARG;
     }
 
     explicit CallArgument(float argument) {
       // TODO(all): CallArgument(float) is untested, remove this check once
       //            tested.
       UNIMPLEMENTED();
       // Make the D register a NaN to try to trap errors if the callee expects a
       // double. If it expects a float, the callee should ignore the top word.
-      ASSERT(sizeof(kFP64SignallingNaN) == sizeof(bits_));
+      DCHECK(sizeof(kFP64SignallingNaN) == sizeof(bits_));
       memcpy(&bits_, &kFP64SignallingNaN, sizeof(kFP64SignallingNaN));
       // Write the float payload to the S register.
-      ASSERT(sizeof(argument) <= sizeof(bits_));
+      DCHECK(sizeof(argument) <= sizeof(bits_));
       memcpy(&bits_, &argument, sizeof(argument));
       type_ = D_ARG;
     }
 
     // This indicates the end of the arguments list, so that CallArgument
     // objects can be passed into varargs functions.
     static CallArgument End() { return CallArgument(); }
 
     int64_t bits() const { return bits_; }
     bool IsEnd() const { return type_ == NO_ARG; }
@@ skipping 37 matching lines @@
 
   // Run the simulator.
   static const Instruction* kEndOfSimAddress;
   void DecodeInstruction();
   void Run();
   void RunFrom(Instruction* start);
 
   // Simulation helpers.
   template <typename T>
   void set_pc(T new_pc) {
-    ASSERT(sizeof(T) == sizeof(pc_));
+    DCHECK(sizeof(T) == sizeof(pc_));
     memcpy(&pc_, &new_pc, sizeof(T));
     pc_modified_ = true;
   }
   Instruction* pc() { return pc_; }
 
   void increment_pc() {
     if (!pc_modified_) {
       pc_ = pc_->following();
     }
 
     pc_modified_ = false;
   }
 
   virtual void Decode(Instruction* instr) {
     decoder_->Decode(instr);
   }
 
   void ExecuteInstruction() {
-    ASSERT(IsAligned(reinterpret_cast<uintptr_t>(pc_), kInstructionSize));
+    DCHECK(IsAligned(reinterpret_cast<uintptr_t>(pc_), kInstructionSize));
     CheckBreakNext();
     Decode(pc_);
     LogProcessorState();
     increment_pc();
     CheckBreakpoints();
   }
 
   // Declare all Visitor functions.
   #define DECLARE(A)  void Visit##A(Instruction* instr);
   VISITOR_LIST(DECLARE)
   #undef DECLARE
 
   bool IsZeroRegister(unsigned code, Reg31Mode r31mode) const {
     return ((code == 31) && (r31mode == Reg31IsZeroRegister));
   }
 
   // Register accessors.
   // Return 'size' bits of the value of an integer register, as the specified
   // type. The value is zero-extended to fill the result.
   //
   template<typename T>
   T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
-    ASSERT(code < kNumberOfRegisters);
+    DCHECK(code < kNumberOfRegisters);
     if (IsZeroRegister(code, r31mode)) {
       return 0;
     }
     return registers_[code].Get<T>();
   }
 
   // Common specialized accessors for the reg() template.
   int32_t wreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
     return reg<int32_t>(code, r31mode);
   }
 
   int64_t xreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
     return reg<int64_t>(code, r31mode);
   }
 
   // Write 'size' bits of 'value' into an integer register. The value is
   // zero-extended. This behaviour matches AArch64 register writes.
 
   // Like set_reg(), but infer the access size from the template type.
   template<typename T>
   void set_reg(unsigned code, T value,
                Reg31Mode r31mode = Reg31IsZeroRegister) {
-    ASSERT(code < kNumberOfRegisters);
+    DCHECK(code < kNumberOfRegisters);
     if (!IsZeroRegister(code, r31mode))
       registers_[code].Set(value);
   }
 
   // Common specialized accessors for the set_reg() template.
   void set_wreg(unsigned code, int32_t value,
                 Reg31Mode r31mode = Reg31IsZeroRegister) {
     set_reg(code, value, r31mode);
   }
 
   void set_xreg(unsigned code, int64_t value,
                 Reg31Mode r31mode = Reg31IsZeroRegister) {
     set_reg(code, value, r31mode);
   }
 
   // Commonly-used special cases.
   template<typename T>
   void set_lr(T value) {
-    ASSERT(sizeof(T) == kPointerSize);
+    DCHECK(sizeof(T) == kPointerSize);
     set_reg(kLinkRegCode, value);
   }
 
   template<typename T>
   void set_sp(T value) {
-    ASSERT(sizeof(T) == kPointerSize);
+    DCHECK(sizeof(T) == kPointerSize);
     set_reg(31, value, Reg31IsStackPointer);
   }
 
   int64_t sp() { return xreg(31, Reg31IsStackPointer); }
   int64_t jssp() { return xreg(kJSSPCode, Reg31IsStackPointer); }
   int64_t fp() {
       return xreg(kFramePointerRegCode, Reg31IsStackPointer);
   }
   Instruction* lr() { return reg<Instruction*>(kLinkRegCode); }
 
   Address get_sp() { return reg<Address>(31, Reg31IsStackPointer); }
 
   template<typename T>
   T fpreg(unsigned code) const {
-    ASSERT(code < kNumberOfRegisters);
+    DCHECK(code < kNumberOfRegisters);
     return fpregisters_[code].Get<T>();
   }
 
   // Common specialized accessors for the fpreg() template.
   float sreg(unsigned code) const {
     return fpreg<float>(code);
   }
 
   uint32_t sreg_bits(unsigned code) const {
     return fpreg<uint32_t>(code);
@@ skipping 14 matching lines @@
       default:
         UNREACHABLE();
         return 0.0;
     }
   }
 
   // Write 'value' into a floating-point register. The value is zero-extended.
   // This behaviour matches AArch64 register writes.
   template<typename T>
   void set_fpreg(unsigned code, T value) {
-    ASSERT((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
-    ASSERT(code < kNumberOfFPRegisters);
+    DCHECK((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
+    DCHECK(code < kNumberOfFPRegisters);
     fpregisters_[code].Set(value);
   }
 
   // Common specialized accessors for the set_fpreg() template.
   void set_sreg(unsigned code, float value) {
     set_fpreg(code, value);
   }
 
   void set_sreg_bits(unsigned code, uint32_t value) {
     set_fpreg(code, value);
@@ skipping 292 matching lines @@
   SimSystemRegister fpcr_;
 
   // Only a subset of FPCR features are supported by the simulator. This helper
   // checks that the FPCR settings are supported.
   //
   // This is checked when floating-point instructions are executed, not when
   // FPCR is set. This allows generated code to modify FPCR for external
   // functions, or to save and restore it when entering and leaving generated
   // code.
   void AssertSupportedFPCR() {
-    ASSERT(fpcr().FZ() == 0);             // No flush-to-zero support.
-    ASSERT(fpcr().RMode() == FPTieEven);  // Ties-to-even rounding only.
+    DCHECK(fpcr().FZ() == 0);             // No flush-to-zero support.
+    DCHECK(fpcr().RMode() == FPTieEven);  // Ties-to-even rounding only.
 
     // The simulator does not support half-precision operations so fpcr().AHP()
     // is irrelevant, and is not checked here.
   }
 
   template <typename T>
   static int CalcNFlag(T result) {
     return (result >> (sizeof(T) * 8 - 1)) & 1;
   }
 
@@ skipping 70 matching lines @@
   static void UnregisterCTryCatch() {
     Simulator::current(Isolate::Current())->PopAddress();
   }
 };
 
 #endif  // !defined(USE_SIMULATOR)
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM64_SIMULATOR_ARM64_H_