Rename ASSERT* to DCHECK*.

src/arm64/instructions-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_ARM64
 
 #define ARM64_DEFINE_FP_STATICS
 
@@ skipping 49 matching lines @@
       case STR_d: return true;
       default: return false;
     }
   }
 }
 
 
 static uint64_t RotateRight(uint64_t value,
                             unsigned int rotate,
                             unsigned int width) {
-  ASSERT(width <= 64);
+  DCHECK(width <= 64);
   rotate &= 63;
   return ((value & ((1UL << rotate) - 1UL)) << (width - rotate)) |
          (value >> rotate);
 }
 
 
 static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
                                     uint64_t value,
                                     unsigned width) {
-  ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
+  DCHECK((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
          (width == 32));
-  ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
+  DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
   uint64_t result = value & ((1UL << width) - 1UL);
   for (unsigned i = width; i < reg_size; i *= 2) {
     result |= (result << i);
   }
   return result;
 }
 
 
 // Logical immediates can't encode zero, so a return value of zero is used to
 // indicate a failure case. Specifically, where the constraints on imm_s are not
@@ skipping 93 matching lines @@
   ptrdiff_t offset;
   if (IsPCRelAddressing()) {
     // PC-relative addressing. Only ADR is supported.
     offset = ImmPCRel();
   } else if (BranchType() != UnknownBranchType) {
     // All PC-relative branches.
     // Relative branch offsets are instruction-size-aligned.
     offset = ImmBranch() << kInstructionSizeLog2;
   } else {
     // Load literal (offset from PC).
-    ASSERT(IsLdrLiteral());
+    DCHECK(IsLdrLiteral());
     // The offset is always shifted by 2 bits, even for loads to 64-bits
     // registers.
     offset = ImmLLiteral() << kInstructionSizeLog2;
   }
   return offset;
 }
 
 
 Instruction* Instruction::ImmPCOffsetTarget() {
   return InstructionAtOffset(ImmPCOffset());
@@ skipping 17 matching lines @@
   } else if (BranchType() != UnknownBranchType) {
     SetBranchImmTarget(target);
   } else {
     SetImmLLiteral(target);
   }
 }
 
 
 void Instruction::SetPCRelImmTarget(Instruction* target) {
   // ADRP is not supported, so 'this' must point to an ADR instruction.
-  ASSERT(IsAdr());
+  DCHECK(IsAdr());
 
   ptrdiff_t target_offset = DistanceTo(target);
   Instr imm;
   if (Instruction::IsValidPCRelOffset(target_offset)) {
     imm = Assembler::ImmPCRelAddress(target_offset);
     SetInstructionBits(Mask(~ImmPCRel_mask) | imm);
   } else {
     PatchingAssembler patcher(this,
                               PatchingAssembler::kAdrFarPatchableNInstrs);
     patcher.PatchAdrFar(target_offset);
   }
 }
 
 
 void Instruction::SetBranchImmTarget(Instruction* target) {
-  ASSERT(IsAligned(DistanceTo(target), kInstructionSize));
+  DCHECK(IsAligned(DistanceTo(target), kInstructionSize));
   Instr branch_imm = 0;
   uint32_t imm_mask = 0;
   ptrdiff_t offset = DistanceTo(target) >> kInstructionSizeLog2;
   switch (BranchType()) {
     case CondBranchType: {
       branch_imm = Assembler::ImmCondBranch(offset);
       imm_mask = ImmCondBranch_mask;
       break;
     }
     case UncondBranchType: {
@@ skipping 11 matching lines @@
       imm_mask = ImmTestBranch_mask;
       break;
     }
     default: UNREACHABLE();
   }
   SetInstructionBits(Mask(~imm_mask) | branch_imm);
 }
 
 
 void Instruction::SetImmLLiteral(Instruction* source) {
-  ASSERT(IsAligned(DistanceTo(source), kInstructionSize));
+  DCHECK(IsAligned(DistanceTo(source), kInstructionSize));
   ptrdiff_t offset = DistanceTo(source) >> kLoadLiteralScaleLog2;
   Instr imm = Assembler::ImmLLiteral(offset);
   Instr mask = ImmLLiteral_mask;
 
   SetInstructionBits(Mask(~mask) | imm);
 }
 
 
 // TODO(jbramley): We can't put this inline in the class because things like
 // xzr and Register are not defined in that header. Consider adding
 // instructions-arm64-inl.h to work around this.
 bool InstructionSequence::IsInlineData() const {
   // Inline data is encoded as a single movz instruction which writes to xzr
   // (x31).
   return IsMovz() && SixtyFourBits() && (Rd() == xzr.code());
   // TODO(all): If we extend ::InlineData() to support bigger data, we need
   // to update this method too.
 }
 
 
 // TODO(jbramley): We can't put this inline in the class because things like
 // xzr and Register are not defined in that header. Consider adding
 // instructions-arm64-inl.h to work around this.
 uint64_t InstructionSequence::InlineData() const {
-  ASSERT(IsInlineData());
+  DCHECK(IsInlineData());
   uint64_t payload = ImmMoveWide();
   // TODO(all): If we extend ::InlineData() to support bigger data, we need
   // to update this method too.
   return payload;
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64