Rename ASSERT* to DCHECK*.

src/arm64/disasm-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <assert.h>
 #include <stdarg.h>
 #include <stdio.h>
 #include <string.h>
 
 #include "src/v8.h"
@@ skipping 240 matching lines @@
       }
       break;
     }
     default: UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
 bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
-  ASSERT((reg_size == kXRegSizeInBits) ||
+  DCHECK((reg_size == kXRegSizeInBits) ||
          ((reg_size == kWRegSizeInBits) && (value <= 0xffffffff)));
 
   // Test for movz: 16-bits set at positions 0, 16, 32 or 48.
   if (((value & 0xffffffffffff0000UL) == 0UL) ||
       ((value & 0xffffffff0000ffffUL) == 0UL) ||
       ((value & 0xffff0000ffffffffUL) == 0UL) ||
       ((value & 0x0000ffffffffffffUL) == 0UL)) {
     return true;
   }
 
@@ skipping 897 matching lines @@
         mnemonic = "msr";
         switch (instr->ImmSystemRegister()) {
           case NZCV: form = "nzcv, 'Xt"; break;
           case FPCR: form = "fpcr, 'Xt"; break;
           default: form = "(unknown), 'Xt"; break;
         }
         break;
       }
     }
   } else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
-    ASSERT(instr->Mask(SystemHintMask) == HINT);
+    DCHECK(instr->Mask(SystemHintMask) == HINT);
     switch (instr->ImmHint()) {
       case NOP: {
         mnemonic = "nop";
         form = NULL;
         break;
       }
     }
   } else if (instr->Mask(MemBarrierFMask) == MemBarrierFixed) {
     switch (instr->Mask(MemBarrierMask)) {
       case DMB: {
@@ skipping 49 matching lines @@
 
 void Disassembler::ProcessOutput(Instruction* /*instr*/) {
   // The base disasm does nothing more than disassembling into a buffer.
 }
 
 
 void Disassembler::Format(Instruction* instr, const char* mnemonic,
                           const char* format) {
   // TODO(mcapewel) don't think I can use the instr address here - there needs
   //                to be a base address too
-  ASSERT(mnemonic != NULL);
+  DCHECK(mnemonic != NULL);
   ResetOutput();
   Substitute(instr, mnemonic);
   if (format != NULL) {
     buffer_[buffer_pos_++] = ' ';
     Substitute(instr, format);
   }
   buffer_[buffer_pos_] = 0;
   ProcessOutput(instr);
 }
 
@@ skipping 97 matching lines @@
     // Disassemble w31/x31 as zero register wzr/xzr.
     AppendToOutput("%czr", reg_type);
   }
 
   return field_len;
 }
 
 
 int Disassembler::SubstituteImmediateField(Instruction* instr,
                                            const char* format) {
-  ASSERT(format[0] == 'I');
+  DCHECK(format[0] == 'I');
 
   switch (format[1]) {
     case 'M': {  // IMoveImm or IMoveLSL.
       if (format[5] == 'I') {
         uint64_t imm = instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
         AppendToOutput("#0x%" PRIx64, imm);
       } else {
-        ASSERT(format[5] == 'L');
+        DCHECK(format[5] == 'L');
         AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide());
         if (instr->ShiftMoveWide() > 0) {
           AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide());
         }
       }
       return 8;
     }
     case 'L': {
       switch (format[2]) {
         case 'L': {  // ILLiteral - Immediate Load Literal.
@@ skipping 24 matching lines @@
         }
       }
     }
     case 'C': {  // ICondB - Immediate Conditional Branch.
       int64_t offset = instr->ImmCondBranch() << 2;
       char sign = (offset >= 0) ? '+' : '-';
       AppendToOutput("#%c0x%" PRIx64, sign, offset);
       return 6;
     }
     case 'A': {  // IAddSub.
-      ASSERT(instr->ShiftAddSub() <= 1);
+      DCHECK(instr->ShiftAddSub() <= 1);
       int64_t imm = instr->ImmAddSub() << (12 * instr->ShiftAddSub());
       AppendToOutput("#0x%" PRIx64 " (%" PRId64 ")", imm, imm);
       return 7;
     }
     case 'F': {  // IFPSingle, IFPDouble or IFPFBits.
       if (format[3] == 'F') {  // IFPFBits.
         AppendToOutput("#%d", 64 - instr->FPScale());
         return 8;
       } else {
         AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(),
@@ skipping 36 matching lines @@
     default: {
       UNREACHABLE();
       return 0;
     }
   }
 }
 
 
 int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
                                                    const char* format) {
-  ASSERT((format[0] == 'I') && (format[1] == 'B'));
+  DCHECK((format[0] == 'I') && (format[1] == 'B'));
   unsigned r = instr->ImmR();
   unsigned s = instr->ImmS();
 
   switch (format[2]) {
     case 'r': {  // IBr.
       AppendToOutput("#%d", r);
       return 3;
     }
     case 's': {  // IBs+1 or IBs-r+1.
       if (format[3] == '+') {
         AppendToOutput("#%d", s + 1);
         return 5;
       } else {
-        ASSERT(format[3] == '-');
+        DCHECK(format[3] == '-');
         AppendToOutput("#%d", s - r + 1);
         return 7;
       }
     }
     case 'Z': {  // IBZ-r.
-      ASSERT((format[3] == '-') && (format[4] == 'r'));
+      DCHECK((format[3] == '-') && (format[4] == 'r'));
       unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
                                                         : kWRegSizeInBits;
       AppendToOutput("#%d", reg_size - r);
       return 5;
     }
     default: {
       UNREACHABLE();
       return 0;
     }
   }
 }
 
 
 int Disassembler::SubstituteLiteralField(Instruction* instr,
                                          const char* format) {
-  ASSERT(strncmp(format, "LValue", 6) == 0);
+  DCHECK(strncmp(format, "LValue", 6) == 0);
   USE(format);
 
   switch (instr->Mask(LoadLiteralMask)) {
     case LDR_w_lit:
     case LDR_x_lit:
     case LDR_s_lit:
     case LDR_d_lit: AppendToOutput("(addr %p)", instr->LiteralAddress()); break;
     default: UNREACHABLE();
   }
 
   return 6;
 }
 
 
 int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
-  ASSERT(format[0] == 'H');
-  ASSERT(instr->ShiftDP() <= 0x3);
+  DCHECK(format[0] == 'H');
+  DCHECK(instr->ShiftDP() <= 0x3);
 
   switch (format[1]) {
     case 'D': {  // HDP.
-      ASSERT(instr->ShiftDP() != ROR);
+      DCHECK(instr->ShiftDP() != ROR);
     }  // Fall through.
     case 'L': {  // HLo.
       if (instr->ImmDPShift() != 0) {
         const char* shift_type[] = {"lsl", "lsr", "asr", "ror"};
         AppendToOutput(", %s #%" PRId64, shift_type[instr->ShiftDP()],
                        instr->ImmDPShift());
       }
       return 3;
     }
     default:
       UNREACHABLE();
       return 0;
   }
 }
 
 
 int Disassembler::SubstituteConditionField(Instruction* instr,
                                            const char* format) {
-  ASSERT(format[0] == 'C');
+  DCHECK(format[0] == 'C');
   const char* condition_code[] = { "eq", "ne", "hs", "lo",
                                    "mi", "pl", "vs", "vc",
                                    "hi", "ls", "ge", "lt",
                                    "gt", "le", "al", "nv" };
   int cond;
   switch (format[1]) {
     case 'B': cond = instr->ConditionBranch(); break;
     case 'I': {
       cond = NegateCondition(static_cast<Condition>(instr->Condition()));
       break;
     }
     default: cond = instr->Condition();
   }
   AppendToOutput("%s", condition_code[cond]);
   return 4;
 }
 
 
 int Disassembler::SubstitutePCRelAddressField(Instruction* instr,
                                               const char* format) {
   USE(format);
-  ASSERT(strncmp(format, "AddrPCRel", 9) == 0);
+  DCHECK(strncmp(format, "AddrPCRel", 9) == 0);
 
   int offset = instr->ImmPCRel();
 
   // Only ADR (AddrPCRelByte) is supported.
-  ASSERT(strcmp(format, "AddrPCRelByte") == 0);
+  DCHECK(strcmp(format, "AddrPCRelByte") == 0);
 
   char sign = '+';
   if (offset < 0) {
     offset = -offset;
     sign = '-';
   }
   AppendToOutput("#%c0x%x (addr %p)", sign, offset,
                  instr->InstructionAtOffset(offset, Instruction::NO_CHECK));
   return 13;
 }
 
 
 int Disassembler::SubstituteBranchTargetField(Instruction* instr,
                                               const char* format) {
-  ASSERT(strncmp(format, "BImm", 4) == 0);
+  DCHECK(strncmp(format, "BImm", 4) == 0);
 
   int64_t offset = 0;
   switch (format[5]) {
     // BImmUncn - unconditional branch immediate.
     case 'n': offset = instr->ImmUncondBranch(); break;
     // BImmCond - conditional branch immediate.
     case 'o': offset = instr->ImmCondBranch(); break;
     // BImmCmpa - compare and branch immediate.
     case 'm': offset = instr->ImmCmpBranch(); break;
     // BImmTest - test and branch immediate.
     case 'e': offset = instr->ImmTestBranch(); break;
     default: UNREACHABLE();
   }
   offset <<= kInstructionSizeLog2;
   char sign = '+';
   if (offset < 0) {
     sign = '-';
   }
   AppendToOutput("#%c0x%" PRIx64 " (addr %p)", sign, Abs(offset),
                  instr->InstructionAtOffset(offset), Instruction::NO_CHECK);
   return 8;
 }
 
 
 int Disassembler::SubstituteExtendField(Instruction* instr,
                                         const char* format) {
-  ASSERT(strncmp(format, "Ext", 3) == 0);
-  ASSERT(instr->ExtendMode() <= 7);
+  DCHECK(strncmp(format, "Ext", 3) == 0);
+  DCHECK(instr->ExtendMode() <= 7);
   USE(format);
 
   const char* extend_mode[] = { "uxtb", "uxth", "uxtw", "uxtx",
                                 "sxtb", "sxth", "sxtw", "sxtx" };
 
   // If rd or rn is SP, uxtw on 32-bit registers and uxtx on 64-bit
   // registers becomes lsl.
   if (((instr->Rd() == kZeroRegCode) || (instr->Rn() == kZeroRegCode)) &&
       (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) ||
        (instr->ExtendMode() == UXTX))) {
     if (instr->ImmExtendShift() > 0) {
       AppendToOutput(", lsl #%d", instr->ImmExtendShift());
     }
   } else {
     AppendToOutput(", %s", extend_mode[instr->ExtendMode()]);
     if (instr->ImmExtendShift() > 0) {
       AppendToOutput(" #%d", instr->ImmExtendShift());
     }
   }
   return 3;
 }
 
 
 int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
                                              const char* format) {
-  ASSERT(strncmp(format, "Offsetreg", 9) == 0);
+  DCHECK(strncmp(format, "Offsetreg", 9) == 0);
   const char* extend_mode[] = { "undefined", "undefined", "uxtw", "lsl",
                                 "undefined", "undefined", "sxtw", "sxtx" };
   USE(format);
 
   unsigned shift = instr->ImmShiftLS();
   Extend ext = static_cast<Extend>(instr->ExtendMode());
   char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x';
 
   unsigned rm = instr->Rm();
   if (rm == kZeroRegCode) {
     AppendToOutput("%czr", reg_type);
   } else {
     AppendToOutput("%c%d", reg_type, rm);
   }
 
   // Extend mode UXTX is an alias for shift mode LSL here.
   if (!((ext == UXTX) && (shift == 0))) {
     AppendToOutput(", %s", extend_mode[ext]);
     if (shift != 0) {
       AppendToOutput(" #%d", instr->SizeLS());
     }
   }
   return 9;
 }
 
 
 int Disassembler::SubstitutePrefetchField(Instruction* instr,
                                           const char* format) {
-  ASSERT(format[0] == 'P');
+  DCHECK(format[0] == 'P');
   USE(format);
 
   int prefetch_mode = instr->PrefetchMode();
 
   const char* ls = (prefetch_mode & 0x10) ? "st" : "ld";
   int level = (prefetch_mode >> 1) + 1;
   const char* ks = (prefetch_mode & 1) ? "strm" : "keep";
 
   AppendToOutput("p%sl%d%s", ls, level, ks);
   return 6;
 }
 
 int Disassembler::SubstituteBarrierField(Instruction* instr,
                                          const char* format) {
-  ASSERT(format[0] == 'M');
+  DCHECK(format[0] == 'M');
   USE(format);
 
   static const char* options[4][4] = {
     { "sy (0b0000)", "oshld", "oshst", "osh" },
     { "sy (0b0100)", "nshld", "nshst", "nsh" },
     { "sy (0b1000)", "ishld", "ishst", "ish" },
     { "sy (0b1100)", "ld", "st", "sy" }
   };
   int domain = instr->ImmBarrierDomain();
   int type = instr->ImmBarrierType();
@@ skipping 119 matching lines @@
   decoder.AppendVisitor(&disasm);
 
   for (byte* pc = start; pc < end; pc += v8::internal::kInstructionSize) {
     decoder.Decode(reinterpret_cast<v8::internal::Instruction*>(pc));
   }
 }
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM64