Rename ASSERT* to DCHECK*.

src/arm64/decoder-arm64-inl.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_DECODER_ARM64_INL_H_
 #define V8_ARM64_DECODER_ARM64_INL_H_
 
 #include "src/arm64/decoder-arm64.h"
 #include "src/globals.h"
 #include "src/utils.h"
@@ skipping 78 matching lines @@
       //      Advanced SIMD.
       case 0xE:
       case 0xF: DecodeFP(instr); break;
     }
   }
 }
 
 
 template<typename V>
 void Decoder<V>::DecodePCRelAddressing(Instruction* instr) {
-  ASSERT(instr->Bits(27, 24) == 0x0);
+  DCHECK(instr->Bits(27, 24) == 0x0);
   // We know bit 28 is set, as <b28:b27> = 0 is filtered out at the top level
   // decode.
-  ASSERT(instr->Bit(28) == 0x1);
+  DCHECK(instr->Bit(28) == 0x1);
   V::VisitPCRelAddressing(instr);
 }
 
 
 template<typename V>
 void Decoder<V>::DecodeBranchSystemException(Instruction* instr) {
-  ASSERT((instr->Bits(27, 24) == 0x4) ||
+  DCHECK((instr->Bits(27, 24) == 0x4) ||
          (instr->Bits(27, 24) == 0x5) ||
          (instr->Bits(27, 24) == 0x6) ||
          (instr->Bits(27, 24) == 0x7) );
 
   switch (instr->Bits(31, 29)) {
     case 0:
     case 4: {
       V::VisitUnconditionalBranch(instr);
       break;
     }
@@ skipping 81 matching lines @@
     case 7: {
       V::VisitUnallocated(instr);
       break;
     }
   }
 }
 
 
 template<typename V>
 void Decoder<V>::DecodeLoadStore(Instruction* instr) {
-  ASSERT((instr->Bits(27, 24) == 0x8) ||
+  DCHECK((instr->Bits(27, 24) == 0x8) ||
          (instr->Bits(27, 24) == 0x9) ||
          (instr->Bits(27, 24) == 0xC) ||
          (instr->Bits(27, 24) == 0xD) );
 
   if (instr->Bit(24) == 0) {
     if (instr->Bit(28) == 0) {
       if (instr->Bit(29) == 0) {
         if (instr->Bit(26) == 0) {
           // TODO(all): VisitLoadStoreExclusive.
           V::VisitUnimplemented(instr);
@@ skipping 99 matching lines @@
           V::VisitLoadStoreUnsignedOffset(instr);
         }
       }
     }
   }
 }
 
 
 template<typename V>
 void Decoder<V>::DecodeLogical(Instruction* instr) {
-  ASSERT(instr->Bits(27, 24) == 0x2);
+  DCHECK(instr->Bits(27, 24) == 0x2);
 
   if (instr->Mask(0x80400000) == 0x00400000) {
     V::VisitUnallocated(instr);
   } else {
     if (instr->Bit(23) == 0) {
       V::VisitLogicalImmediate(instr);
     } else {
       if (instr->Bits(30, 29) == 0x1) {
         V::VisitUnallocated(instr);
       } else {
         V::VisitMoveWideImmediate(instr);
       }
     }
   }
 }
 
 
 template<typename V>
 void Decoder<V>::DecodeBitfieldExtract(Instruction* instr) {
-  ASSERT(instr->Bits(27, 24) == 0x3);
+  DCHECK(instr->Bits(27, 24) == 0x3);
 
   if ((instr->Mask(0x80400000) == 0x80000000) ||
       (instr->Mask(0x80400000) == 0x00400000) ||
       (instr->Mask(0x80008000) == 0x00008000)) {
     V::VisitUnallocated(instr);
   } else if (instr->Bit(23) == 0) {
     if ((instr->Mask(0x80200000) == 0x00200000) ||
         (instr->Mask(0x60000000) == 0x60000000)) {
       V::VisitUnallocated(instr);
     } else {
       V::VisitBitfield(instr);
     }
   } else {
     if ((instr->Mask(0x60200000) == 0x00200000) ||
         (instr->Mask(0x60000000) != 0x00000000)) {
       V::VisitUnallocated(instr);
     } else {
       V::VisitExtract(instr);
     }
   }
 }
 
 
 template<typename V>
 void Decoder<V>::DecodeAddSubImmediate(Instruction* instr) {
-  ASSERT(instr->Bits(27, 24) == 0x1);
+  DCHECK(instr->Bits(27, 24) == 0x1);
   if (instr->Bit(23) == 1) {
     V::VisitUnallocated(instr);
   } else {
     V::VisitAddSubImmediate(instr);
   }
 }
 
 
 template<typename V>
 void Decoder<V>::DecodeDataProcessing(Instruction* instr) {
-  ASSERT((instr->Bits(27, 24) == 0xA) ||
+  DCHECK((instr->Bits(27, 24) == 0xA) ||
          (instr->Bits(27, 24) == 0xB) );
 
   if (instr->Bit(24) == 0) {
     if (instr->Bit(28) == 0) {
       if (instr->Mask(0x80008000) == 0x00008000) {
         V::VisitUnallocated(instr);
       } else {
         V::VisitLogicalShifted(instr);
       }
     } else {
@@ skipping 95 matching lines @@
       } else {
         V::VisitDataProcessing3Source(instr);
       }
     }
   }
 }
 
 
 template<typename V>
 void Decoder<V>::DecodeFP(Instruction* instr) {
-  ASSERT((instr->Bits(27, 24) == 0xE) ||
+  DCHECK((instr->Bits(27, 24) == 0xE) ||
          (instr->Bits(27, 24) == 0xF) );
 
   if (instr->Bit(28) == 0) {
     DecodeAdvSIMDDataProcessing(instr);
   } else {
     if (instr->Bit(29) == 1) {
       V::VisitUnallocated(instr);
     } else {
       if (instr->Bits(31, 30) == 0x3) {
         V::VisitUnallocated(instr);
@@ skipping 92 matching lines @@
                     V::VisitFPConditionalSelect(instr);
                     break;
                   }
                   default: UNREACHABLE();
                 }
               }
             }
           }
         } else {
           // Bit 30 == 1 has been handled earlier.
-          ASSERT(instr->Bit(30) == 0);
+          DCHECK(instr->Bit(30) == 0);
           if (instr->Mask(0xA0800000) != 0) {
             V::VisitUnallocated(instr);
           } else {
             V::VisitFPDataProcessing3Source(instr);
           }
         }
       }
     }
   }
 }
 
 
 template<typename V>
 void Decoder<V>::DecodeAdvSIMDLoadStore(Instruction* instr) {
   // TODO(all): Implement Advanced SIMD load/store instruction decode.
-  ASSERT(instr->Bits(29, 25) == 0x6);
+  DCHECK(instr->Bits(29, 25) == 0x6);
   V::VisitUnimplemented(instr);
 }
 
 
 template<typename V>
 void Decoder<V>::DecodeAdvSIMDDataProcessing(Instruction* instr) {
   // TODO(all): Implement Advanced SIMD data processing instruction decode.
-  ASSERT(instr->Bits(27, 25) == 0x7);
+  DCHECK(instr->Bits(27, 25) == 0x7);
   V::VisitUnimplemented(instr);
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM64_DECODER_ARM64_INL_H_