Rename ASSERT* to DCHECK*.

src/arm64/cpu-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // CPU specific code for arm independent of OS goes here.
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_ARM64
 
@@ skipping 41 matching lines @@
   // The code below assumes user space cache operations are allowed. The goal
   // of this routine is to make sure the code generated is visible to the I
   // side of the CPU.
 
   uintptr_t start = reinterpret_cast<uintptr_t>(address);
   // Sizes will be used to generate a mask big enough to cover a pointer.
   CacheLineSizes sizes;
   uintptr_t dsize = sizes.dcache_line_size();
   uintptr_t isize = sizes.icache_line_size();
   // Cache line sizes are always a power of 2.
-  ASSERT(CountSetBits(dsize, 64) == 1);
-  ASSERT(CountSetBits(isize, 64) == 1);
+  DCHECK(CountSetBits(dsize, 64) == 1);
+  DCHECK(CountSetBits(isize, 64) == 1);
   uintptr_t dstart = start & ~(dsize - 1);
   uintptr_t istart = start & ~(isize - 1);
   uintptr_t end = start + length;
 
   __asm__ __volatile__ (  // NOLINT
     // Clean every line of the D cache containing the target data.
     "0:                                \n\t"
     // dc      : Data Cache maintenance
     //    c    : Clean
     //     va  : by (Virtual) Address
@@ skipping 40 matching lines @@
     // This code does not write to memory but without the dependency gcc might
     // move this code before the code is generated.
     : "cc", "memory"
   );  // NOLINT
 #endif
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64