Rename ASSERT* to DCHECK*.

src/arm64/assembler-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
@@ skipping 47 matching lines @@
 
 
 void CpuFeatures::PrintTarget() { }
 void CpuFeatures::PrintFeatures() { }
 
 
 // -----------------------------------------------------------------------------
 // CPURegList utilities.
 
 CPURegister CPURegList::PopLowestIndex() {
-  ASSERT(IsValid());
+  DCHECK(IsValid());
   if (IsEmpty()) {
     return NoCPUReg;
   }
   int index = CountTrailingZeros(list_, kRegListSizeInBits);
-  ASSERT((1 << index) & list_);
+  DCHECK((1 << index) & list_);
   Remove(index);
   return CPURegister::Create(index, size_, type_);
 }
 
 
 CPURegister CPURegList::PopHighestIndex() {
-  ASSERT(IsValid());
+  DCHECK(IsValid());
   if (IsEmpty()) {
     return NoCPUReg;
   }
   int index = CountLeadingZeros(list_, kRegListSizeInBits);
   index = kRegListSizeInBits - 1 - index;
-  ASSERT((1 << index) & list_);
+  DCHECK((1 << index) & list_);
   Remove(index);
   return CPURegister::Create(index, size_, type_);
 }
 
 
 void CPURegList::RemoveCalleeSaved() {
   if (type() == CPURegister::kRegister) {
     Remove(GetCalleeSaved(RegisterSizeInBits()));
   } else if (type() == CPURegister::kFPRegister) {
     Remove(GetCalleeSavedFP(RegisterSizeInBits()));
   } else {
-    ASSERT(type() == CPURegister::kNoRegister);
-    ASSERT(IsEmpty());
+    DCHECK(type() == CPURegister::kNoRegister);
+    DCHECK(IsEmpty());
     // The list must already be empty, so do nothing.
   }
 }
 
 
 CPURegList CPURegList::GetCalleeSaved(unsigned size) {
   return CPURegList(CPURegister::kRegister, size, 19, 29);
 }
 
 
@@ skipping 118 matching lines @@
   const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
 
   for (unsigned i = 0; i < sizeof(regs) / sizeof(regs[0]); i++) {
     if (regs[i].IsRegister()) {
       number_of_valid_regs++;
       unique_regs |= regs[i].Bit();
     } else if (regs[i].IsFPRegister()) {
       number_of_valid_fpregs++;
       unique_fpregs |= regs[i].Bit();
     } else {
-      ASSERT(!regs[i].IsValid());
+      DCHECK(!regs[i].IsValid());
     }
   }
 
   int number_of_unique_regs =
     CountSetBits(unique_regs, sizeof(unique_regs) * kBitsPerByte);
   int number_of_unique_fpregs =
     CountSetBits(unique_fpregs, sizeof(unique_fpregs) * kBitsPerByte);
 
-  ASSERT(number_of_valid_regs >= number_of_unique_regs);
-  ASSERT(number_of_valid_fpregs >= number_of_unique_fpregs);
+  DCHECK(number_of_valid_regs >= number_of_unique_regs);
+  DCHECK(number_of_valid_fpregs >= number_of_unique_fpregs);
 
   return (number_of_valid_regs != number_of_unique_regs) ||
          (number_of_valid_fpregs != number_of_unique_fpregs);
 }
 
 
 bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2,
                         const CPURegister& reg3, const CPURegister& reg4,
                         const CPURegister& reg5, const CPURegister& reg6,
                         const CPURegister& reg7, const CPURegister& reg8) {
-  ASSERT(reg1.IsValid());
+  DCHECK(reg1.IsValid());
   bool match = true;
   match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
   match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
   match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
   match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
   match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1);
   match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1);
   match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1);
   return match;
 }
 
 
 void Immediate::InitializeHandle(Handle<Object> handle) {
   AllowDeferredHandleDereference using_raw_address;
 
   // Verify all Objects referred by code are NOT in new space.
   Object* obj = *handle;
   if (obj->IsHeapObject()) {
-    ASSERT(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));
+    DCHECK(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));
     value_ = reinterpret_cast<intptr_t>(handle.location());
     rmode_ = RelocInfo::EMBEDDED_OBJECT;
   } else {
     STATIC_ASSERT(sizeof(intptr_t) == sizeof(int64_t));
     value_ = reinterpret_cast<intptr_t>(obj);
     rmode_ = RelocInfo::NONE64;
   }
 }
 
 
 bool Operand::NeedsRelocation(const Assembler* assembler) const {
   RelocInfo::Mode rmode = immediate_.rmode();
 
   if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
     return assembler->serializer_enabled();
   }
 
   return !RelocInfo::IsNone(rmode);
 }
 
 
 // Constant Pool.
 void ConstPool::RecordEntry(intptr_t data,
                             RelocInfo::Mode mode) {
-  ASSERT(mode != RelocInfo::COMMENT &&
+  DCHECK(mode != RelocInfo::COMMENT &&
          mode != RelocInfo::POSITION &&
          mode != RelocInfo::STATEMENT_POSITION &&
          mode != RelocInfo::CONST_POOL &&
          mode != RelocInfo::VENEER_POOL &&
          mode != RelocInfo::CODE_AGE_SEQUENCE);
 
   uint64_t raw_data = static_cast<uint64_t>(data);
   int offset = assm_->pc_offset();
   if (IsEmpty()) {
     first_use_ = offset;
@@ skipping 10 matching lines @@
   }
 
   if (EntryCount() > Assembler::kApproxMaxPoolEntryCount) {
     // Request constant pool emission after the next instruction.
     assm_->SetNextConstPoolCheckIn(1);
   }
 }
 
 
 int ConstPool::DistanceToFirstUse() {
-  ASSERT(first_use_ >= 0);
+  DCHECK(first_use_ >= 0);
   return assm_->pc_offset() - first_use_;
 }
 
 
 int ConstPool::MaxPcOffset() {
   // There are no pending entries in the pool so we can never get out of
   // range.
   if (IsEmpty()) return kMaxInt;
 
   // Entries are not necessarily emitted in the order they are added so in the
@@ skipping 27 matching lines @@
   prologue_size += 2 * kInstructionSize;
   prologue_size += IsAligned(assm_->pc_offset() + prologue_size, 8) ?
                    0 : kInstructionSize;
 
   // All entries are 64-bit for now.
   return prologue_size + EntryCount() * kPointerSize;
 }
 
 
 void ConstPool::Emit(bool require_jump) {
-  ASSERT(!assm_->is_const_pool_blocked());
+  DCHECK(!assm_->is_const_pool_blocked());
   // Prevent recursive pool emission and protect from veneer pools.
   Assembler::BlockPoolsScope block_pools(assm_);
 
   int size = SizeIfEmittedAtCurrentPc(require_jump);
   Label size_check;
   assm_->bind(&size_check);
 
   assm_->RecordConstPool(size);
   // Emit the constant pool. It is preceded by an optional branch if
   // require_jump and a header which will:
@@ skipping 28 matching lines @@
   // Emit constant pool entries.
   // TODO(all): currently each relocated constant is 64 bits, consider adding
   // support for 32-bit entries.
   EmitEntries();
   assm_->RecordComment("]");
 
   if (after_pool.is_linked()) {
     assm_->bind(&after_pool);
   }
 
-  ASSERT(assm_->SizeOfCodeGeneratedSince(&size_check) ==
+  DCHECK(assm_->SizeOfCodeGeneratedSince(&size_check) ==
          static_cast<unsigned>(size));
 }
 
 
 void ConstPool::Clear() {
   shared_entries_.clear();
   shared_entries_count = 0;
   unique_entries_.clear();
   first_use_ = -1;
 }
 
 
 bool ConstPool::CanBeShared(RelocInfo::Mode mode) {
   // Constant pool currently does not support 32-bit entries.
-  ASSERT(mode != RelocInfo::NONE32);
+  DCHECK(mode != RelocInfo::NONE32);
 
   return RelocInfo::IsNone(mode) ||
          (!assm_->serializer_enabled() && (mode >= RelocInfo::CELL));
 }
 
 
 void ConstPool::EmitMarker() {
   // A constant pool size is expressed in number of 32-bits words.
   // Currently all entries are 64-bit.
   // + 1 is for the crash guard.
   // + 0/1 for alignment.
   int word_count = EntryCount() * 2 + 1 +
                    (IsAligned(assm_->pc_offset(), 8) ? 0 : 1);
   assm_->Emit(LDR_x_lit                          |
               Assembler::ImmLLiteral(word_count) |
               Assembler::Rt(xzr));
 }
 
 
 MemOperand::PairResult MemOperand::AreConsistentForPair(
     const MemOperand& operandA,
     const MemOperand& operandB,
     int access_size_log2) {
-  ASSERT(access_size_log2 >= 0);
-  ASSERT(access_size_log2 <= 3);
+  DCHECK(access_size_log2 >= 0);
+  DCHECK(access_size_log2 <= 3);
   // Step one: check that they share the same base, that the mode is Offset
   // and that the offset is a multiple of access size.
   if (!operandA.base().Is(operandB.base()) ||
       (operandA.addrmode() != Offset) ||
       (operandB.addrmode() != Offset) ||
       ((operandA.offset() & ((1 << access_size_log2) - 1)) != 0)) {
     return kNotPair;
   }
   // Step two: check that the offsets are contiguous and that the range
   // is OK for ldp/stp.
   if ((operandB.offset() == operandA.offset() + (1 << access_size_log2)) &&
       is_int7(operandA.offset() >> access_size_log2)) {
     return kPairAB;
   }
   if ((operandA.offset() == operandB.offset() + (1 << access_size_log2)) &&
       is_int7(operandB.offset() >> access_size_log2)) {
     return kPairBA;
   }
   return kNotPair;
 }
 
 
 void ConstPool::EmitGuard() {
 #ifdef DEBUG
   Instruction* instr = reinterpret_cast<Instruction*>(assm_->pc());
-  ASSERT(instr->preceding()->IsLdrLiteralX() &&
+  DCHECK(instr->preceding()->IsLdrLiteralX() &&
          instr->preceding()->Rt() == xzr.code());
 #endif
   assm_->EmitPoolGuard();
 }
 
 
 void ConstPool::EmitEntries() {
-  ASSERT(IsAligned(assm_->pc_offset(), 8));
+  DCHECK(IsAligned(assm_->pc_offset(), 8));
 
   typedef std::multimap<uint64_t, int>::const_iterator SharedEntriesIterator;
   SharedEntriesIterator value_it;
   // Iterate through the keys (constant pool values).
   for (value_it = shared_entries_.begin();
        value_it != shared_entries_.end();
        value_it = shared_entries_.upper_bound(value_it->first)) {
     std::pair<SharedEntriesIterator, SharedEntriesIterator> range;
     uint64_t data = value_it->first;
     range = shared_entries_.equal_range(data);
     SharedEntriesIterator offset_it;
     // Iterate through the offsets of a given key.
     for (offset_it = range.first; offset_it != range.second; offset_it++) {
       Instruction* instr = assm_->InstructionAt(offset_it->second);
 
       // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
-      ASSERT(instr->IsLdrLiteral() && instr->ImmLLiteral() == 0);
+      DCHECK(instr->IsLdrLiteral() && instr->ImmLLiteral() == 0);
       instr->SetImmPCOffsetTarget(assm_->pc());
     }
     assm_->dc64(data);
   }
   shared_entries_.clear();
   shared_entries_count = 0;
 
   // Emit unique entries.
   std::vector<std::pair<uint64_t, int> >::const_iterator unique_it;
   for (unique_it = unique_entries_.begin();
        unique_it != unique_entries_.end();
        unique_it++) {
     Instruction* instr = assm_->InstructionAt(unique_it->second);
 
     // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
-    ASSERT(instr->IsLdrLiteral() && instr->ImmLLiteral() == 0);
+    DCHECK(instr->IsLdrLiteral() && instr->ImmLLiteral() == 0);
     instr->SetImmPCOffsetTarget(assm_->pc());
     assm_->dc64(unique_it->first);
   }
   unique_entries_.clear();
   first_use_ = -1;
 }
 
 
 // Assembler
 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
     : AssemblerBase(isolate, buffer, buffer_size),
       constpool_(this),
       recorded_ast_id_(TypeFeedbackId::None()),
       unresolved_branches_(),
       positions_recorder_(this) {
   const_pool_blocked_nesting_ = 0;
   veneer_pool_blocked_nesting_ = 0;
   Reset();
 }
 
 
 Assembler::~Assembler() {
-  ASSERT(constpool_.IsEmpty());
-  ASSERT(const_pool_blocked_nesting_ == 0);
-  ASSERT(veneer_pool_blocked_nesting_ == 0);
+  DCHECK(constpool_.IsEmpty());
+  DCHECK(const_pool_blocked_nesting_ == 0);
+  DCHECK(veneer_pool_blocked_nesting_ == 0);
 }
 
 
 void Assembler::Reset() {
 #ifdef DEBUG
-  ASSERT((pc_ >= buffer_) && (pc_ < buffer_ + buffer_size_));
-  ASSERT(const_pool_blocked_nesting_ == 0);
-  ASSERT(veneer_pool_blocked_nesting_ == 0);
-  ASSERT(unresolved_branches_.empty());
+  DCHECK((pc_ >= buffer_) && (pc_ < buffer_ + buffer_size_));
+  DCHECK(const_pool_blocked_nesting_ == 0);
+  DCHECK(veneer_pool_blocked_nesting_ == 0);
+  DCHECK(unresolved_branches_.empty());
   memset(buffer_, 0, pc_ - buffer_);
 #endif
   pc_ = buffer_;
   reloc_info_writer.Reposition(reinterpret_cast<byte*>(buffer_ + buffer_size_),
                                reinterpret_cast<byte*>(pc_));
   constpool_.Clear();
   next_constant_pool_check_ = 0;
   next_veneer_pool_check_ = kMaxInt;
   no_const_pool_before_ = 0;
   ClearRecordedAstId();
 }
 
 
 void Assembler::GetCode(CodeDesc* desc) {
   // Emit constant pool if necessary.
   CheckConstPool(true, false);
-  ASSERT(constpool_.IsEmpty());
+  DCHECK(constpool_.IsEmpty());
 
   // Set up code descriptor.
   if (desc) {
     desc->buffer = reinterpret_cast<byte*>(buffer_);
     desc->buffer_size = buffer_size_;
     desc->instr_size = pc_offset();
     desc->reloc_size = (reinterpret_cast<byte*>(buffer_) + buffer_size_) -
                        reloc_info_writer.pos();
     desc->origin = this;
   }
 }
 
 
 void Assembler::Align(int m) {
-  ASSERT(m >= 4 && IsPowerOf2(m));
+  DCHECK(m >= 4 && IsPowerOf2(m));
   while ((pc_offset() & (m - 1)) != 0) {
     nop();
   }
 }
 
 
 void Assembler::CheckLabelLinkChain(Label const * label) {
 #ifdef DEBUG
   if (label->is_linked()) {
     int linkoffset = label->pos();
     bool end_of_chain = false;
     while (!end_of_chain) {
       Instruction * link = InstructionAt(linkoffset);
       int linkpcoffset = link->ImmPCOffset();
       int prevlinkoffset = linkoffset + linkpcoffset;
 
       end_of_chain = (linkoffset == prevlinkoffset);
       linkoffset = linkoffset + linkpcoffset;
     }
   }
 #endif
 }
 
 
 void Assembler::RemoveBranchFromLabelLinkChain(Instruction* branch,
                                                Label* label,
                                                Instruction* label_veneer) {
-  ASSERT(label->is_linked());
+  DCHECK(label->is_linked());
 
   CheckLabelLinkChain(label);
 
   Instruction* link = InstructionAt(label->pos());
   Instruction* prev_link = link;
   Instruction* next_link;
   bool end_of_chain = false;
 
   while (link != branch && !end_of_chain) {
     next_link = link->ImmPCOffsetTarget();
     end_of_chain = (link == next_link);
     prev_link = link;
     link = next_link;
   }
 
-  ASSERT(branch == link);
+  DCHECK(branch == link);
   next_link = branch->ImmPCOffsetTarget();
 
   if (branch == prev_link) {
     // The branch is the first instruction in the chain.
     if (branch == next_link) {
       // It is also the last instruction in the chain, so it is the only branch
       // currently referring to this label.
       label->Unuse();
     } else {
       label->link_to(reinterpret_cast<byte*>(next_link) - buffer_);
@@ skipping 45 matching lines @@
 
   CheckLabelLinkChain(label);
 }
 
 
 void Assembler::bind(Label* label) {
   // Bind label to the address at pc_. All instructions (most likely branches)
   // that are linked to this label will be updated to point to the newly-bound
   // label.
 
-  ASSERT(!label->is_near_linked());
-  ASSERT(!label->is_bound());
+  DCHECK(!label->is_near_linked());
+  DCHECK(!label->is_bound());
 
   DeleteUnresolvedBranchInfoForLabel(label);
 
   // If the label is linked, the link chain looks something like this:
   //
   // |--I----I-------I-------L
   // |---------------------->| pc_offset
   // |-------------->|         linkoffset = label->pos()
   //         |<------|         link->ImmPCOffset()
   // |------>|                 prevlinkoffset = linkoffset + link->ImmPCOffset()
   //
   // On each iteration, the last link is updated and then removed from the
   // chain until only one remains. At that point, the label is bound.
   //
   // If the label is not linked, no preparation is required before binding.
   while (label->is_linked()) {
     int linkoffset = label->pos();
     Instruction* link = InstructionAt(linkoffset);
     int prevlinkoffset = linkoffset + link->ImmPCOffset();
 
     CheckLabelLinkChain(label);
 
-    ASSERT(linkoffset >= 0);
-    ASSERT(linkoffset < pc_offset());
-    ASSERT((linkoffset > prevlinkoffset) ||
+    DCHECK(linkoffset >= 0);
+    DCHECK(linkoffset < pc_offset());
+    DCHECK((linkoffset > prevlinkoffset) ||
            (linkoffset - prevlinkoffset == kStartOfLabelLinkChain));
-    ASSERT(prevlinkoffset >= 0);
+    DCHECK(prevlinkoffset >= 0);
 
     // Update the link to point to the label.
     link->SetImmPCOffsetTarget(reinterpret_cast<Instruction*>(pc_));
 
     // Link the label to the previous link in the chain.
     if (linkoffset - prevlinkoffset == kStartOfLabelLinkChain) {
       // We hit kStartOfLabelLinkChain, so the chain is fully processed.
       label->Unuse();
     } else {
       // Update the label for the next iteration.
       label->link_to(prevlinkoffset);
     }
   }
   label->bind_to(pc_offset());
 
-  ASSERT(label->is_bound());
-  ASSERT(!label->is_linked());
+  DCHECK(label->is_bound());
+  DCHECK(!label->is_linked());
 }
 
 
 int Assembler::LinkAndGetByteOffsetTo(Label* label) {
-  ASSERT(sizeof(*pc_) == 1);
+  DCHECK(sizeof(*pc_) == 1);
   CheckLabelLinkChain(label);
 
   int offset;
   if (label->is_bound()) {
     // The label is bound, so it does not need to be updated. Referring
     // instructions must link directly to the label as they will not be
     // updated.
     //
     // In this case, label->pos() returns the offset of the label from the
     // start of the buffer.
     //
     // Note that offset can be zero for self-referential instructions. (This
     // could be useful for ADR, for example.)
     offset = label->pos() - pc_offset();
-    ASSERT(offset <= 0);
+    DCHECK(offset <= 0);
   } else {
     if (label->is_linked()) {
       // The label is linked, so the referring instruction should be added onto
       // the end of the label's link chain.
       //
       // In this case, label->pos() returns the offset of the last linked
       // instruction from the start of the buffer.
       offset = label->pos() - pc_offset();
-      ASSERT(offset != kStartOfLabelLinkChain);
+      DCHECK(offset != kStartOfLabelLinkChain);
       // Note that the offset here needs to be PC-relative only so that the
       // first instruction in a buffer can link to an unbound label. Otherwise,
       // the offset would be 0 for this case, and 0 is reserved for
       // kStartOfLabelLinkChain.
     } else {
       // The label is unused, so it now becomes linked and the referring
       // instruction is at the start of the new link chain.
       offset = kStartOfLabelLinkChain;
     }
     // The instruction at pc is now the last link in the label's chain.
     label->link_to(pc_offset());
   }
 
   return offset;
 }
 
 
 void Assembler::DeleteUnresolvedBranchInfoForLabelTraverse(Label* label) {
-  ASSERT(label->is_linked());
+  DCHECK(label->is_linked());
   CheckLabelLinkChain(label);
 
   int link_offset = label->pos();
   int link_pcoffset;
   bool end_of_chain = false;
 
   while (!end_of_chain) {
     Instruction * link = InstructionAt(link_offset);
     link_pcoffset = link->ImmPCOffset();
 
@@ skipping 14 matching lines @@
     }
 
     end_of_chain = (link_pcoffset == 0);
     link_offset = link_offset + link_pcoffset;
   }
 }
 
 
 void Assembler::DeleteUnresolvedBranchInfoForLabel(Label* label) {
   if (unresolved_branches_.empty()) {
-    ASSERT(next_veneer_pool_check_ == kMaxInt);
+    DCHECK(next_veneer_pool_check_ == kMaxInt);
     return;
   }
 
   if (label->is_linked()) {
     // Branches to this label will be resolved when the label is bound, normally
     // just after all the associated info has been deleted.
     DeleteUnresolvedBranchInfoForLabelTraverse(label);
   }
   if (unresolved_branches_.empty()) {
     next_veneer_pool_check_ = kMaxInt;
   } else {
     next_veneer_pool_check_ =
       unresolved_branches_first_limit() - kVeneerDistanceCheckMargin;
   }
 }
 
 
 void Assembler::StartBlockConstPool() {
   if (const_pool_blocked_nesting_++ == 0) {
     // Prevent constant pool checks happening by setting the next check to
     // the biggest possible offset.
     next_constant_pool_check_ = kMaxInt;
   }
 }
 
 
 void Assembler::EndBlockConstPool() {
   if (--const_pool_blocked_nesting_ == 0) {
     // Check the constant pool hasn't been blocked for too long.
-    ASSERT(pc_offset() < constpool_.MaxPcOffset());
+    DCHECK(pc_offset() < constpool_.MaxPcOffset());
     // Two cases:
     //  * no_const_pool_before_ >= next_constant_pool_check_ and the emission is
     //    still blocked
     //  * no_const_pool_before_ < next_constant_pool_check_ and the next emit
     //    will trigger a check.
     next_constant_pool_check_ = no_const_pool_before_;
   }
 }
 
 
 bool Assembler::is_const_pool_blocked() const {
   return (const_pool_blocked_nesting_ > 0) ||
          (pc_offset() < no_const_pool_before_);
 }
 
 
 bool Assembler::IsConstantPoolAt(Instruction* instr) {
   // The constant pool marker is made of two instructions. These instructions
   // will never be emitted by the JIT, so checking for the first one is enough:
   // 0: ldr xzr, #<size of pool>
   bool result = instr->IsLdrLiteralX() && (instr->Rt() == xzr.code());
 
   // It is still worth asserting the marker is complete.
   // 4: blr xzr
-  ASSERT(!result || (instr->following()->IsBranchAndLinkToRegister() &&
+  DCHECK(!result || (instr->following()->IsBranchAndLinkToRegister() &&
                      instr->following()->Rn() == xzr.code()));
 
   return result;
 }
 
 
 int Assembler::ConstantPoolSizeAt(Instruction* instr) {
 #ifdef USE_SIMULATOR
   // Assembler::debug() embeds constants directly into the instruction stream.
   // Although this is not a genuine constant pool, treat it like one to avoid
@@ skipping 28 matching lines @@
 
 
 void Assembler::StartBlockVeneerPool() {
   ++veneer_pool_blocked_nesting_;
 }
 
 
 void Assembler::EndBlockVeneerPool() {
   if (--veneer_pool_blocked_nesting_ == 0) {
     // Check the veneer pool hasn't been blocked for too long.
-    ASSERT(unresolved_branches_.empty() ||
+    DCHECK(unresolved_branches_.empty() ||
            (pc_offset() < unresolved_branches_first_limit()));
   }
 }
 
 
 void Assembler::br(const Register& xn) {
   positions_recorder()->WriteRecordedPositions();
-  ASSERT(xn.Is64Bits());
+  DCHECK(xn.Is64Bits());
   Emit(BR | Rn(xn));
 }
 
 
 void Assembler::blr(const Register& xn) {
   positions_recorder()->WriteRecordedPositions();
-  ASSERT(xn.Is64Bits());
+  DCHECK(xn.Is64Bits());
   // The pattern 'blr xzr' is used as a guard to detect when execution falls
   // through the constant pool. It should not be emitted.
-  ASSERT(!xn.Is(xzr));
+  DCHECK(!xn.Is(xzr));
   Emit(BLR | Rn(xn));
 }
 
 
 void Assembler::ret(const Register& xn) {
   positions_recorder()->WriteRecordedPositions();
-  ASSERT(xn.Is64Bits());
+  DCHECK(xn.Is64Bits());
   Emit(RET | Rn(xn));
 }
 
 
 void Assembler::b(int imm26) {
   Emit(B | ImmUncondBranch(imm26));
 }
 
 
 void Assembler::b(Label* label) {
@@ skipping 50 matching lines @@
                      Label* label) {
   positions_recorder()->WriteRecordedPositions();
   cbnz(rt, LinkAndGetInstructionOffsetTo(label));
 }
 
 
 void Assembler::tbz(const Register& rt,
                     unsigned bit_pos,
                     int imm14) {
   positions_recorder()->WriteRecordedPositions();
-  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
+  DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
   Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
 }
 
 
 void Assembler::tbz(const Register& rt,
                     unsigned bit_pos,
                     Label* label) {
   positions_recorder()->WriteRecordedPositions();
   tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
 }
 
 
 void Assembler::tbnz(const Register& rt,
                      unsigned bit_pos,
                      int imm14) {
   positions_recorder()->WriteRecordedPositions();
-  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
+  DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
   Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
 }
 
 
 void Assembler::tbnz(const Register& rt,
                      unsigned bit_pos,
                      Label* label) {
   positions_recorder()->WriteRecordedPositions();
   tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
 }
 
 
 void Assembler::adr(const Register& rd, int imm21) {
-  ASSERT(rd.Is64Bits());
+  DCHECK(rd.Is64Bits());
   Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd));
 }
 
 
 void Assembler::adr(const Register& rd, Label* label) {
   adr(rd, LinkAndGetByteOffsetTo(label));
 }
 
 
 void Assembler::add(const Register& rd,
@@ skipping 148 matching lines @@
 void Assembler::eon(const Register& rd,
                     const Register& rn,
                     const Operand& operand) {
   Logical(rd, rn, operand, EON);
 }
 
 
 void Assembler::lslv(const Register& rd,
                      const Register& rn,
                      const Register& rm) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(rd.SizeInBits() == rm.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rm.SizeInBits());
   Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::lsrv(const Register& rd,
                      const Register& rn,
                      const Register& rm) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(rd.SizeInBits() == rm.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rm.SizeInBits());
   Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::asrv(const Register& rd,
                      const Register& rn,
                      const Register& rm) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(rd.SizeInBits() == rm.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rm.SizeInBits());
   Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::rorv(const Register& rd,
                      const Register& rn,
                      const Register& rm) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(rd.SizeInBits() == rm.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rm.SizeInBits());
   Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
 }
 
 
 // Bitfield operations.
 void Assembler::bfm(const Register& rd,
                      const Register& rn,
                      unsigned immr,
                      unsigned imms) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
   Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
   Emit(SF(rd) | BFM | N |
        ImmR(immr, rd.SizeInBits()) |
        ImmS(imms, rn.SizeInBits()) |
        Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::sbfm(const Register& rd,
                      const Register& rn,
                      unsigned immr,
                      unsigned imms) {
-  ASSERT(rd.Is64Bits() || rn.Is32Bits());
+  DCHECK(rd.Is64Bits() || rn.Is32Bits());
   Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
   Emit(SF(rd) | SBFM | N |
        ImmR(immr, rd.SizeInBits()) |
        ImmS(imms, rn.SizeInBits()) |
        Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::ubfm(const Register& rd,
                      const Register& rn,
                      unsigned immr,
                      unsigned imms) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
   Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
   Emit(SF(rd) | UBFM | N |
        ImmR(immr, rd.SizeInBits()) |
        ImmS(imms, rn.SizeInBits()) |
        Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::extr(const Register& rd,
                      const Register& rn,
                      const Register& rm,
                      unsigned lsb) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(rd.SizeInBits() == rm.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rm.SizeInBits());
   Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
   Emit(SF(rd) | EXTR | N | Rm(rm) |
        ImmS(lsb, rn.SizeInBits()) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::csel(const Register& rd,
                      const Register& rn,
                      const Register& rm,
                      Condition cond) {
@@ skipping 19 matching lines @@
 
 void Assembler::csneg(const Register& rd,
                       const Register& rn,
                       const Register& rm,
                       Condition cond) {
   ConditionalSelect(rd, rn, rm, cond, CSNEG);
 }
 
 
 void Assembler::cset(const Register &rd, Condition cond) {
-  ASSERT((cond != al) && (cond != nv));
+  DCHECK((cond != al) && (cond != nv));
   Register zr = AppropriateZeroRegFor(rd);
   csinc(rd, zr, zr, NegateCondition(cond));
 }
 
 
 void Assembler::csetm(const Register &rd, Condition cond) {
-  ASSERT((cond != al) && (cond != nv));
+  DCHECK((cond != al) && (cond != nv));
   Register zr = AppropriateZeroRegFor(rd);
   csinv(rd, zr, zr, NegateCondition(cond));
 }
 
 
 void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) {
-  ASSERT((cond != al) && (cond != nv));
+  DCHECK((cond != al) && (cond != nv));
   csinc(rd, rn, rn, NegateCondition(cond));
 }
 
 
 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) {
-  ASSERT((cond != al) && (cond != nv));
+  DCHECK((cond != al) && (cond != nv));
   csinv(rd, rn, rn, NegateCondition(cond));
 }
 
 
 void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) {
-  ASSERT((cond != al) && (cond != nv));
+  DCHECK((cond != al) && (cond != nv));
   csneg(rd, rn, rn, NegateCondition(cond));
 }
 
 
 void Assembler::ConditionalSelect(const Register& rd,
                                   const Register& rn,
                                   const Register& rm,
                                   Condition cond,
                                   ConditionalSelectOp op) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(rd.SizeInBits() == rm.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rm.SizeInBits());
   Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::ccmn(const Register& rn,
                      const Operand& operand,
                      StatusFlags nzcv,
                      Condition cond) {
   ConditionalCompare(rn, operand, nzcv, cond, CCMN);
 }
@@ skipping 12 matching lines @@
                                       const Register& rm,
                                       const Register& ra,
                                       DataProcessing3SourceOp op) {
   Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::mul(const Register& rd,
                     const Register& rn,
                     const Register& rm) {
-  ASSERT(AreSameSizeAndType(rd, rn, rm));
+  DCHECK(AreSameSizeAndType(rd, rn, rm));
   Register zr = AppropriateZeroRegFor(rn);
   DataProcessing3Source(rd, rn, rm, zr, MADD);
 }
 
 
 void Assembler::madd(const Register& rd,
                      const Register& rn,
                      const Register& rm,
                      const Register& ra) {
-  ASSERT(AreSameSizeAndType(rd, rn, rm, ra));
+  DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
   DataProcessing3Source(rd, rn, rm, ra, MADD);
 }
 
 
 void Assembler::mneg(const Register& rd,
                      const Register& rn,
                      const Register& rm) {
-  ASSERT(AreSameSizeAndType(rd, rn, rm));
+  DCHECK(AreSameSizeAndType(rd, rn, rm));
   Register zr = AppropriateZeroRegFor(rn);
   DataProcessing3Source(rd, rn, rm, zr, MSUB);
 }
 
 
 void Assembler::msub(const Register& rd,
                      const Register& rn,
                      const Register& rm,
                      const Register& ra) {
-  ASSERT(AreSameSizeAndType(rd, rn, rm, ra));
+  DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
   DataProcessing3Source(rd, rn, rm, ra, MSUB);
 }
 
 
 void Assembler::smaddl(const Register& rd,
                        const Register& rn,
                        const Register& rm,
                        const Register& ra) {
-  ASSERT(rd.Is64Bits() && ra.Is64Bits());
-  ASSERT(rn.Is32Bits() && rm.Is32Bits());
+  DCHECK(rd.Is64Bits() && ra.Is64Bits());
+  DCHECK(rn.Is32Bits() && rm.Is32Bits());
   DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
 }
 
 
 void Assembler::smsubl(const Register& rd,
                        const Register& rn,
                        const Register& rm,
                        const Register& ra) {
-  ASSERT(rd.Is64Bits() && ra.Is64Bits());
-  ASSERT(rn.Is32Bits() && rm.Is32Bits());
+  DCHECK(rd.Is64Bits() && ra.Is64Bits());
+  DCHECK(rn.Is32Bits() && rm.Is32Bits());
   DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
 }
 
 
 void Assembler::umaddl(const Register& rd,
                        const Register& rn,
                        const Register& rm,
                        const Register& ra) {
-  ASSERT(rd.Is64Bits() && ra.Is64Bits());
-  ASSERT(rn.Is32Bits() && rm.Is32Bits());
+  DCHECK(rd.Is64Bits() && ra.Is64Bits());
+  DCHECK(rn.Is32Bits() && rm.Is32Bits());
   DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
 }
 
 
 void Assembler::umsubl(const Register& rd,
                        const Register& rn,
                        const Register& rm,
                        const Register& ra) {
-  ASSERT(rd.Is64Bits() && ra.Is64Bits());
-  ASSERT(rn.Is32Bits() && rm.Is32Bits());
+  DCHECK(rd.Is64Bits() && ra.Is64Bits());
+  DCHECK(rn.Is32Bits() && rm.Is32Bits());
   DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
 }
 
 
 void Assembler::smull(const Register& rd,
                       const Register& rn,
                       const Register& rm) {
-  ASSERT(rd.Is64Bits());
-  ASSERT(rn.Is32Bits() && rm.Is32Bits());
+  DCHECK(rd.Is64Bits());
+  DCHECK(rn.Is32Bits() && rm.Is32Bits());
   DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x);
 }
 
 
 void Assembler::smulh(const Register& rd,
                       const Register& rn,
                       const Register& rm) {
-  ASSERT(AreSameSizeAndType(rd, rn, rm));
+  DCHECK(AreSameSizeAndType(rd, rn, rm));
   DataProcessing3Source(rd, rn, rm, xzr, SMULH_x);
 }
 
 
 void Assembler::sdiv(const Register& rd,
                      const Register& rn,
                      const Register& rm) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(rd.SizeInBits() == rm.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rm.SizeInBits());
   Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::udiv(const Register& rd,
                      const Register& rn,
                      const Register& rm) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(rd.SizeInBits() == rm.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rm.SizeInBits());
   Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::rbit(const Register& rd,
                      const Register& rn) {
   DataProcessing1Source(rd, rn, RBIT);
 }
 
 
 void Assembler::rev16(const Register& rd,
                       const Register& rn) {
   DataProcessing1Source(rd, rn, REV16);
 }
 
 
 void Assembler::rev32(const Register& rd,
                       const Register& rn) {
-  ASSERT(rd.Is64Bits());
+  DCHECK(rd.Is64Bits());
   DataProcessing1Source(rd, rn, REV);
 }
 
 
 void Assembler::rev(const Register& rd,
                     const Register& rn) {
   DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w);
 }
 
 
@@ skipping 19 matching lines @@
 void Assembler::stp(const CPURegister& rt,
                     const CPURegister& rt2,
                     const MemOperand& dst) {
   LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2));
 }
 
 
 void Assembler::ldpsw(const Register& rt,
                       const Register& rt2,
                       const MemOperand& src) {
-  ASSERT(rt.Is64Bits());
+  DCHECK(rt.Is64Bits());
   LoadStorePair(rt, rt2, src, LDPSW_x);
 }
 
 
 void Assembler::LoadStorePair(const CPURegister& rt,
                               const CPURegister& rt2,
                               const MemOperand& addr,
                               LoadStorePairOp op) {
   // 'rt' and 'rt2' can only be aliased for stores.
-  ASSERT(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2));
-  ASSERT(AreSameSizeAndType(rt, rt2));
+  DCHECK(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2));
+  DCHECK(AreSameSizeAndType(rt, rt2));
 
   Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) |
                 ImmLSPair(addr.offset(), CalcLSPairDataSize(op));
 
   Instr addrmodeop;
   if (addr.IsImmediateOffset()) {
     addrmodeop = LoadStorePairOffsetFixed;
   } else {
     // Pre-index and post-index modes.
-    ASSERT(!rt.Is(addr.base()));
-    ASSERT(!rt2.Is(addr.base()));
-    ASSERT(addr.offset() != 0);
+    DCHECK(!rt.Is(addr.base()));
+    DCHECK(!rt2.Is(addr.base()));
+    DCHECK(addr.offset() != 0);
     if (addr.IsPreIndex()) {
       addrmodeop = LoadStorePairPreIndexFixed;
     } else {
-      ASSERT(addr.IsPostIndex());
+      DCHECK(addr.IsPostIndex());
       addrmodeop = LoadStorePairPostIndexFixed;
     }
   }
   Emit(addrmodeop | memop);
 }
 
 
 void Assembler::ldnp(const CPURegister& rt,
                      const CPURegister& rt2,
                      const MemOperand& src) {
   LoadStorePairNonTemporal(rt, rt2, src,
                            LoadPairNonTemporalOpFor(rt, rt2));
 }
 
 
 void Assembler::stnp(const CPURegister& rt,
                      const CPURegister& rt2,
                      const MemOperand& dst) {
   LoadStorePairNonTemporal(rt, rt2, dst,
                            StorePairNonTemporalOpFor(rt, rt2));
 }
 
 
 void Assembler::LoadStorePairNonTemporal(const CPURegister& rt,
                                          const CPURegister& rt2,
                                          const MemOperand& addr,
                                          LoadStorePairNonTemporalOp op) {
-  ASSERT(!rt.Is(rt2));
-  ASSERT(AreSameSizeAndType(rt, rt2));
-  ASSERT(addr.IsImmediateOffset());
+  DCHECK(!rt.Is(rt2));
+  DCHECK(AreSameSizeAndType(rt, rt2));
+  DCHECK(addr.IsImmediateOffset());
 
   LSDataSize size = CalcLSPairDataSize(
     static_cast<LoadStorePairOp>(op & LoadStorePairMask));
   Emit(op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) |
        ImmLSPair(addr.offset(), size));
 }
 
 
 // Memory instructions.
 void Assembler::ldrb(const Register& rt, const MemOperand& src) {
@@ skipping 30 matching lines @@
   LoadStore(rt, src, LoadOpFor(rt));
 }
 
 
 void Assembler::str(const CPURegister& rt, const MemOperand& src) {
   LoadStore(rt, src, StoreOpFor(rt));
 }
 
 
 void Assembler::ldrsw(const Register& rt, const MemOperand& src) {
-  ASSERT(rt.Is64Bits());
+  DCHECK(rt.Is64Bits());
   LoadStore(rt, src, LDRSW_x);
 }
 
 
 void Assembler::ldr_pcrel(const CPURegister& rt, int imm19) {
   // The pattern 'ldr xzr, #offset' is used to indicate the beginning of a
   // constant pool. It should not be emitted.
-  ASSERT(!rt.IsZero());
+  DCHECK(!rt.IsZero());
   Emit(LoadLiteralOpFor(rt) | ImmLLiteral(imm19) | Rt(rt));
 }
 
 
 void Assembler::ldr(const CPURegister& rt, const Immediate& imm) {
   // Currently we only support 64-bit literals.
-  ASSERT(rt.Is64Bits());
+  DCHECK(rt.Is64Bits());
 
   RecordRelocInfo(imm.rmode(), imm.value());
   BlockConstPoolFor(1);
   // The load will be patched when the constpool is emitted, patching code
   // expect a load literal with offset 0.
   ldr_pcrel(rt, 0);
 }
 
 
 void Assembler::mov(const Register& rd, const Register& rm) {
   // Moves involving the stack pointer are encoded as add immediate with
   // second operand of zero. Otherwise, orr with first operand zr is
   // used.
   if (rd.IsSP() || rm.IsSP()) {
     add(rd, rm, 0);
   } else {
     orr(rd, AppropriateZeroRegFor(rd), rm);
   }
 }
 
 
 void Assembler::mvn(const Register& rd, const Operand& operand) {
   orn(rd, AppropriateZeroRegFor(rd), operand);
 }
 
 
 void Assembler::mrs(const Register& rt, SystemRegister sysreg) {
-  ASSERT(rt.Is64Bits());
+  DCHECK(rt.Is64Bits());
   Emit(MRS | ImmSystemRegister(sysreg) | Rt(rt));
 }
 
 
 void Assembler::msr(SystemRegister sysreg, const Register& rt) {
-  ASSERT(rt.Is64Bits());
+  DCHECK(rt.Is64Bits());
   Emit(MSR | Rt(rt) | ImmSystemRegister(sysreg));
 }
 
 
 void Assembler::hint(SystemHint code) {
   Emit(HINT | ImmHint(code) | Rt(xzr));
 }
 
 
 void Assembler::dmb(BarrierDomain domain, BarrierType type) {
   Emit(DMB | ImmBarrierDomain(domain) | ImmBarrierType(type));
 }
 
 
 void Assembler::dsb(BarrierDomain domain, BarrierType type) {
   Emit(DSB | ImmBarrierDomain(domain) | ImmBarrierType(type));
 }
 
 
 void Assembler::isb() {
   Emit(ISB | ImmBarrierDomain(FullSystem) | ImmBarrierType(BarrierAll));
 }
 
 
 void Assembler::fmov(FPRegister fd, double imm) {
-  ASSERT(fd.Is64Bits());
-  ASSERT(IsImmFP64(imm));
+  DCHECK(fd.Is64Bits());
+  DCHECK(IsImmFP64(imm));
   Emit(FMOV_d_imm | Rd(fd) | ImmFP64(imm));
 }
 
 
 void Assembler::fmov(FPRegister fd, float imm) {
-  ASSERT(fd.Is32Bits());
-  ASSERT(IsImmFP32(imm));
+  DCHECK(fd.Is32Bits());
+  DCHECK(IsImmFP32(imm));
   Emit(FMOV_s_imm | Rd(fd) | ImmFP32(imm));
 }
 
 
 void Assembler::fmov(Register rd, FPRegister fn) {
-  ASSERT(rd.SizeInBits() == fn.SizeInBits());
+  DCHECK(rd.SizeInBits() == fn.SizeInBits());
   FPIntegerConvertOp op = rd.Is32Bits() ? FMOV_ws : FMOV_xd;
   Emit(op | Rd(rd) | Rn(fn));
 }
 
 
 void Assembler::fmov(FPRegister fd, Register rn) {
-  ASSERT(fd.SizeInBits() == rn.SizeInBits());
+  DCHECK(fd.SizeInBits() == rn.SizeInBits());
   FPIntegerConvertOp op = fd.Is32Bits() ? FMOV_sw : FMOV_dx;
   Emit(op | Rd(fd) | Rn(rn));
 }
 
 
 void Assembler::fmov(FPRegister fd, FPRegister fn) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
   Emit(FPType(fd) | FMOV | Rd(fd) | Rn(fn));
 }
 
 
 void Assembler::fadd(const FPRegister& fd,
                      const FPRegister& fn,
                      const FPRegister& fm) {
   FPDataProcessing2Source(fd, fn, fm, FADD);
 }
 
@@ skipping 74 matching lines @@
 
 void Assembler::fminnm(const FPRegister& fd,
                        const FPRegister& fn,
                        const FPRegister& fm) {
   FPDataProcessing2Source(fd, fn, fm, FMINNM);
 }
 
 
 void Assembler::fabs(const FPRegister& fd,
                      const FPRegister& fn) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
   FPDataProcessing1Source(fd, fn, FABS);
 }
 
 
 void Assembler::fneg(const FPRegister& fd,
                      const FPRegister& fn) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
   FPDataProcessing1Source(fd, fn, FNEG);
 }
 
 
 void Assembler::fsqrt(const FPRegister& fd,
                       const FPRegister& fn) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
   FPDataProcessing1Source(fd, fn, FSQRT);
 }
 
 
 void Assembler::frinta(const FPRegister& fd,
                        const FPRegister& fn) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
   FPDataProcessing1Source(fd, fn, FRINTA);
 }
 
 
 void Assembler::frintm(const FPRegister& fd,
                        const FPRegister& fn) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
   FPDataProcessing1Source(fd, fn, FRINTM);
 }
 
 
 void Assembler::frintn(const FPRegister& fd,
                        const FPRegister& fn) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
   FPDataProcessing1Source(fd, fn, FRINTN);
 }
 
 
 void Assembler::frintz(const FPRegister& fd,
                        const FPRegister& fn) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
   FPDataProcessing1Source(fd, fn, FRINTZ);
 }
 
 
 void Assembler::fcmp(const FPRegister& fn,
                      const FPRegister& fm) {
-  ASSERT(fn.SizeInBits() == fm.SizeInBits());
+  DCHECK(fn.SizeInBits() == fm.SizeInBits());
   Emit(FPType(fn) | FCMP | Rm(fm) | Rn(fn));
 }
 
 
 void Assembler::fcmp(const FPRegister& fn,
                      double value) {
   USE(value);
   // Although the fcmp instruction can strictly only take an immediate value of
   // +0.0, we don't need to check for -0.0 because the sign of 0.0 doesn't
   // affect the result of the comparison.
-  ASSERT(value == 0.0);
+  DCHECK(value == 0.0);
   Emit(FPType(fn) | FCMP_zero | Rn(fn));
 }
 
 
 void Assembler::fccmp(const FPRegister& fn,
                       const FPRegister& fm,
                       StatusFlags nzcv,
                       Condition cond) {
-  ASSERT(fn.SizeInBits() == fm.SizeInBits());
+  DCHECK(fn.SizeInBits() == fm.SizeInBits());
   Emit(FPType(fn) | FCCMP | Rm(fm) | Cond(cond) | Rn(fn) | Nzcv(nzcv));
 }
 
 
 void Assembler::fcsel(const FPRegister& fd,
                       const FPRegister& fn,
                       const FPRegister& fm,
                       Condition cond) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
-  ASSERT(fd.SizeInBits() == fm.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fm.SizeInBits());
   Emit(FPType(fd) | FCSEL | Rm(fm) | Cond(cond) | Rn(fn) | Rd(fd));
 }
 
 
 void Assembler::FPConvertToInt(const Register& rd,
                                const FPRegister& fn,
                                FPIntegerConvertOp op) {
   Emit(SF(rd) | FPType(fn) | op | Rn(fn) | Rd(rd));
 }
 
 
 void Assembler::fcvt(const FPRegister& fd,
                      const FPRegister& fn) {
   if (fd.Is64Bits()) {
     // Convert float to double.
-    ASSERT(fn.Is32Bits());
+    DCHECK(fn.Is32Bits());
     FPDataProcessing1Source(fd, fn, FCVT_ds);
   } else {
     // Convert double to float.
-    ASSERT(fn.Is64Bits());
+    DCHECK(fn.Is64Bits());
     FPDataProcessing1Source(fd, fn, FCVT_sd);
   }
 }
 
 
 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) {
   FPConvertToInt(rd, fn, FCVTAU);
 }
 
 
@@ skipping 54 matching lines @@
          Rd(fd));
   }
 }
 
 
 // Note:
 // Below, a difference in case for the same letter indicates a
 // negated bit.
 // If b is 1, then B is 0.
 Instr Assembler::ImmFP32(float imm) {
-  ASSERT(IsImmFP32(imm));
+  DCHECK(IsImmFP32(imm));
   // bits: aBbb.bbbc.defg.h000.0000.0000.0000.0000
   uint32_t bits = float_to_rawbits(imm);
   // bit7: a000.0000
   uint32_t bit7 = ((bits >> 31) & 0x1) << 7;
   // bit6: 0b00.0000
   uint32_t bit6 = ((bits >> 29) & 0x1) << 6;
   // bit5_to_0: 00cd.efgh
   uint32_t bit5_to_0 = (bits >> 19) & 0x3f;
 
   return (bit7 | bit6 | bit5_to_0) << ImmFP_offset;
 }
 
 
 Instr Assembler::ImmFP64(double imm) {
-  ASSERT(IsImmFP64(imm));
+  DCHECK(IsImmFP64(imm));
   // bits: aBbb.bbbb.bbcd.efgh.0000.0000.0000.0000
   //       0000.0000.0000.0000.0000.0000.0000.0000
   uint64_t bits = double_to_rawbits(imm);
   // bit7: a000.0000
   uint32_t bit7 = ((bits >> 63) & 0x1) << 7;
   // bit6: 0b00.0000
   uint32_t bit6 = ((bits >> 61) & 0x1) << 6;
   // bit5_to_0: 00cd.efgh
   uint32_t bit5_to_0 = (bits >> 48) & 0x3f;
 
   return (bit7 | bit6 | bit5_to_0) << ImmFP_offset;
 }
 
 
 // Code generation helpers.
 void Assembler::MoveWide(const Register& rd,
                          uint64_t imm,
                          int shift,
                          MoveWideImmediateOp mov_op) {
   // Ignore the top 32 bits of an immediate if we're moving to a W register.
   if (rd.Is32Bits()) {
     // Check that the top 32 bits are zero (a positive 32-bit number) or top
     // 33 bits are one (a negative 32-bit number, sign extended to 64 bits).
-    ASSERT(((imm >> kWRegSizeInBits) == 0) ||
+    DCHECK(((imm >> kWRegSizeInBits) == 0) ||
            ((imm >> (kWRegSizeInBits - 1)) == 0x1ffffffff));
     imm &= kWRegMask;
   }
 
   if (shift >= 0) {
     // Explicit shift specified.
-    ASSERT((shift == 0) || (shift == 16) || (shift == 32) || (shift == 48));
-    ASSERT(rd.Is64Bits() || (shift == 0) || (shift == 16));
+    DCHECK((shift == 0) || (shift == 16) || (shift == 32) || (shift == 48));
+    DCHECK(rd.Is64Bits() || (shift == 0) || (shift == 16));
     shift /= 16;
   } else {
     // Calculate a new immediate and shift combination to encode the immediate
     // argument.
     shift = 0;
     if ((imm & ~0xffffUL) == 0) {
       // Nothing to do.
     } else if ((imm & ~(0xffffUL << 16)) == 0) {
       imm >>= 16;
       shift = 1;
     } else if ((imm & ~(0xffffUL << 32)) == 0) {
-      ASSERT(rd.Is64Bits());
+      DCHECK(rd.Is64Bits());
       imm >>= 32;
       shift = 2;
     } else if ((imm & ~(0xffffUL << 48)) == 0) {
-      ASSERT(rd.Is64Bits());
+      DCHECK(rd.Is64Bits());
       imm >>= 48;
       shift = 3;
     }
   }
 
-  ASSERT(is_uint16(imm));
+  DCHECK(is_uint16(imm));
 
   Emit(SF(rd) | MoveWideImmediateFixed | mov_op |
        Rd(rd) | ImmMoveWide(imm) | ShiftMoveWide(shift));
 }
 
 
 void Assembler::AddSub(const Register& rd,
                        const Register& rn,
                        const Operand& operand,
                        FlagsUpdate S,
                        AddSubOp op) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(!operand.NeedsRelocation(this));
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(!operand.NeedsRelocation(this));
   if (operand.IsImmediate()) {
     int64_t immediate = operand.ImmediateValue();
-    ASSERT(IsImmAddSub(immediate));
+    DCHECK(IsImmAddSub(immediate));
     Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd);
     Emit(SF(rd) | AddSubImmediateFixed | op | Flags(S) |
          ImmAddSub(immediate) | dest_reg | RnSP(rn));
   } else if (operand.IsShiftedRegister()) {
-    ASSERT(operand.reg().SizeInBits() == rd.SizeInBits());
-    ASSERT(operand.shift() != ROR);
+    DCHECK(operand.reg().SizeInBits() == rd.SizeInBits());
+    DCHECK(operand.shift() != ROR);
 
     // For instructions of the form:
     //   add/sub   wsp, <Wn>, <Wm> [, LSL #0-3 ]
     //   add/sub   <Wd>, wsp, <Wm> [, LSL #0-3 ]
     //   add/sub   wsp, wsp, <Wm> [, LSL #0-3 ]
     //   adds/subs <Wd>, wsp, <Wm> [, LSL #0-3 ]
     // or their 64-bit register equivalents, convert the operand from shifted to
     // extended register mode, and emit an add/sub extended instruction.
     if (rn.IsSP() || rd.IsSP()) {
-      ASSERT(!(rd.IsSP() && (S == SetFlags)));
+      DCHECK(!(rd.IsSP() && (S == SetFlags)));
       DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
                                AddSubExtendedFixed | op);
     } else {
       DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
     }
   } else {
-    ASSERT(operand.IsExtendedRegister());
+    DCHECK(operand.IsExtendedRegister());
     DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
   }
 }
 
 
 void Assembler::AddSubWithCarry(const Register& rd,
                                 const Register& rn,
                                 const Operand& operand,
                                 FlagsUpdate S,
                                 AddSubWithCarryOp op) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(rd.SizeInBits() == operand.reg().SizeInBits());
-  ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
-  ASSERT(!operand.NeedsRelocation(this));
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == operand.reg().SizeInBits());
+  DCHECK(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
+  DCHECK(!operand.NeedsRelocation(this));
   Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::hlt(int code) {
-  ASSERT(is_uint16(code));
+  DCHECK(is_uint16(code));
   Emit(HLT | ImmException(code));
 }
 
 
 void Assembler::brk(int code) {
-  ASSERT(is_uint16(code));
+  DCHECK(is_uint16(code));
   Emit(BRK | ImmException(code));
 }
 
 
 void Assembler::debug(const char* message, uint32_t code, Instr params) {
 #ifdef USE_SIMULATOR
   // Don't generate simulator specific code if we are building a snapshot, which
   // might be run on real hardware.
   if (!serializer_enabled()) {
     // The arguments to the debug marker need to be contiguous in memory, so
     // make sure we don't try to emit pools.
     BlockPoolsScope scope(this);
 
     Label start;
     bind(&start);
 
     // Refer to instructions-arm64.h for a description of the marker and its
     // arguments.
     hlt(kImmExceptionIsDebug);
-    ASSERT(SizeOfCodeGeneratedSince(&start) == kDebugCodeOffset);
+    DCHECK(SizeOfCodeGeneratedSince(&start) == kDebugCodeOffset);
     dc32(code);
-    ASSERT(SizeOfCodeGeneratedSince(&start) == kDebugParamsOffset);
+    DCHECK(SizeOfCodeGeneratedSince(&start) == kDebugParamsOffset);
     dc32(params);
-    ASSERT(SizeOfCodeGeneratedSince(&start) == kDebugMessageOffset);
+    DCHECK(SizeOfCodeGeneratedSince(&start) == kDebugMessageOffset);
     EmitStringData(message);
     hlt(kImmExceptionIsUnreachable);
 
     return;
   }
   // Fall through if Serializer is enabled.
 #endif
 
   if (params & BREAK) {
     hlt(kImmExceptionIsDebug);
   }
 }
 
 
 void Assembler::Logical(const Register& rd,
                         const Register& rn,
                         const Operand& operand,
                         LogicalOp op) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
-  ASSERT(!operand.NeedsRelocation(this));
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(!operand.NeedsRelocation(this));
   if (operand.IsImmediate()) {
     int64_t immediate = operand.ImmediateValue();
     unsigned reg_size = rd.SizeInBits();
 
-    ASSERT(immediate != 0);
-    ASSERT(immediate != -1);
-    ASSERT(rd.Is64Bits() || is_uint32(immediate));
+    DCHECK(immediate != 0);
+    DCHECK(immediate != -1);
+    DCHECK(rd.Is64Bits() || is_uint32(immediate));
 
     // If the operation is NOT, invert the operation and immediate.
     if ((op & NOT) == NOT) {
       op = static_cast<LogicalOp>(op & ~NOT);
       immediate = rd.Is64Bits() ? ~immediate : (~immediate & kWRegMask);
     }
 
     unsigned n, imm_s, imm_r;
     if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) {
       // Immediate can be encoded in the instruction.
       LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
     } else {
       // This case is handled in the macro assembler.
       UNREACHABLE();
     }
   } else {
-    ASSERT(operand.IsShiftedRegister());
-    ASSERT(operand.reg().SizeInBits() == rd.SizeInBits());
+    DCHECK(operand.IsShiftedRegister());
+    DCHECK(operand.reg().SizeInBits() == rd.SizeInBits());
     Instr dp_op = static_cast<Instr>(op | LogicalShiftedFixed);
     DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
   }
 }
 
 
 void Assembler::LogicalImmediate(const Register& rd,
                                  const Register& rn,
                                  unsigned n,
                                  unsigned imm_s,
                                  unsigned imm_r,
                                  LogicalOp op) {
   unsigned reg_size = rd.SizeInBits();
   Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd);
   Emit(SF(rd) | LogicalImmediateFixed | op | BitN(n, reg_size) |
        ImmSetBits(imm_s, reg_size) | ImmRotate(imm_r, reg_size) | dest_reg |
        Rn(rn));
 }
 
 
 void Assembler::ConditionalCompare(const Register& rn,
                                    const Operand& operand,
                                    StatusFlags nzcv,
                                    Condition cond,
                                    ConditionalCompareOp op) {
   Instr ccmpop;
-  ASSERT(!operand.NeedsRelocation(this));
+  DCHECK(!operand.NeedsRelocation(this));
   if (operand.IsImmediate()) {
     int64_t immediate = operand.ImmediateValue();
-    ASSERT(IsImmConditionalCompare(immediate));
+    DCHECK(IsImmConditionalCompare(immediate));
     ccmpop = ConditionalCompareImmediateFixed | op | ImmCondCmp(immediate);
   } else {
-    ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
+    DCHECK(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
     ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.reg());
   }
   Emit(SF(rn) | ccmpop | Cond(cond) | Rn(rn) | Nzcv(nzcv));
 }
 
 
 void Assembler::DataProcessing1Source(const Register& rd,
                                       const Register& rn,
                                       DataProcessing1SourceOp op) {
-  ASSERT(rd.SizeInBits() == rn.SizeInBits());
+  DCHECK(rd.SizeInBits() == rn.SizeInBits());
   Emit(SF(rn) | op | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::FPDataProcessing1Source(const FPRegister& fd,
                                         const FPRegister& fn,
                                         FPDataProcessing1SourceOp op) {
   Emit(FPType(fn) | op | Rn(fn) | Rd(fd));
 }
 
 
 void Assembler::FPDataProcessing2Source(const FPRegister& fd,
                                         const FPRegister& fn,
                                         const FPRegister& fm,
                                         FPDataProcessing2SourceOp op) {
-  ASSERT(fd.SizeInBits() == fn.SizeInBits());
-  ASSERT(fd.SizeInBits() == fm.SizeInBits());
+  DCHECK(fd.SizeInBits() == fn.SizeInBits());
+  DCHECK(fd.SizeInBits() == fm.SizeInBits());
   Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd));
 }
 
 
 void Assembler::FPDataProcessing3Source(const FPRegister& fd,
                                         const FPRegister& fn,
                                         const FPRegister& fm,
                                         const FPRegister& fa,
                                         FPDataProcessing3SourceOp op) {
-  ASSERT(AreSameSizeAndType(fd, fn, fm, fa));
+  DCHECK(AreSameSizeAndType(fd, fn, fm, fa));
   Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd) | Ra(fa));
 }
 
 
 void Assembler::EmitShift(const Register& rd,
                           const Register& rn,
                           Shift shift,
                           unsigned shift_amount) {
   switch (shift) {
     case LSL:
@@ skipping 11 matching lines @@
     default:
       UNREACHABLE();
   }
 }
 
 
 void Assembler::EmitExtendShift(const Register& rd,
                                 const Register& rn,
                                 Extend extend,
                                 unsigned left_shift) {
-  ASSERT(rd.SizeInBits() >= rn.SizeInBits());
+  DCHECK(rd.SizeInBits() >= rn.SizeInBits());
   unsigned reg_size = rd.SizeInBits();
   // Use the correct size of register.
   Register rn_ = Register::Create(rn.code(), rd.SizeInBits());
   // Bits extracted are high_bit:0.
   unsigned high_bit = (8 << (extend & 0x3)) - 1;
   // Number of bits left in the result that are not introduced by the shift.
   unsigned non_shift_bits = (reg_size - left_shift) & (reg_size - 1);
 
   if ((non_shift_bits > high_bit) || (non_shift_bits == 0)) {
     switch (extend) {
       case UXTB:
       case UXTH:
       case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break;
       case SXTB:
       case SXTH:
       case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break;
       case UXTX:
       case SXTX: {
-        ASSERT(rn.SizeInBits() == kXRegSizeInBits);
+        DCHECK(rn.SizeInBits() == kXRegSizeInBits);
         // Nothing to extend. Just shift.
         lsl(rd, rn_, left_shift);
         break;
       }
       default: UNREACHABLE();
     }
   } else {
     // No need to extend as the extended bits would be shifted away.
     lsl(rd, rn_, left_shift);
   }
 }
 
 
 void Assembler::DataProcShiftedRegister(const Register& rd,
                                         const Register& rn,
                                         const Operand& operand,
                                         FlagsUpdate S,
                                         Instr op) {
-  ASSERT(operand.IsShiftedRegister());
-  ASSERT(rn.Is64Bits() || (rn.Is32Bits() && is_uint5(operand.shift_amount())));
-  ASSERT(!operand.NeedsRelocation(this));
+  DCHECK(operand.IsShiftedRegister());
+  DCHECK(rn.Is64Bits() || (rn.Is32Bits() && is_uint5(operand.shift_amount())));
+  DCHECK(!operand.NeedsRelocation(this));
   Emit(SF(rd) | op | Flags(S) |
        ShiftDP(operand.shift()) | ImmDPShift(operand.shift_amount()) |
        Rm(operand.reg()) | Rn(rn) | Rd(rd));
 }
 
 
 void Assembler::DataProcExtendedRegister(const Register& rd,
                                          const Register& rn,
                                          const Operand& operand,
                                          FlagsUpdate S,
                                          Instr op) {
-  ASSERT(!operand.NeedsRelocation(this));
+  DCHECK(!operand.NeedsRelocation(this));
   Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd);
   Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
        ExtendMode(operand.extend()) | ImmExtendShift(operand.shift_amount()) |
        dest_reg | RnSP(rn));
 }
 
 
 bool Assembler::IsImmAddSub(int64_t immediate) {
   return is_uint12(immediate) ||
          (is_uint12(immediate >> 12) && ((immediate & 0xfff) == 0));
@@ skipping 23 matching lines @@
     Shift shift = addr.shift();
     unsigned shift_amount = addr.shift_amount();
 
     // LSL is encoded in the option field as UXTX.
     if (shift == LSL) {
       ext = UXTX;
     }
 
     // Shifts are encoded in one bit, indicating a left shift by the memory
     // access size.
-    ASSERT((shift_amount == 0) ||
+    DCHECK((shift_amount == 0) ||
            (shift_amount == static_cast<unsigned>(CalcLSDataSize(op))));
     Emit(LoadStoreRegisterOffsetFixed | memop | Rm(addr.regoffset()) |
          ExtendMode(ext) | ImmShiftLS((shift_amount > 0) ? 1 : 0));
   } else {
     // Pre-index and post-index modes.
-    ASSERT(!rt.Is(addr.base()));
+    DCHECK(!rt.Is(addr.base()));
     if (IsImmLSUnscaled(offset)) {
       if (addr.IsPreIndex()) {
         Emit(LoadStorePreIndexFixed | memop | ImmLS(offset));
       } else {
-        ASSERT(addr.IsPostIndex());
+        DCHECK(addr.IsPostIndex());
         Emit(LoadStorePostIndexFixed | memop | ImmLS(offset));
       }
     } else {
       // This case is handled in the macro assembler.
       UNREACHABLE();
     }
   }
 }
 
 
@@ skipping 13 matching lines @@
 // If it can be encoded, the function returns true, and values pointed to by n,
 // imm_s and imm_r are updated with immediates encoded in the format required
 // by the corresponding fields in the logical instruction.
 // If it can not be encoded, the function returns false, and the values pointed
 // to by n, imm_s and imm_r are undefined.
 bool Assembler::IsImmLogical(uint64_t value,
                              unsigned width,
                              unsigned* n,
                              unsigned* imm_s,
                              unsigned* imm_r) {
-  ASSERT((n != NULL) && (imm_s != NULL) && (imm_r != NULL));
-  ASSERT((width == kWRegSizeInBits) || (width == kXRegSizeInBits));
+  DCHECK((n != NULL) && (imm_s != NULL) && (imm_r != NULL));
+  DCHECK((width == kWRegSizeInBits) || (width == kXRegSizeInBits));
 
   bool negate = false;
 
   // Logical immediates are encoded using parameters n, imm_s and imm_r using
   // the following table:
   //
   //    N   imms    immr    size        S             R
   //    1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
   //    0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
   //    0  10ssss  xxrrrr    16    UInt(ssss)    UInt(rrrr)
@@ skipping 120 matching lines @@
   static const uint64_t multipliers[] = {
     0x0000000000000001UL,
     0x0000000100000001UL,
     0x0001000100010001UL,
     0x0101010101010101UL,
     0x1111111111111111UL,
     0x5555555555555555UL,
   };
   int multiplier_idx = CountLeadingZeros(d, kXRegSizeInBits) - 57;
   // Ensure that the index to the multipliers array is within bounds.
-  ASSERT((multiplier_idx >= 0) &&
+  DCHECK((multiplier_idx >= 0) &&
          (static_cast<size_t>(multiplier_idx) <
           (sizeof(multipliers) / sizeof(multipliers[0]))));
   uint64_t multiplier = multipliers[multiplier_idx];
   uint64_t candidate = (b - a) * multiplier;
 
   if (value != candidate) {
     // The candidate pattern doesn't match our input value, so fail.
     return false;
   }
 
@@ skipping 143 matching lines @@
 
 
 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
   // We do not try to reuse pool constants.
   RelocInfo rinfo(reinterpret_cast<byte*>(pc_), rmode, data, NULL);
   if (((rmode >= RelocInfo::JS_RETURN) &&
        (rmode <= RelocInfo::DEBUG_BREAK_SLOT)) ||
       (rmode == RelocInfo::CONST_POOL) ||
       (rmode == RelocInfo::VENEER_POOL)) {
     // Adjust code for new modes.
-    ASSERT(RelocInfo::IsDebugBreakSlot(rmode)
+    DCHECK(RelocInfo::IsDebugBreakSlot(rmode)
            || RelocInfo::IsJSReturn(rmode)
            || RelocInfo::IsComment(rmode)
            || RelocInfo::IsPosition(rmode)
            || RelocInfo::IsConstPool(rmode)
            || RelocInfo::IsVeneerPool(rmode));
     // These modes do not need an entry in the constant pool.
   } else {
     constpool_.RecordEntry(data, rmode);
     // Make sure the constant pool is not emitted in place of the next
     // instruction for which we just recorded relocation info.
     BlockConstPoolFor(1);
   }
 
   if (!RelocInfo::IsNone(rmode)) {
     // Don't record external references unless the heap will be serialized.
     if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
         !serializer_enabled() && !emit_debug_code()) {
       return;
     }
-    ASSERT(buffer_space() >= kMaxRelocSize);  // too late to grow buffer here
+    DCHECK(buffer_space() >= kMaxRelocSize);  // too late to grow buffer here
     if (rmode == RelocInfo::CODE_TARGET_WITH_ID) {
       RelocInfo reloc_info_with_ast_id(
           reinterpret_cast<byte*>(pc_), rmode, RecordedAstId().ToInt(), NULL);
       ClearRecordedAstId();
       reloc_info_writer.Write(&reloc_info_with_ast_id);
     } else {
       reloc_info_writer.Write(&rinfo);
     }
   }
 }
 
 
 void Assembler::BlockConstPoolFor(int instructions) {
   int pc_limit = pc_offset() + instructions * kInstructionSize;
   if (no_const_pool_before_ < pc_limit) {
     no_const_pool_before_ = pc_limit;
     // Make sure the pool won't be blocked for too long.
-    ASSERT(pc_limit < constpool_.MaxPcOffset());
+    DCHECK(pc_limit < constpool_.MaxPcOffset());
   }
 
   if (next_constant_pool_check_ < no_const_pool_before_) {
     next_constant_pool_check_ = no_const_pool_before_;
   }
 }
 
 
 void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
   // Some short sequence of instruction mustn't be broken up by constant pool
   // emission, such sequences are protected by calls to BlockConstPoolFor and
   // BlockConstPoolScope.
   if (is_const_pool_blocked()) {
     // Something is wrong if emission is forced and blocked at the same time.
-    ASSERT(!force_emit);
+    DCHECK(!force_emit);
     return;
   }
 
   // There is nothing to do if there are no pending constant pool entries.
   if (constpool_.IsEmpty())  {
     // Calculate the offset of the next check.
     SetNextConstPoolCheckIn(kCheckConstPoolInterval);
     return;
   }
 
@@ skipping 20 matching lines @@
   // Check that the code buffer is large enough before emitting the constant
   // pool (this includes the gap to the relocation information).
   int needed_space = worst_case_size + kGap + 1 * kInstructionSize;
   while (buffer_space() <= needed_space) {
     GrowBuffer();
   }
 
   Label size_check;
   bind(&size_check);
   constpool_.Emit(require_jump);
-  ASSERT(SizeOfCodeGeneratedSince(&size_check) <=
+  DCHECK(SizeOfCodeGeneratedSince(&size_check) <=
          static_cast<unsigned>(worst_case_size));
 
   // Since a constant pool was just emitted, move the check offset forward by
   // the standard interval.
   SetNextConstPoolCheckIn(kCheckConstPoolInterval);
 }
 
 
 bool Assembler::ShouldEmitVeneer(int max_reachable_pc, int margin) {
   // Account for the branch around the veneers and the guard.
@@ skipping 44 matching lines @@
 #ifdef DEBUG
       bind(&veneer_size_check);
 #endif
       // Patch the branch to point to the current position, and emit a branch
       // to the label.
       Instruction* veneer = reinterpret_cast<Instruction*>(pc_);
       RemoveBranchFromLabelLinkChain(branch, label, veneer);
       branch->SetImmPCOffsetTarget(veneer);
       b(label);
 #ifdef DEBUG
-      ASSERT(SizeOfCodeGeneratedSince(&veneer_size_check) <=
+      DCHECK(SizeOfCodeGeneratedSince(&veneer_size_check) <=
              static_cast<uint64_t>(kMaxVeneerCodeSize));
       veneer_size_check.Unuse();
 #endif
 
       it_to_delete = it++;
       unresolved_branches_.erase(it_to_delete);
     } else {
       ++it;
     }
   }
@@ skipping 12 matching lines @@
   bind(&end);
 
   RecordComment("]");
 }
 
 
 void Assembler::CheckVeneerPool(bool force_emit, bool require_jump,
                                 int margin) {
   // There is nothing to do if there are no pending veneer pool entries.
   if (unresolved_branches_.empty())  {
-    ASSERT(next_veneer_pool_check_ == kMaxInt);
+    DCHECK(next_veneer_pool_check_ == kMaxInt);
     return;
   }
 
-  ASSERT(pc_offset() < unresolved_branches_first_limit());
+  DCHECK(pc_offset() < unresolved_branches_first_limit());
 
   // Some short sequence of instruction mustn't be broken up by veneer pool
   // emission, such sequences are protected by calls to BlockVeneerPoolFor and
   // BlockVeneerPoolScope.
   if (is_veneer_pool_blocked()) {
-    ASSERT(!force_emit);
+    DCHECK(!force_emit);
     return;
   }
 
   if (!require_jump) {
     // Prefer emitting veneers protected by an existing instruction.
     margin *= kVeneerNoProtectionFactor;
   }
   if (force_emit || ShouldEmitVeneers(margin)) {
     EmitVeneers(force_emit, require_jump, margin);
   } else {
@@ skipping 32 matching lines @@
 
 void Assembler::RecordConstPool(int size) {
   // We only need this for debugger support, to correctly compute offsets in the
   // code.
   RecordRelocInfo(RelocInfo::CONST_POOL, static_cast<intptr_t>(size));
 }
 
 
 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
   // No out-of-line constant pool support.
-  ASSERT(!FLAG_enable_ool_constant_pool);
+  DCHECK(!FLAG_enable_ool_constant_pool);
   return isolate->factory()->empty_constant_pool_array();
 }
 
 
 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
   // No out-of-line constant pool support.
-  ASSERT(!FLAG_enable_ool_constant_pool);
+  DCHECK(!FLAG_enable_ool_constant_pool);
   return;
 }
 
 
 void PatchingAssembler::PatchAdrFar(ptrdiff_t target_offset) {
   // The code at the current instruction should be:
   //   adr  rd, 0
   //   nop  (adr_far)
   //   nop  (adr_far)
   //   movz scratch, 0
@@ skipping 12 matching lines @@
         (expected_movz->ShiftMoveWide() == 0));
   int scratch_code = expected_movz->Rd();
 
   // Patch to load the correct address.
   Register rd = Register::XRegFromCode(rd_code);
   Register scratch = Register::XRegFromCode(scratch_code);
   // Addresses are only 48 bits.
   adr(rd, target_offset & 0xFFFF);
   movz(scratch, (target_offset >> 16) & 0xFFFF, 16);
   movk(scratch, (target_offset >> 32) & 0xFFFF, 32);
-  ASSERT((target_offset >> 48) == 0);
+  DCHECK((target_offset >> 48) == 0);
   add(rd, rd, scratch);
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64