Rename ASSERT* to DCHECK*.

src/arm/macro-assembler-arm.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM_MACRO_ASSEMBLER_ARM_H_
 #define V8_ARM_MACRO_ASSEMBLER_ARM_H_
 
 #include "src/assembler.h"
 #include "src/frames.h"
 #include "src/globals.h"
@@ skipping 296 matching lines @@
       SmiCheck smi_check = INLINE_SMI_CHECK,
       PointersToHereCheck pointers_to_here_check_for_value =
           kPointersToHereMaybeInteresting);
 
   // Push a handle.
   void Push(Handle<Object> handle);
   void Push(Smi* smi) { Push(Handle<Smi>(smi, isolate())); }
 
   // Push two registers.  Pushes leftmost register first (to highest address).
   void Push(Register src1, Register src2, Condition cond = al) {
-    ASSERT(!src1.is(src2));
+    DCHECK(!src1.is(src2));
     if (src1.code() > src2.code()) {
       stm(db_w, sp, src1.bit() | src2.bit(), cond);
     } else {
       str(src1, MemOperand(sp, 4, NegPreIndex), cond);
       str(src2, MemOperand(sp, 4, NegPreIndex), cond);
     }
   }
 
   // Push three registers.  Pushes leftmost register first (to highest address).
   void Push(Register src1, Register src2, Register src3, Condition cond = al) {
-    ASSERT(!src1.is(src2));
-    ASSERT(!src2.is(src3));
-    ASSERT(!src1.is(src3));
+    DCHECK(!src1.is(src2));
+    DCHECK(!src2.is(src3));
+    DCHECK(!src1.is(src3));
     if (src1.code() > src2.code()) {
       if (src2.code() > src3.code()) {
         stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
       } else {
         stm(db_w, sp, src1.bit() | src2.bit(), cond);
         str(src3, MemOperand(sp, 4, NegPreIndex), cond);
       }
     } else {
       str(src1, MemOperand(sp, 4, NegPreIndex), cond);
       Push(src2, src3, cond);
     }
   }
 
   // Push four registers.  Pushes leftmost register first (to highest address).
   void Push(Register src1,
             Register src2,
             Register src3,
             Register src4,
             Condition cond = al) {
-    ASSERT(!src1.is(src2));
-    ASSERT(!src2.is(src3));
-    ASSERT(!src1.is(src3));
-    ASSERT(!src1.is(src4));
-    ASSERT(!src2.is(src4));
-    ASSERT(!src3.is(src4));
+    DCHECK(!src1.is(src2));
+    DCHECK(!src2.is(src3));
+    DCHECK(!src1.is(src3));
+    DCHECK(!src1.is(src4));
+    DCHECK(!src2.is(src4));
+    DCHECK(!src3.is(src4));
     if (src1.code() > src2.code()) {
       if (src2.code() > src3.code()) {
         if (src3.code() > src4.code()) {
           stm(db_w,
               sp,
               src1.bit() | src2.bit() | src3.bit() | src4.bit(),
               cond);
         } else {
           stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
           str(src4, MemOperand(sp, 4, NegPreIndex), cond);
         }
       } else {
         stm(db_w, sp, src1.bit() | src2.bit(), cond);
         Push(src3, src4, cond);
       }
     } else {
       str(src1, MemOperand(sp, 4, NegPreIndex), cond);
       Push(src2, src3, src4, cond);
     }
   }
 
   // Pop two registers. Pops rightmost register first (from lower address).
   void Pop(Register src1, Register src2, Condition cond = al) {
-    ASSERT(!src1.is(src2));
+    DCHECK(!src1.is(src2));
     if (src1.code() > src2.code()) {
       ldm(ia_w, sp, src1.bit() | src2.bit(), cond);
     } else {
       ldr(src2, MemOperand(sp, 4, PostIndex), cond);
       ldr(src1, MemOperand(sp, 4, PostIndex), cond);
     }
   }
 
   // Pop three registers.  Pops rightmost register first (from lower address).
   void Pop(Register src1, Register src2, Register src3, Condition cond = al) {
-    ASSERT(!src1.is(src2));
-    ASSERT(!src2.is(src3));
-    ASSERT(!src1.is(src3));
+    DCHECK(!src1.is(src2));
+    DCHECK(!src2.is(src3));
+    DCHECK(!src1.is(src3));
     if (src1.code() > src2.code()) {
       if (src2.code() > src3.code()) {
         ldm(ia_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
       } else {
         ldr(src3, MemOperand(sp, 4, PostIndex), cond);
         ldm(ia_w, sp, src1.bit() | src2.bit(), cond);
       }
     } else {
       Pop(src2, src3, cond);
       ldr(src1, MemOperand(sp, 4, PostIndex), cond);
     }
   }
 
   // Pop four registers.  Pops rightmost register first (from lower address).
   void Pop(Register src1,
            Register src2,
            Register src3,
            Register src4,
            Condition cond = al) {
-    ASSERT(!src1.is(src2));
-    ASSERT(!src2.is(src3));
-    ASSERT(!src1.is(src3));
-    ASSERT(!src1.is(src4));
-    ASSERT(!src2.is(src4));
-    ASSERT(!src3.is(src4));
+    DCHECK(!src1.is(src2));
+    DCHECK(!src2.is(src3));
+    DCHECK(!src1.is(src3));
+    DCHECK(!src1.is(src4));
+    DCHECK(!src2.is(src4));
+    DCHECK(!src3.is(src4));
     if (src1.code() > src2.code()) {
       if (src2.code() > src3.code()) {
         if (src3.code() > src4.code()) {
           ldm(ia_w,
               sp,
               src1.bit() | src2.bit() | src3.bit() | src4.bit(),
               cond);
         } else {
           ldr(src4, MemOperand(sp, 4, PostIndex), cond);
           ldm(ia_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
@@ skipping 252 matching lines @@
 
   inline void MarkCode(NopMarkerTypes type) {
     nop(type);
   }
 
   // Check if the given instruction is a 'type' marker.
   // i.e. check if is is a mov r<type>, r<type> (referenced as nop(type))
   // These instructions are generated to mark special location in the code,
   // like some special IC code.
   static inline bool IsMarkedCode(Instr instr, int type) {
-    ASSERT((FIRST_IC_MARKER <= type) && (type < LAST_CODE_MARKER));
+    DCHECK((FIRST_IC_MARKER <= type) && (type < LAST_CODE_MARKER));
     return IsNop(instr, type);
   }
 
 
   static inline int GetCodeMarker(Instr instr) {
     int dst_reg_offset = 12;
     int dst_mask = 0xf << dst_reg_offset;
     int src_mask = 0xf;
     int dst_reg = (instr & dst_mask) >> dst_reg_offset;
     int src_reg = instr & src_mask;
     uint32_t non_register_mask = ~(dst_mask | src_mask);
     uint32_t mov_mask = al | 13 << 21;
 
     // Return <n> if we have a mov rn rn, else return -1.
     int type = ((instr & non_register_mask) == mov_mask) &&
                (dst_reg == src_reg) &&
                (FIRST_IC_MARKER <= dst_reg) && (dst_reg < LAST_CODE_MARKER)
                    ? src_reg
                    : -1;
-    ASSERT((type == -1) ||
+    DCHECK((type == -1) ||
            ((FIRST_IC_MARKER <= type) && (type < LAST_CODE_MARKER)));
     return type;
   }
 
 
   // ---------------------------------------------------------------------------
   // Allocation support
 
   // Allocate an object in new space or old pointer space. The object_size is
   // specified either in bytes or in words if the allocation flag SIZE_IN_WORDS
@@ skipping 219 matching lines @@
   // Loads the type into the second argument register.
   // Returns a condition that will be enabled if the object was a string
   // and the passed-in condition passed. If the passed-in condition failed
   // then flags remain unchanged.
   Condition IsObjectStringType(Register obj,
                                Register type,
                                Condition cond = al) {
     ldr(type, FieldMemOperand(obj, HeapObject::kMapOffset), cond);
     ldrb(type, FieldMemOperand(type, Map::kInstanceTypeOffset), cond);
     tst(type, Operand(kIsNotStringMask), cond);
-    ASSERT_EQ(0, kStringTag);
+    DCHECK_EQ(0, kStringTag);
     return eq;
   }
 
 
   // Picks out an array index from the hash field.
   // Register use:
   //   hash - holds the index's hash. Clobbered.
   //   index - holds the overwritten index on exit.
   void IndexFromHash(Register hash, Register index);
 
@@ skipping 176 matching lines @@
                      const CallWrapper& call_wrapper = NullCallWrapper());
 
   // Store the code object for the given builtin in the target register and
   // setup the function in r1.
   void GetBuiltinEntry(Register target, Builtins::JavaScript id);
 
   // Store the function for the given builtin in the target register.
   void GetBuiltinFunction(Register target, Builtins::JavaScript id);
 
   Handle<Object> CodeObject() {
-    ASSERT(!code_object_.is_null());
+    DCHECK(!code_object_.is_null());
     return code_object_;
   }
 
 
   // Emit code for a truncating division by a constant. The dividend register is
   // unchanged and ip gets clobbered. Dividend and result must be different.
   void TruncatingDiv(Register result, Register dividend, int32_t divisor);
 
   // ---------------------------------------------------------------------------
   // StatsCounter support
@@ skipping 382 matching lines @@
 
 class FrameAndConstantPoolScope {
  public:
   FrameAndConstantPoolScope(MacroAssembler* masm, StackFrame::Type type)
       : masm_(masm),
         type_(type),
         old_has_frame_(masm->has_frame()),
         old_constant_pool_available_(masm->is_constant_pool_available())  {
     // We only want to enable constant pool access for non-manual frame scopes
     // to ensure the constant pool pointer is valid throughout the scope.
-    ASSERT(type_ != StackFrame::MANUAL && type_ != StackFrame::NONE);
+    DCHECK(type_ != StackFrame::MANUAL && type_ != StackFrame::NONE);
     masm->set_has_frame(true);
     masm->set_constant_pool_available(true);
     masm->EnterFrame(type, !old_constant_pool_available_);
   }
 
   ~FrameAndConstantPoolScope() {
     masm_->LeaveFrame(type_);
     masm_->set_has_frame(old_has_frame_);
     masm_->set_constant_pool_available(old_constant_pool_available_);
   }
 
   // Normally we generate the leave-frame code when this object goes
   // out of scope.  Sometimes we may need to generate the code somewhere else
   // in addition.  Calling this will achieve that, but the object stays in
   // scope, the MacroAssembler is still marked as being in a frame scope, and
   // the code will be generated again when it goes out of scope.
   void GenerateLeaveFrame() {
-    ASSERT(type_ != StackFrame::MANUAL && type_ != StackFrame::NONE);
+    DCHECK(type_ != StackFrame::MANUAL && type_ != StackFrame::NONE);
     masm_->LeaveFrame(type_);
   }
 
  private:
   MacroAssembler* masm_;
   StackFrame::Type type_;
   bool old_has_frame_;
   bool old_constant_pool_available_;
 
   DISALLOW_IMPLICIT_CONSTRUCTORS(FrameAndConstantPoolScope);
@@ skipping 43 matching lines @@
 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
 #else
 #define ACCESS_MASM(masm) masm->
 #endif
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM_MACRO_ASSEMBLER_ARM_H_