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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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285 bool is_int16() const { | 285 bool is_int16() const { |
286 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_); | 286 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_); |
287 } | 287 } |
288 | 288 |
289 private: | 289 private: |
290 inline explicit Immediate(Label* value); | 290 inline explicit Immediate(Label* value); |
291 | 291 |
292 int x_; | 292 int x_; |
293 RelocInfo::Mode rmode_; | 293 RelocInfo::Mode rmode_; |
294 | 294 |
| 295 friend class Operand; |
295 friend class Assembler; | 296 friend class Assembler; |
296 friend class MacroAssembler; | 297 friend class MacroAssembler; |
297 }; | 298 }; |
298 | 299 |
299 | 300 |
300 // ----------------------------------------------------------------------------- | 301 // ----------------------------------------------------------------------------- |
301 // Machine instruction Operands | 302 // Machine instruction Operands |
302 | 303 |
303 enum ScaleFactor { | 304 enum ScaleFactor { |
304 times_1 = 0, | 305 times_1 = 0, |
305 times_2 = 1, | 306 times_2 = 1, |
306 times_4 = 2, | 307 times_4 = 2, |
307 times_8 = 3, | 308 times_8 = 3, |
308 times_int_size = times_4, | 309 times_int_size = times_4, |
309 times_half_pointer_size = times_2, | 310 times_half_pointer_size = times_2, |
310 times_pointer_size = times_4, | 311 times_pointer_size = times_4, |
311 times_twice_pointer_size = times_8 | 312 times_twice_pointer_size = times_8 |
312 }; | 313 }; |
313 | 314 |
314 | 315 |
315 class Operand BASE_EMBEDDED { | 316 class Operand BASE_EMBEDDED { |
316 public: | 317 public: |
| 318 // reg |
| 319 INLINE(explicit Operand(Register reg)); |
| 320 |
317 // [disp/r] | 321 // [disp/r] |
318 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode)); | 322 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode)); |
319 // disp only must always be relocated | 323 |
| 324 // [disp/r] |
| 325 INLINE(explicit Operand(Immediate imm)); |
320 | 326 |
321 // [base + disp/r] | 327 // [base + disp/r] |
322 explicit Operand(Register base, int32_t disp, | 328 explicit Operand(Register base, int32_t disp, |
323 RelocInfo::Mode rmode = RelocInfo::NONE32); | 329 RelocInfo::Mode rmode = RelocInfo::NONE32); |
324 | 330 |
325 // [base + index*scale + disp/r] | 331 // [base + index*scale + disp/r] |
326 explicit Operand(Register base, | 332 explicit Operand(Register base, |
327 Register index, | 333 Register index, |
328 ScaleFactor scale, | 334 ScaleFactor scale, |
329 int32_t disp, | 335 int32_t disp, |
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346 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()), | 352 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()), |
347 RelocInfo::EXTERNAL_REFERENCE); | 353 RelocInfo::EXTERNAL_REFERENCE); |
348 } | 354 } |
349 | 355 |
350 static Operand ForCell(Handle<Cell> cell) { | 356 static Operand ForCell(Handle<Cell> cell) { |
351 AllowDeferredHandleDereference embedding_raw_address; | 357 AllowDeferredHandleDereference embedding_raw_address; |
352 return Operand(reinterpret_cast<int32_t>(cell.location()), | 358 return Operand(reinterpret_cast<int32_t>(cell.location()), |
353 RelocInfo::CELL); | 359 RelocInfo::CELL); |
354 } | 360 } |
355 | 361 |
| 362 static Operand ForRegisterPlusImmediate(Register base, Immediate imm) { |
| 363 return Operand(base, imm.x_, imm.rmode_); |
| 364 } |
| 365 |
356 // Returns true if this Operand is a wrapper for the specified register. | 366 // Returns true if this Operand is a wrapper for the specified register. |
357 bool is_reg(Register reg) const; | 367 bool is_reg(Register reg) const; |
358 | 368 |
359 // Returns true if this Operand is a wrapper for one register. | 369 // Returns true if this Operand is a wrapper for one register. |
360 bool is_reg_only() const; | 370 bool is_reg_only() const; |
361 | 371 |
362 // Asserts that this Operand is a wrapper for one register and returns the | 372 // Asserts that this Operand is a wrapper for one register and returns the |
363 // register. | 373 // register. |
364 Register reg() const; | 374 Register reg() const; |
365 | 375 |
366 private: | 376 private: |
367 // reg | |
368 INLINE(explicit Operand(Register reg)); | |
369 | |
370 // Set the ModRM byte without an encoded 'reg' register. The | 377 // Set the ModRM byte without an encoded 'reg' register. The |
371 // register is encoded later as part of the emit_operand operation. | 378 // register is encoded later as part of the emit_operand operation. |
372 inline void set_modrm(int mod, Register rm); | 379 inline void set_modrm(int mod, Register rm); |
373 | 380 |
374 inline void set_sib(ScaleFactor scale, Register index, Register base); | 381 inline void set_sib(ScaleFactor scale, Register index, Register base); |
375 inline void set_disp8(int8_t disp); | 382 inline void set_disp8(int8_t disp); |
376 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode); | 383 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode); |
377 | 384 |
378 byte buf_[6]; | 385 byte buf_[6]; |
379 // The number of bytes in buf_. | 386 // The number of bytes in buf_. |
380 unsigned int len_; | 387 unsigned int len_; |
381 // Only valid if len_ > 4. | 388 // Only valid if len_ > 4. |
382 RelocInfo::Mode rmode_; | 389 RelocInfo::Mode rmode_; |
383 | 390 |
384 friend class Assembler; | 391 friend class Assembler; |
385 friend class MacroAssembler; | 392 friend class MacroAssembler; |
386 friend class LCodeGen; | |
387 }; | 393 }; |
388 | 394 |
389 | 395 |
390 // ----------------------------------------------------------------------------- | 396 // ----------------------------------------------------------------------------- |
391 // A Displacement describes the 32bit immediate field of an instruction which | 397 // A Displacement describes the 32bit immediate field of an instruction which |
392 // may be used together with a Label in order to refer to a yet unknown code | 398 // may be used together with a Label in order to refer to a yet unknown code |
393 // position. Displacements stored in the instruction stream are used to describe | 399 // position. Displacements stored in the instruction stream are used to describe |
394 // the instruction and to chain a list of instructions using the same Label. | 400 // the instruction and to chain a list of instructions using the same Label. |
395 // A Displacement contains 2 different fields: | 401 // A Displacement contains 2 different fields: |
396 // | 402 // |
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623 void movzx_w(Register dst, const Operand& src); | 629 void movzx_w(Register dst, const Operand& src); |
624 | 630 |
625 // Flag management. | 631 // Flag management. |
626 void cld(); | 632 void cld(); |
627 | 633 |
628 // Repetitive string instructions. | 634 // Repetitive string instructions. |
629 void rep_movs(); | 635 void rep_movs(); |
630 void rep_stos(); | 636 void rep_stos(); |
631 void stos(); | 637 void stos(); |
632 | 638 |
633 // Exchange two registers | 639 // Exchange |
634 void xchg(Register dst, Register src); | 640 void xchg(Register dst, Register src); |
| 641 void xchg(Register dst, const Operand& src); |
635 | 642 |
636 // Arithmetics | 643 // Arithmetics |
637 void adc(Register dst, int32_t imm32); | 644 void adc(Register dst, int32_t imm32); |
638 void adc(Register dst, const Operand& src); | 645 void adc(Register dst, const Operand& src); |
639 | 646 |
640 void add(Register dst, Register src) { add(dst, Operand(src)); } | 647 void add(Register dst, Register src) { add(dst, Operand(src)); } |
641 void add(Register dst, const Operand& src); | 648 void add(Register dst, const Operand& src); |
642 void add(const Operand& dst, Register src); | 649 void add(const Operand& dst, Register src); |
643 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); } | 650 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); } |
644 void add(const Operand& dst, const Immediate& x); | 651 void add(const Operand& dst, const Immediate& x); |
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666 void cmp(const Operand& op, Handle<Object> handle); | 673 void cmp(const Operand& op, Handle<Object> handle); |
667 | 674 |
668 void dec_b(Register dst); | 675 void dec_b(Register dst); |
669 void dec_b(const Operand& dst); | 676 void dec_b(const Operand& dst); |
670 | 677 |
671 void dec(Register dst); | 678 void dec(Register dst); |
672 void dec(const Operand& dst); | 679 void dec(const Operand& dst); |
673 | 680 |
674 void cdq(); | 681 void cdq(); |
675 | 682 |
676 void idiv(Register src); | 683 void idiv(Register src) { idiv(Operand(src)); } |
| 684 void idiv(const Operand& src); |
| 685 void div(Register src) { div(Operand(src)); } |
| 686 void div(const Operand& src); |
677 | 687 |
678 // Signed multiply instructions. | 688 // Signed multiply instructions. |
679 void imul(Register src); // edx:eax = eax * src. | 689 void imul(Register src); // edx:eax = eax * src. |
680 void imul(Register dst, Register src) { imul(dst, Operand(src)); } | 690 void imul(Register dst, Register src) { imul(dst, Operand(src)); } |
681 void imul(Register dst, const Operand& src); // dst = dst * src. | 691 void imul(Register dst, const Operand& src); // dst = dst * src. |
682 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32. | 692 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32. |
| 693 void imul(Register dst, const Operand& src, int32_t imm32); |
683 | 694 |
684 void inc(Register dst); | 695 void inc(Register dst); |
685 void inc(const Operand& dst); | 696 void inc(const Operand& dst); |
686 | 697 |
687 void lea(Register dst, const Operand& src); | 698 void lea(Register dst, const Operand& src); |
688 | 699 |
689 // Unsigned multiply instruction. | 700 // Unsigned multiply instruction. |
690 void mul(Register src); // edx:eax = eax * reg. | 701 void mul(Register src); // edx:eax = eax * reg. |
691 | 702 |
692 void neg(Register dst); | 703 void neg(Register dst); |
| 704 void neg(const Operand& dst); |
693 | 705 |
694 void not_(Register dst); | 706 void not_(Register dst); |
| 707 void not_(const Operand& dst); |
695 | 708 |
696 void or_(Register dst, int32_t imm32); | 709 void or_(Register dst, int32_t imm32); |
697 void or_(Register dst, Register src) { or_(dst, Operand(src)); } | 710 void or_(Register dst, Register src) { or_(dst, Operand(src)); } |
698 void or_(Register dst, const Operand& src); | 711 void or_(Register dst, const Operand& src); |
699 void or_(const Operand& dst, Register src); | 712 void or_(const Operand& dst, Register src); |
700 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); } | 713 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); } |
701 void or_(const Operand& dst, const Immediate& x); | 714 void or_(const Operand& dst, const Immediate& x); |
702 | 715 |
703 void rcl(Register dst, uint8_t imm8); | 716 void rcl(Register dst, uint8_t imm8); |
704 void rcr(Register dst, uint8_t imm8); | 717 void rcr(Register dst, uint8_t imm8); |
705 void ror(Register dst, uint8_t imm8); | 718 void ror(Register dst, uint8_t imm8); |
706 void ror_cl(Register dst); | 719 void ror_cl(Register dst); |
707 | 720 |
708 void sar(Register dst, uint8_t imm8); | 721 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); } |
709 void sar_cl(Register dst); | 722 void sar(const Operand& dst, uint8_t imm8); |
| 723 void sar_cl(Register dst) { sar_cl(Operand(dst)); } |
| 724 void sar_cl(const Operand& dst); |
710 | 725 |
711 void sbb(Register dst, const Operand& src); | 726 void sbb(Register dst, const Operand& src); |
712 | 727 |
713 void shld(Register dst, Register src) { shld(dst, Operand(src)); } | 728 void shld(Register dst, Register src) { shld(dst, Operand(src)); } |
714 void shld(Register dst, const Operand& src); | 729 void shld(Register dst, const Operand& src); |
715 | 730 |
716 void shl(Register dst, uint8_t imm8); | 731 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); } |
717 void shl_cl(Register dst); | 732 void shl(const Operand& dst, uint8_t imm8); |
| 733 void shl_cl(Register dst) { shl_cl(Operand(dst)); } |
| 734 void shl_cl(const Operand& dst); |
718 | 735 |
719 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); } | 736 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); } |
720 void shrd(Register dst, const Operand& src); | 737 void shrd(Register dst, const Operand& src); |
721 | 738 |
722 void shr(Register dst, uint8_t imm8); | 739 void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); } |
723 void shr_cl(Register dst); | 740 void shr(const Operand& dst, uint8_t imm8); |
| 741 void shr_cl(Register dst) { shr_cl(Operand(dst)); } |
| 742 void shr_cl(const Operand& dst); |
724 | 743 |
725 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); } | 744 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); } |
726 void sub(const Operand& dst, const Immediate& x); | 745 void sub(const Operand& dst, const Immediate& x); |
727 void sub(Register dst, Register src) { sub(dst, Operand(src)); } | 746 void sub(Register dst, Register src) { sub(dst, Operand(src)); } |
728 void sub(Register dst, const Operand& src); | 747 void sub(Register dst, const Operand& src); |
729 void sub(const Operand& dst, Register src); | 748 void sub(const Operand& dst, Register src); |
730 | 749 |
731 void test(Register reg, const Immediate& imm); | 750 void test(Register reg, const Immediate& imm); |
732 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); } | 751 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); } |
733 void test(Register reg, const Operand& op); | 752 void test(Register reg, const Operand& op); |
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1022 private: | 1041 private: |
1023 Assembler* assembler_; | 1042 Assembler* assembler_; |
1024 #ifdef DEBUG | 1043 #ifdef DEBUG |
1025 int space_before_; | 1044 int space_before_; |
1026 #endif | 1045 #endif |
1027 }; | 1046 }; |
1028 | 1047 |
1029 } } // namespace v8::internal | 1048 } } // namespace v8::internal |
1030 | 1049 |
1031 #endif // V8_X87_ASSEMBLER_X87_H_ | 1050 #endif // V8_X87_ASSEMBLER_X87_H_ |
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