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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// | 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file implements the TargetLoweringX8632 class, which | 10 // This file implements the TargetLoweringX8632 class, which |
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107 #undef X | 107 #undef X |
108 }; | 108 }; |
109 const size_t TableTypeX8632AttributesSize = | 109 const size_t TableTypeX8632AttributesSize = |
110 llvm::array_lengthof(TableTypeX8632Attributes); | 110 llvm::array_lengthof(TableTypeX8632Attributes); |
111 | 111 |
112 // Return the type which the elements of the vector have in the X86 | 112 // Return the type which the elements of the vector have in the X86 |
113 // representation of the vector. | 113 // representation of the vector. |
114 Type getInVectorElementType(Type Ty) { | 114 Type getInVectorElementType(Type Ty) { |
115 assert(isVectorType(Ty)); | 115 assert(isVectorType(Ty)); |
116 size_t Index = static_cast<size_t>(Ty); | 116 size_t Index = static_cast<size_t>(Ty); |
117 (void)Index; | |
117 assert(Index < TableTypeX8632AttributesSize); | 118 assert(Index < TableTypeX8632AttributesSize); |
118 return TableTypeX8632Attributes[Ty].InVectorElementType; | 119 return TableTypeX8632Attributes[Ty].InVectorElementType; |
119 } | 120 } |
120 | 121 |
121 // The maximum number of arguments to pass in XMM registers | 122 // The maximum number of arguments to pass in XMM registers |
122 const unsigned X86_MAX_XMM_ARGS = 4; | 123 const unsigned X86_MAX_XMM_ARGS = 4; |
123 // The number of bits in a byte | 124 // The number of bits in a byte |
124 const unsigned X86_CHAR_BIT = 8; | 125 const unsigned X86_CHAR_BIT = 8; |
125 | 126 |
126 // Return a string representation of the type that is suitable for use | 127 // Return a string representation of the type that is suitable for use |
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2029 assert(Src0->getType() == IceType_v16i1); | 2030 assert(Src0->getType() == IceType_v16i1); |
2030 InstCall *Call = makeHelperCall("Sz_bitcast_v16i1_to_i16", Dest, 1); | 2031 InstCall *Call = makeHelperCall("Sz_bitcast_v16i1_to_i16", Dest, 1); |
2031 Call->addArg(Src0); | 2032 Call->addArg(Src0); |
2032 lowerCall(Call); | 2033 lowerCall(Call); |
2033 } break; | 2034 } break; |
2034 case IceType_i32: | 2035 case IceType_i32: |
2035 case IceType_f32: { | 2036 case IceType_f32: { |
2036 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem); | 2037 Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem); |
2037 Type DestType = Dest->getType(); | 2038 Type DestType = Dest->getType(); |
2038 Type SrcType = Src0RM->getType(); | 2039 Type SrcType = Src0RM->getType(); |
2040 (void)DestType; | |
2039 assert((DestType == IceType_i32 && SrcType == IceType_f32) || | 2041 assert((DestType == IceType_i32 && SrcType == IceType_f32) || |
2040 (DestType == IceType_f32 && SrcType == IceType_i32)); | 2042 (DestType == IceType_f32 && SrcType == IceType_i32)); |
2041 // a.i32 = bitcast b.f32 ==> | 2043 // a.i32 = bitcast b.f32 ==> |
2042 // t.f32 = b.f32 | 2044 // t.f32 = b.f32 |
2043 // s.f32 = spill t.f32 | 2045 // s.f32 = spill t.f32 |
2044 // a.i32 = s.f32 | 2046 // a.i32 = s.f32 |
2045 Variable *T = NULL; | 2047 Variable *T = NULL; |
2046 // TODO: Should be able to force a spill setup by calling legalize() with | 2048 // TODO: Should be able to force a spill setup by calling legalize() with |
2047 // Legal_Mem and not Legal_Reg or Legal_Imm. | 2049 // Legal_Mem and not Legal_Reg or Legal_Imm. |
2048 Variable *Spill = Func->makeVariable(SrcType, Context.getNode()); | 2050 Variable *Spill = Func->makeVariable(SrcType, Context.getNode()); |
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2727 // Make sure that the atomic load isn't elided when unused. | 2729 // Make sure that the atomic load isn't elided when unused. |
2728 Context.insert(InstFakeUse::create(Func, Dest->getLo())); | 2730 Context.insert(InstFakeUse::create(Func, Dest->getLo())); |
2729 Context.insert(InstFakeUse::create(Func, Dest->getHi())); | 2731 Context.insert(InstFakeUse::create(Func, Dest->getHi())); |
2730 return; | 2732 return; |
2731 } | 2733 } |
2732 InstLoad *Load = InstLoad::create(Func, Dest, Instr->getArg(0)); | 2734 InstLoad *Load = InstLoad::create(Func, Dest, Instr->getArg(0)); |
2733 lowerLoad(Load); | 2735 lowerLoad(Load); |
2734 // Make sure the atomic load isn't elided when unused, by adding a FakeUse. | 2736 // Make sure the atomic load isn't elided when unused, by adding a FakeUse. |
2735 // Since lowerLoad may fuse the load w/ an arithmetic instruction, | 2737 // Since lowerLoad may fuse the load w/ an arithmetic instruction, |
2736 // insert the FakeUse on the last-inserted instruction's dest. | 2738 // insert the FakeUse on the last-inserted instruction's dest. |
2737 Context.insert(InstFakeUse::create(Func, | 2739 Context.insert( |
Jim Stichnoth
2014/07/30 18:30:58
sorry, this snuck in despite "make format-diff" :)
| |
2738 Context.getLastInserted()->getDest())); | 2740 InstFakeUse::create(Func, Context.getLastInserted()->getDest())); |
2739 return; | 2741 return; |
2740 } | 2742 } |
2741 case Intrinsics::AtomicRMW: | 2743 case Intrinsics::AtomicRMW: |
2742 if (!Intrinsics::VerifyMemoryOrder( | 2744 if (!Intrinsics::VerifyMemoryOrder( |
2743 llvm::cast<ConstantInteger>(Instr->getArg(3))->getValue())) { | 2745 llvm::cast<ConstantInteger>(Instr->getArg(3))->getValue())) { |
2744 Func->setError("Unexpected memory ordering for AtomicRMW"); | 2746 Func->setError("Unexpected memory ordering for AtomicRMW"); |
2745 return; | 2747 return; |
2746 } | 2748 } |
2747 lowerAtomicRMW(Instr->getDest(), | 2749 lowerAtomicRMW(Instr->getDest(), |
2748 static_cast<uint32_t>(llvm::cast<ConstantInteger>( | 2750 static_cast<uint32_t>(llvm::cast<ConstantInteger>( |
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3120 break; | 3122 break; |
3121 } | 3123 } |
3122 OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Dest->getType()); | 3124 OperandX8632Mem *Addr = FormMemoryOperand(Ptr, Dest->getType()); |
3123 Variable *T = NULL; | 3125 Variable *T = NULL; |
3124 _mov(T, Val); | 3126 _mov(T, Val); |
3125 _xchg(Addr, T); | 3127 _xchg(Addr, T); |
3126 _mov(Dest, T); | 3128 _mov(Dest, T); |
3127 return; | 3129 return; |
3128 } | 3130 } |
3129 // Otherwise, we need a cmpxchg loop. | 3131 // Otherwise, we need a cmpxchg loop. |
3132 (void)NeedsCmpxchg; | |
3130 assert(NeedsCmpxchg); | 3133 assert(NeedsCmpxchg); |
3131 expandAtomicRMWAsCmpxchg(Op_Lo, Op_Hi, Dest, Ptr, Val); | 3134 expandAtomicRMWAsCmpxchg(Op_Lo, Op_Hi, Dest, Ptr, Val); |
3132 } | 3135 } |
3133 | 3136 |
3134 void TargetX8632::expandAtomicRMWAsCmpxchg(LowerBinOp Op_Lo, LowerBinOp Op_Hi, | 3137 void TargetX8632::expandAtomicRMWAsCmpxchg(LowerBinOp Op_Lo, LowerBinOp Op_Hi, |
3135 Variable *Dest, Operand *Ptr, | 3138 Variable *Dest, Operand *Ptr, |
3136 Operand *Val) { | 3139 Operand *Val) { |
3137 // Expand a more complex RMW operation as a cmpxchg loop: | 3140 // Expand a more complex RMW operation as a cmpxchg loop: |
3138 // For 64-bit: | 3141 // For 64-bit: |
3139 // mov eax, [ptr] | 3142 // mov eax, [ptr] |
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4090 for (SizeT i = 0; i < Size; ++i) { | 4093 for (SizeT i = 0; i < Size; ++i) { |
4091 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n"; | 4094 Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n"; |
4092 } | 4095 } |
4093 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; | 4096 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; |
4094 } | 4097 } |
4095 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName | 4098 Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName |
4096 << "\n"; | 4099 << "\n"; |
4097 } | 4100 } |
4098 | 4101 |
4099 } // end of namespace Ice | 4102 } // end of namespace Ice |
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