Subzero: Add support for SSE4.1 instructions.

tests_lit/llvm2ice_tests/vector-ops.ll

 ; This checks support for insertelement and extractelement.
 
-; RUN: %llvm2ice --verbose inst %s | FileCheck %s
+; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
+; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
+; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
+; RUN:                | FileCheck %s --check-prefix=SSE41
+; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
+; RUN:                | FileCheck %s --check-prefix=SSE41
 ; RUN: %llvm2ice -O2 --verbose none %s \
 ; RUN:               | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj
 ; RUN: %llvm2ice -Om1 --verbose none %s \
 ; RUN:               | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj
+; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
+; RUN:               | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj
+; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
+; RUN:               | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj
 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
 ; RUN:                           | FileCheck --check-prefix=DUMP %s
 
 ; insertelement operations
 
 define <4 x float> @insertelement_v4f32_0(<4 x float> %vec, float %elt) {
 entry:
   %res = insertelement <4 x float> %vec, float %elt, i32 0
   ret <4 x float> %res
 ; CHECK-LABEL: insertelement_v4f32_0:
 ; CHECK: movss
+
+; SSE41-LABEL: insertelement_v4f32_0:
+; SSE41: insertps {{.*}}, {{.*}}, 0
 }
 
 define <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) {
 entry:
   %res = insertelement <4 x i32> %vec, i32 %elt, i32 0
   ret <4 x i32> %res
 ; CHECK-LABEL: insertelement_v4i32_0:
 ; CHECK: movss
+
+; SSE41-LABEL: insertelement_v4i32_0:
+; SSE41: pinsrd {{.*}}, {{.*}}, 0
 }
 
 
 define <4 x float> @insertelement_v4f32_1(<4 x float> %vec, float %elt) {
 entry:
   %res = insertelement <4 x float> %vec, float %elt, i32 1
   ret <4 x float> %res
 ; CHECK-LABEL: insertelement_v4f32_1:
 ; CHECK: shufps
 ; CHECK: shufps
+
+; SSE41-LABEL: insertelement_v4f32_1:
+; SSE41: insertps {{.*}}, {{.*}}, 16
 }
 
 define <4 x i32> @insertelement_v4i32_1(<4 x i32> %vec, i32 %elt) {
 entry:
   %res = insertelement <4 x i32> %vec, i32 %elt, i32 1
   ret <4 x i32> %res
 ; CHECK-LABEL: insertelement_v4i32_1:
 ; CHECK: shufps
 ; CHECK: shufps
+
+; SSE41-LABEL: insertelement_v4i32_1:
+; SSE41: pinsrd {{.*}}, {{.*}}, 1
 }
 
 define <8 x i16> @insertelement_v8i16(<8 x i16> %vec, i32 %elt.arg) {
 entry:
   %elt = trunc i32 %elt.arg to i16
   %res = insertelement <8 x i16> %vec, i16 %elt, i32 1
   ret <8 x i16> %res
-; CHECK-LABEL: insertelement_v8i16
+; CHECK-LABEL: insertelement_v8i16:
 ; CHECK: pinsrw
+
+; SSE41-LABEL: insertelement_v8i16:
+; SSE41: pinsrw
 }
 
 define <16 x i8> @insertelement_v16i8(<16 x i8> %vec, i32 %elt.arg) {
 entry:
   %elt = trunc i32 %elt.arg to i8
   %res = insertelement <16 x i8> %vec, i8 %elt, i32 1
   ret <16 x i8> %res
 ; CHECK-LABEL: insertelement_v16i8:
 ; CHECK: movups
 ; CHECK: lea
 ; CHECK: mov
+
+; SSE41-LABEL: insertelement_v16i8:
+; SSE41: pinsrb
 }
 
 define <4 x i1> @insertelement_v4i1_0(<4 x i1> %vec, i32 %elt.arg) {
 entry:
   %elt = trunc i32 %elt.arg to i1
   %res = insertelement <4 x i1> %vec, i1 %elt, i32 0
   ret <4 x i1> %res
 ; CHECK-LABEL: insertelement_v4i1_0:
 ; CHECK: movss
+
+; SSE41-LABEL: insertelement_v4i1_0:
+; SSE41: pinsrd {{.*}}, {{.*}}, 0
 }
 
 define <4 x i1> @insertelement_v4i1_1(<4 x i1> %vec, i32 %elt.arg) {
 entry:
   %elt = trunc i32 %elt.arg to i1
   %res = insertelement <4 x i1> %vec, i1 %elt, i32 1
   ret <4 x i1> %res
 ; CHECK-LABEL: insertelement_v4i1_1:
 ; CHECK: shufps
 ; CHECK: shufps
+
+; SSE41-LABEL: insertelement_v4i1_1:
+; SSE41: pinsrd {{.*}}, {{.*}}, 1
 }
 
 define <8 x i1> @insertelement_v8i1(<8 x i1> %vec, i32 %elt.arg) {
 entry:
   %elt = trunc i32 %elt.arg to i1
   %res = insertelement <8 x i1> %vec, i1 %elt, i32 1
   ret <8 x i1> %res
 ; CHECK-LABEL: insertelement_v8i1:
 ; CHECK: pinsrw
+
+; SSE41-LABEL: insertelement_v8i1:
+; SSE41: pinsrw
 }
 
 define <16 x i1> @insertelement_v16i1(<16 x i1> %vec, i32 %elt.arg) {
 entry:
   %elt = trunc i32 %elt.arg to i1
   %res = insertelement <16 x i1> %vec, i1 %elt, i32 1
   ret <16 x i1> %res
 ; CHECK-LABEL: insertelement_v16i1:
 ; CHECK: movups
 ; CHECK: lea
 ; CHECK: mov
+
+; SSE41-LABEL: insertelement_v16i1:
+; SSE41: pinsrb
 }
 
 ; extractelement operations
 
 define float @extractelement_v4f32(<4 x float> %vec) {
 entry:
   %res = extractelement <4 x float> %vec, i32 1
   ret float %res
 ; CHECK-LABEL: extractelement_v4f32:
 ; CHECK: pshufd
+
+; SSE41-LABEL: extractelement_v4f32:
+; SSE41: pshufd

[jvoung (off chromium), 2014/07/30 04:30:11]

Is the plan to use extractps later?

[wala, 2014/07/30 18:11:55]

No. I now think we should not be using extractps to implement extractelement.

extractps takes reg32/mem32 as the dest operand, so to implement extractelement
of v4f32 with extractps would require an extra operation (like movd) after
extractps to copy the result back into an xmm register. This seems inferior to
pshufd. LLVM uses pshufd even with -mattr=sse4.1.

 }
 
 define i32 @extractelement_v4i32(<4 x i32> %vec) {
 entry:
   %res = extractelement <4 x i32> %vec, i32 1
   ret i32 %res
 ; CHECK-LABEL: extractelement_v4i32:
 ; CHECK: pshufd
+
+; SSE41-LABEL: extractelement_v4i32:
+; SSE41: pextrd
 }
 
 define i32 @extractelement_v8i16(<8 x i16> %vec) {
 entry:
   %res = extractelement <8 x i16> %vec, i32 1
   %res.ext = zext i16 %res to i32
   ret i32 %res.ext
 ; CHECK-LABEL: extractelement_v8i16:
 ; CHECK: pextrw
+
+; SSE41-LABEL: extractelement_v8i16:
+; SSE41: pextrw
 }
 
 define i32 @extractelement_v16i8(<16 x i8> %vec) {
 entry:
   %res = extractelement <16 x i8> %vec, i32 1
   %res.ext = zext i8 %res to i32
   ret i32 %res.ext
 ; CHECK-LABEL: extractelement_v16i8:
 ; CHECK: movups
 ; CHECK: lea
 ; CHECK: mov
+
+; SSE41-LABEL: extractelement_v16i8:
+; SSE41: pextrb
 }
 
 define i32 @extractelement_v4i1(<4 x i1> %vec) {
 entry:
   %res = extractelement <4 x i1> %vec, i32 1
   %res.ext = zext i1 %res to i32
   ret i32 %res.ext
 ; CHECK-LABEL: extractelement_v4i1:
 ; CHECK: pshufd
+
+; SSE41-LABEL: extractelement_v4i1:
+; SSE41: pextrd
 }
 
 define i32 @extractelement_v8i1(<8 x i1> %vec) {
 entry:
   %res = extractelement <8 x i1> %vec, i32 1
   %res.ext = zext i1 %res to i32
   ret i32 %res.ext
 ; CHECK-LABEL: extractelement_v8i1:
 ; CHECK: pextrw
+
+; SSE41-LABEL: extractelement_v8i1:
+; SSE41: pextrw
 }
 
 define i32 @extractelement_v16i1(<16 x i1> %vec) {
 entry:
   %res = extractelement <16 x i1> %vec, i32 1
   %res.ext = zext i1 %res to i32
   ret i32 %res.ext
 ; CHECK-LABEL: extractelement_v16i1:
 ; CHECK: movups
 ; CHECK: lea
 ; CHECK: mov
+
+; SSE41-LABEL: extractelement_v16i1:
+; SSE41: pextrb
 }
 
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ