Subzero: Add support for SSE4.1 instructions.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 435 matching lines @@
     if (ShiftReg && ShiftReg->getRegNum() == TargetX8632::Reg_ecx) {
       Str << "cl";
       EmittedSrc1 = true;
     }
   }
   if (!EmittedSrc1)
     Inst->getSrc(1)->emit(Func);
   Str << "\n";
 }
 
-
 // In-place ops
 template <> const char *InstX8632Bswap::Opcode = "bswap";
 template <> const char *InstX8632Neg::Opcode = "neg";
 // Unary ops
 template <> const char *InstX8632Bsf::Opcode = "bsf";
 template <> const char *InstX8632Bsr::Opcode = "bsr";
 template <> const char *InstX8632Lea::Opcode = "lea";
 template <> const char *InstX8632Movd::Opcode = "movd";
 template <> const char *InstX8632Sqrtss::Opcode = "sqrtss";
 // Binary ops
@@ skipping 10 matching lines @@
 template <> const char *InstX8632And::Opcode = "and";
 template <> const char *InstX8632Pand::Opcode = "pand";
 template <> const char *InstX8632Pandn::Opcode = "pandn";
 template <> const char *InstX8632Or::Opcode = "or";
 template <> const char *InstX8632Por::Opcode = "por";
 template <> const char *InstX8632Xor::Opcode = "xor";
 template <> const char *InstX8632Pxor::Opcode = "pxor";
 template <> const char *InstX8632Imul::Opcode = "imul";
 template <> const char *InstX8632Mulps::Opcode = "mulps";
 template <> const char *InstX8632Mulss::Opcode = "mulss";
-template <> const char *InstX8632Pmullw::Opcode = "pmullw";
+template <> const char *InstX8632Pmull::Opcode = "pmull";
 template <> const char *InstX8632Pmuludq::Opcode = "pmuludq";
 template <> const char *InstX8632Div::Opcode = "div";
 template <> const char *InstX8632Divps::Opcode = "divps";
 template <> const char *InstX8632Idiv::Opcode = "idiv";
 template <> const char *InstX8632Divss::Opcode = "divss";
 template <> const char *InstX8632Rol::Opcode = "rol";
 template <> const char *InstX8632Shl::Opcode = "shl";
 template <> const char *InstX8632Psll::Opcode = "psll";
 template <> const char *InstX8632Shr::Opcode = "shr";
 template <> const char *InstX8632Sar::Opcode = "sar";
 template <> const char *InstX8632Psra::Opcode = "psra";
 template <> const char *InstX8632Pcmpeq::Opcode = "pcmpeq";
 template <> const char *InstX8632Pcmpgt::Opcode = "pcmpgt";
 template <> const char *InstX8632Movss::Opcode = "movss";
 // Ternary ops
+template <> const char *InstX8632Insertps::Opcode = "insertps";
 template <> const char *InstX8632Shufps::Opcode = "shufps";
-template <> const char *InstX8632Pinsrw::Opcode = "pinsrw";
+template <> const char *InstX8632Pinsr::Opcode = "pinsr";
+template <> const char *InstX8632Blendvps::Opcode = "blendvps";
+template <> const char *InstX8632Pblendvb::Opcode = "pblendvb";
 // Three address ops
-template <> const char *InstX8632Pextrw::Opcode = "pextrw";
+template <> const char *InstX8632Pextr::Opcode = "pextr";
 template <> const char *InstX8632Pshufd::Opcode = "pshufd";
 
 template <> void InstX8632Sqrtss::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Type Ty = getSrc(0)->getType();
   assert(Ty == IceType_f32 || Ty == IceType_f64);
   Str << "\tsqrt" << TypeX8632Attributes[Ty].SdSsString << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
   Str << "\n";
 }
 
 template <> void InstX8632Addss::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "add%s",
            TypeX8632Attributes[getDest()->getType()].SdSsString);
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Padd::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "padd%s",
            TypeX8632Attributes[getDest()->getType()].PackString);
   emitTwoAddress(buf, this, Func);
 }
 
+template <> void InstX8632Pmull::emit(const Cfg *Func) const {
+  char buf[30];
+  assert(getDest()->getType() == IceType_v4i32 ||

[Jim Stichnoth, 2014/07/29 23:01:16]

It would be nice if the asserts here and in lowerArithmetic() were syntactically
basically the same.

[wala, 2014/07/30 00:11:24]

I'm not sure what you mean by this. I don't see any relevant asserts in
lowerArithmetic(). Are you suggesting that the asserts should syntactically
match the conditions that generate the instructions in lowerArithmetic()  /
lowerExtractElement() (the latter for pextrw and pextrd)? I have at least two
issues with that suggestion:

1) Breaking up the conditions into multiple assert statements allows for more
precise error messsages.

2) The instructions may be used in other contexts that don't fit the conditions
present in lowerArithmetic() / lowerExtractElement(). For instance, there is no
requirement preventing pextrw or pextrd from having Src0 as a v4f32, despite the
fact that the condition in lowerExtractElement() checks that Src0 is not a
v4f32.

[Jim Stichnoth, 2014/07/30 02:58:56]

I'm talking about lines 1244-1245 of IceTargetLoweringX8632.cpp, which are part
of lowerArithmetic():

  if (Dest->getType() == IceType_v8i16 ||
      (InstructionSet >= SSE4_1 && Dest->getType() == IceType_v4i32)) {

compared to the (slightly paraphrased) asserts here:

  assert(getDest()->getType() == IceType_v4i32 ||
         getDest()->getType() == IceType_v8i16);
  assert(getDest()->getType() != IceType_v4i32 ||
         InstructionSet >= SSE4_1);
Basically, yes (for the conditions I transcribed above).  I had to do more
head-scratching than should be necessary to convince myself that the two
conditions are the same.  What if both sections had code like this:

  bool Blah1 = (getDest()->getType() == IceType_v4i32 ||
                getDest()->getType() == IceType_v8i16);
  bool Blah2 = (getDest()->getType() != IceType_v4i32 ||
                InstructionSet >= SSE4_1);

and the first condition were rewritten as:

  if (Blah1 && Blah2) {

and the asserts were rewritten as:

  assert(Blah1);
  assert(Blah2);
My suggestion allows for that.
OK, this is a great point.  I would adjust my suggestion as follows.  There is
some set of basic structural conditions on the instruction, which the emit()
routine asserts.  The lowering code uses that same set of conditions, plus
possibly some more restrictive conditions, to determine whether to lower to that
instruction.

[wala, 2014/07/30 18:11:55]

Done.

Thanks for the explanation.

+         getDest()->getType() == IceType_v8i16);
+  // pmulld requires SSE4.1.
+  assert(getDest()->getType() != IceType_v4i32 ||
+         static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
+             >= TargetX8632::SSE4_1);
+  snprintf(buf, llvm::array_lengthof(buf), "pmull%s",
+           TypeX8632Attributes[getDest()->getType()].PackString);
+  emitTwoAddress(buf, this, Func);
+}
+
 template <> void InstX8632Subss::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "sub%s",
            TypeX8632Attributes[getDest()->getType()].SdSsString);
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Psub::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "psub%s",
            TypeX8632Attributes[getDest()->getType()].PackString);
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Mulss::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "mul%s",
            TypeX8632Attributes[getDest()->getType()].SdSsString);
   emitTwoAddress(buf, this, Func);
 }
 
-template <> void InstX8632Pmullw::emit(const Cfg *Func) const {
-  assert(getSrc(0)->getType() == IceType_v8i16 &&
-         getSrc(1)->getType() == IceType_v8i16);
-  emitTwoAddress(Opcode, this, Func);
-}
-
 template <> void InstX8632Pmuludq::emit(const Cfg *Func) const {
   assert(getSrc(0)->getType() == IceType_v4i32 &&
          getSrc(1)->getType() == IceType_v4i32);
   emitTwoAddress(Opcode, this, Func);
 }
 
 template <> void InstX8632Divss::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "div%s",
            TypeX8632Attributes[getDest()->getType()].SdSsString);
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Div::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 3);
   Str << "\t" << Opcode << "\t";
   getSrc(1)->emit(Func);
   Str << "\n";
 }
 
 template <> void InstX8632Idiv::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 3);
   Str << "\t" << Opcode << "\t";
   getSrc(1)->emit(Func);
   Str << "\n";
 }
 
+
+namespace {
+
+// pblendvb and blendvps take xmm0 as a final implicit argument.
+void emitVariableBlendInst(const char *Opcode, const Inst *Inst,
+                           const Cfg *Func) {
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(Inst->getSrcSize() == 3);
+  assert(llvm::isa<Variable>(Inst->getSrc(2)));
+  assert(llvm::cast<Variable>(Inst->getSrc(2))->getRegNum() ==
+         TargetX8632::Reg_xmm0);
+  Str << "\t" << Opcode << "\t";
+  Inst->getDest()->emit(Func);
+  Str << ", ";
+  Inst->getSrc(1)->emit(Func);
+  Str << "\n";
+}
+
+} // end anonymous namespace
+
+template <> void InstX8632Blendvps::emit(const Cfg *Func) const {
+  assert(static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
+         TargetX8632::SSE4_1);
+  emitVariableBlendInst(Opcode, this, Func);
+}
+
+template <> void InstX8632Pblendvb::emit(const Cfg *Func) const {
+  assert(static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
+         TargetX8632::SSE4_1);
+  emitVariableBlendInst(Opcode, this, Func);
+}
+
 template <> void InstX8632Imul::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   if (getDest()->getType() == IceType_i8) {
     // The 8-bit version of imul only allows the form "imul r/m8".
     Variable *Src0 = llvm::dyn_cast<Variable>(getSrc(0));
     assert(Src0 && Src0->getRegNum() == TargetX8632::Reg_eax);
     Str << "\timul\t";
     getSrc(1)->emit(Func);
     Str << "\n";
@@ skipping 519 matching lines @@
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Pcmpgt::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "pcmpgt%s",
            TypeX8632Attributes[getDest()->getType()].PackString);
   emitTwoAddress(buf, this, Func);
 }
 
-template <> void InstX8632Pextrw::emit(const Cfg *Func) const {
+template <> void InstX8632Pextr::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
-  Str << "\t" << Opcode << "\t";
+  // pextrb and pextrd are SSE4.1 instructions.
+  assert(getSrc(0)->getType() == IceType_v8i16 ||

[Jim Stichnoth, 2014/07/29 23:01:16]

Same comment about syntactically equivalent asserts.

[wala, 2014/07/30 00:11:24]

See reply above.

[wala, 2014/07/30 18:11:55]

Done.

+         getSrc(0)->getType() == IceType_v8i1 ||
+         static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
+             >= TargetX8632::SSE4_1);
+  Str << "\t" << Opcode
+      << TypeX8632Attributes[getSrc(0)->getType()].PackString << "\t";
   Variable *Dest = getDest();
-  assert(Dest->hasReg() && Dest->getType() == IceType_i16);
-  // pextrw takes r32 dest.
+  // pextrw must take a register dest.
+  assert(Dest->getType() != IceType_i16 || Dest->hasReg());
   Dest->asType(IceType_i32).emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
   Str << ", ";
   getSrc(1)->emit(Func);
   Str << "\n";
 }
 
-template <> void InstX8632Pinsrw::emit(const Cfg *Func) const {
+template <> void InstX8632Pinsr::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 3);
-  Str << "\t" << Opcode << "\t";
+  // pinsrb and pinsrd are SSE4.1 instructions.
+  assert(getDest()->getType() == IceType_v8i16 ||
+         getDest()->getType() == IceType_v8i1 ||
+         static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
+             >= TargetX8632::SSE4_1);
+  Str << "\t" << Opcode
+      << TypeX8632Attributes[getDest()->getType()].PackString << "\t";
   getDest()->emit(Func);
   Str << ", ";
   Operand *Src1 = getSrc(1);
   if (Variable *VSrc1 = llvm::dyn_cast<Variable>(Src1)) {
-    // If src1 is a register, it should be r32.
-    VSrc1->asType(VSrc1->hasReg() ? IceType_i32 : IceType_i16).emit(Func);
+    // If src1 is a register, it should always be r32.
+    if (VSrc1->hasReg()) {
+      VSrc1->asType(IceType_i32).emit(Func);
+    } else {
+      VSrc1->emit(Func);
+    }
   } else {
     Src1->emit(Func);
   }
   Str << ", ";
   getSrc(2)->emit(Func);
   Str << "\n";
 }
 
 void InstX8632Pop::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
@@ skipping 44 matching lines @@
 }
 
 void InstX8632Push::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "push." << getSrc(0)->getType() << " ";
   dumpSources(Func);
 }
 
 template <> void InstX8632Psll::emit(const Cfg *Func) const {
   assert(getDest()->getType() == IceType_v8i16 ||
-         getDest()->getType() == IceType_v4i32);
+         getDest()->getType() == IceType_v8i1 ||
+         getDest()->getType() == IceType_v4i32 ||
+         getDest()->getType() == IceType_v4i1);
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "psll%s",
            TypeX8632Attributes[getDest()->getType()].PackString);
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Psra::emit(const Cfg *Func) const {
   assert(getDest()->getType() == IceType_v8i16 ||
-         getDest()->getType() == IceType_v4i32);
+         getDest()->getType() == IceType_v8i1 ||
+         getDest()->getType() == IceType_v4i32 ||
+         getDest()->getType() == IceType_v4i1);
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "psra%s",
            TypeX8632Attributes[getDest()->getType()].PackString);
   emitTwoAddress(buf, this, Func);
 }
 
 void InstX8632Ret::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\tret\n";
 }
@@ skipping 169 matching lines @@
   default:
     Str << "???";
     break;
   }
   Str << "(";
   Var->dump(Func);
   Str << ")";
 }
 
 } // end of namespace Ice