OLD | NEW |
1 ; This test checks support for vector arithmetic. | 1 ; This test checks support for vector arithmetic. |
2 | 2 |
3 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s | 3 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s |
4 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s | 4 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s |
| 5 ; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \ |
| 6 ; RUN: | FileCheck %s --check-prefix=SSE41 |
| 7 ; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \ |
| 8 ; RUN: | FileCheck %s --check-prefix=SSE41 |
5 ; RUN: %llvm2ice -O2 --verbose none %s \ | 9 ; RUN: %llvm2ice -O2 --verbose none %s \ |
6 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj | 10 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj |
7 ; RUN: %llvm2ice -Om1 --verbose none %s \ | 11 ; RUN: %llvm2ice -Om1 --verbose none %s \ |
8 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj | 12 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj |
| 13 ; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \ |
| 14 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj |
| 15 ; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \ |
| 16 ; RUN: | llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj |
9 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s | 17 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s |
10 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s | 18 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s |
11 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ | 19 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ |
12 ; RUN: | FileCheck --check-prefix=DUMP %s | 20 ; RUN: | FileCheck --check-prefix=DUMP %s |
13 | 21 |
14 define <4 x float> @test_fadd(<4 x float> %arg0, <4 x float> %arg1) { | 22 define <4 x float> @test_fadd(<4 x float> %arg0, <4 x float> %arg1) { |
15 entry: | 23 entry: |
16 %res = fadd <4 x float> %arg0, %arg1 | 24 %res = fadd <4 x float> %arg0, %arg1 |
17 ret <4 x float> %res | 25 ret <4 x float> %res |
18 ; CHECK-LABEL: test_fadd: | 26 ; CHECK-LABEL: test_fadd: |
(...skipping 280 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
299 ; CHECK: psubd | 307 ; CHECK: psubd |
300 } | 308 } |
301 | 309 |
302 define <4 x i32> @test_mul_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { | 310 define <4 x i32> @test_mul_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { |
303 entry: | 311 entry: |
304 %res = mul <4 x i32> %arg0, %arg1 | 312 %res = mul <4 x i32> %arg0, %arg1 |
305 ret <4 x i32> %res | 313 ret <4 x i32> %res |
306 ; CHECK-LABEL: test_mul_v4i32: | 314 ; CHECK-LABEL: test_mul_v4i32: |
307 ; CHECK: pmuludq | 315 ; CHECK: pmuludq |
308 ; CHECK: pmuludq | 316 ; CHECK: pmuludq |
| 317 ; |
| 318 ; SSE41-LABEL: test_mul_v4i32: |
| 319 ; SSE41: pmulld |
309 } | 320 } |
310 | 321 |
311 define <4 x i32> @test_shl_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { | 322 define <4 x i32> @test_shl_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { |
312 entry: | 323 entry: |
313 %res = shl <4 x i32> %arg0, %arg1 | 324 %res = shl <4 x i32> %arg0, %arg1 |
314 ret <4 x i32> %res | 325 ret <4 x i32> %res |
315 ; CHECK-LABEL: test_shl_v4i32: | 326 ; CHECK-LABEL: test_shl_v4i32: |
316 ; CHECK: Sz_shl_v4i32 | 327 ; CHECK: Sz_shl_v4i32 |
| 328 |
| 329 ; This line is to ensure that pmulld is generated in test_mul_v4i32 above. |
| 330 ; SSE41-LABEL: test_shl_v4i32: |
317 } | 331 } |
318 | 332 |
319 define <4 x i32> @test_lshr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { | 333 define <4 x i32> @test_lshr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { |
320 entry: | 334 entry: |
321 %res = lshr <4 x i32> %arg0, %arg1 | 335 %res = lshr <4 x i32> %arg0, %arg1 |
322 ret <4 x i32> %res | 336 ret <4 x i32> %res |
323 ; CHECK-LABEL: test_lshr_v4i32: | 337 ; CHECK-LABEL: test_lshr_v4i32: |
324 ; CHECK: Sz_lshr_v4i32 | 338 ; CHECK: Sz_lshr_v4i32 |
325 } | 339 } |
326 | 340 |
(...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
359 define <4 x i32> @test_srem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { | 373 define <4 x i32> @test_srem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) { |
360 entry: | 374 entry: |
361 %res = srem <4 x i32> %arg0, %arg1 | 375 %res = srem <4 x i32> %arg0, %arg1 |
362 ret <4 x i32> %res | 376 ret <4 x i32> %res |
363 ; CHECK-LABEL: test_srem_v4i32: | 377 ; CHECK-LABEL: test_srem_v4i32: |
364 ; CHECK: Sz_srem_v4i32 | 378 ; CHECK: Sz_srem_v4i32 |
365 } | 379 } |
366 | 380 |
367 ; ERRORS-NOT: ICE translation error | 381 ; ERRORS-NOT: ICE translation error |
368 ; DUMP-NOT: SZ | 382 ; DUMP-NOT: SZ |
OLD | NEW |