Subzero: Add support for SSE4.1 instructions.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
 // consists almost entirely of the lowering sequence for each
 // high-level instruction.  It also implements
 // TargetX8632Fast::postLower() which does the simplest possible
 // register allocation for the "fast" target.
 //
 //===----------------------------------------------------------------------===//
 
 #include "IceDefs.h"
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceInstX8632.h"
 #include "IceOperand.h"
 #include "IceTargetLoweringX8632.def"
 #include "IceTargetLoweringX8632.h"
+#include "llvm/Support/CommandLine.h"
 
 namespace Ice {
 
 namespace {
 
 // The following table summarizes the logic for lowering the fcmp
 // instruction.  There is one table entry for each of the 16 conditions.
 //
 // The first four columns describe the case when the operands are
 // floating point scalar values.  A comment in lowerFcmp() describes the
@@ skipping 81 matching lines @@
   size_t Index = static_cast<size_t>(Ty);
   assert(Index < TableTypeX8632AttributesSize);
   return TableTypeX8632Attributes[Ty].InVectorElementType;
 }
 
 // The maximum number of arguments to pass in XMM registers
 const unsigned X86_MAX_XMM_ARGS = 4;
 // The number of bits in a byte
 const unsigned X86_CHAR_BIT = 8;
 
+// Instruction set options
+namespace cl = ::llvm::cl;
+cl::opt<TargetX8632::X86InstructionSet> CLInstructionSet(
+    "mattr", cl::desc("X86 target attributes"),
+    cl::init(TargetX8632::SSE2),
+    cl::values(
+        clEnumValN(TargetX8632::SSE2, "sse2",
+                   "Enable SSE2 instructions (default)"),
+        clEnumValN(TargetX8632::SSE4_1, "sse4.1",
+                   "Enable SSE 4.1 instructions"), clEnumValEnd));
+
 // Return a string representation of the type that is suitable for use
 // in an identifier.
 IceString typeIdentString(const Type Ty) {
   IceString Str;
   llvm::raw_string_ostream BaseOS(Str);
   if (isVectorType(Ty)) {
     BaseOS << "v" << typeNumElements(Ty) << typeElementType(Ty);
   } else {
     BaseOS << Ty;
   }
@@ skipping 91 matching lines @@
 #define X(tag, size, align, elts, elty, str)                                   \
   STATIC_ASSERT(_table1_##tag == _table2_##tag);
     ICETYPE_TABLE;
 #undef X
   }
 }
 
 } // end of anonymous namespace
 
 TargetX8632::TargetX8632(Cfg *Func)
-    : TargetLowering(Func), IsEbpBasedFrame(false), FrameSizeLocals(0),
-      LocalsSizeBytes(0), NextLabelNumber(0), ComputedLiveRanges(false),
+    : TargetLowering(Func), InstructionSet(CLInstructionSet),
+      IsEbpBasedFrame(false), FrameSizeLocals(0), LocalsSizeBytes(0),
+      NextLabelNumber(0), ComputedLiveRanges(false),
       PhysicalRegisters(VarList(Reg_NUM)) {
   // TODO: Don't initialize IntegerRegisters and friends every time.
   // Instead, initialize in some sort of static initializer for the
   // class.
   llvm::SmallBitVector IntegerRegisters(Reg_NUM);
   llvm::SmallBitVector IntegerRegistersI8(Reg_NUM);
   llvm::SmallBitVector FloatRegisters(Reg_NUM);
   llvm::SmallBitVector VectorRegisters(Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(Reg_NUM);
   ScratchRegs.resize(Reg_NUM);
@@ skipping 972 matching lines @@
       _pxor(T, LEGAL_HACK(Src1));
       _movp(Dest, T);
     } break;
     case InstArithmetic::Sub: {
       Variable *T = makeReg(Dest->getType());
       _movp(T, Src0);
       _psub(T, LEGAL_HACK(Src1));
       _movp(Dest, T);
     } break;
     case InstArithmetic::Mul: {
-      if (Dest->getType() == IceType_v4i32) {
+      bool TypesAreValidForPmull =
+          Dest->getType() == IceType_v4i32 || Dest->getType() == IceType_v8i16;
+      bool InstructionSetIsValidForPmull =
+          Dest->getType() == IceType_v8i16 || InstructionSet >= SSE4_1;
+      if (TypesAreValidForPmull && InstructionSetIsValidForPmull) {
+        Variable *T = makeReg(Dest->getType());
+        _movp(T, Src0);
+        _pmull(T, legalizeToVar(Src1));
+        _movp(Dest, T);
+      } else if (Dest->getType() == IceType_v4i32) {
         // Lowering sequence:
         // Note: The mask arguments have index 0 on the left.
         //
         // movups  T1, Src0
         // pshufd  T2, Src0, {1,0,3,0}
         // pshufd  T3, Src1, {1,0,3,0}
         // # T1 = {Src0[0] * Src1[0], Src0[2] * Src1[2]}
         // pmuludq T1, Src1
         // # T2 = {Src0[1] * Src1[1], Src0[3] * Src1[3]}
         // pmuludq T2, T3
         // # T1 = {lo(T1[0]), lo(T1[2]), lo(T2[0]), lo(T2[2])}
         // shufps  T1, T2, {0,2,0,2}
         // pshufd  T4, T1, {0,2,1,3}
         // movups  Dest, T4
-        //
-        // TODO(wala): SSE4.1 has pmulld.
 
         // Mask that directs pshufd to create a vector with entries
         // Src[1, 0, 3, 0]
         const unsigned Constant1030 = 0x31;
         Constant *Mask1030 = Ctx->getConstantInt(IceType_i8, Constant1030);
         // Mask that directs shufps to create a vector with entries
         // Dest[0, 2], Src[0, 2]
         const unsigned Mask0202 = 0x88;
         // Mask that directs pshufd to create a vector with entries
         // Src[0, 2, 1, 3]
         const unsigned Mask0213 = 0xd8;
         Variable *T1 = makeReg(IceType_v4i32);
         Variable *T2 = makeReg(IceType_v4i32);
         Variable *T3 = makeReg(IceType_v4i32);
         Variable *T4 = makeReg(IceType_v4i32);
         _movp(T1, Src0);
         // TODO(wala): ALIGHNHACK: Replace Src0R with Src0 and Src1R
         // with Src1 after stack operand alignment support is
         // implemented.
         Variable *Src0R = LEGAL_HACK(Src0);
         Variable *Src1R = LEGAL_HACK(Src1);
         _pshufd(T2, Src0R, Mask1030);
         _pshufd(T3, Src1R, Mask1030);
         _pmuludq(T1, Src1R);
         _pmuludq(T2, T3);
         _shufps(T1, T2, Ctx->getConstantInt(IceType_i8, Mask0202));
         _pshufd(T4, T1, Ctx->getConstantInt(IceType_i8, Mask0213));
         _movp(Dest, T4);
-      } else if (Dest->getType() == IceType_v8i16) {
-        Variable *T = makeReg(IceType_v8i16);
-        _movp(T, Src0);
-        _pmullw(T, legalizeToVar(Src1));
-        _movp(Dest, T);
       } else {
         assert(Dest->getType() == IceType_v16i8);
         // Sz_mul_v16i8
         const IceString Helper = "Sz_mul_v16i8";
         const SizeT MaxSrcs = 2;
         InstCall *Call = makeHelperCall(Helper, Dest, MaxSrcs);
         Call->addArg(Src0);
         Call->addArg(Src1);
         lowerCall(Call);
       }
@@ skipping 857 matching lines @@
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
 
   unsigned Index = ElementIndex->getValue();
   Type Ty = SourceVectOperand->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = getInVectorElementType(Ty);
   Variable *ExtractedElement = makeReg(InVectorElementTy);
 
   // TODO(wala): Determine the best lowering sequences for each type.
-  if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
-    // Lower extractelement operations where the element is 32 bits
-    // wide with pshufd.
-    // TODO(wala): SSE4.1 has extractps and pextrd
+  bool CanUsePextr =
+      Ty == IceType_v8i16 || Ty == IceType_v8i1 || InstructionSet >= SSE4_1;
+  if (CanUsePextr && Ty != IceType_v4f32) {
+    // Use pextrb, pextrw, or pextrd.
+    Constant *Mask = Ctx->getConstantInt(IceType_i8, Index);
+    Variable *SourceVectR = legalizeToVar(SourceVectOperand);
+    _pextr(ExtractedElement, SourceVectR, Mask);
+  } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
+    // Use pshufd and movd/movss.
     //
     // ALIGNHACK: Force vector operands to registers in instructions that
     // require aligned memory operands until support for stack alignment
     // is implemented.
 #define ALIGN_HACK(Vect) legalizeToVar((Vect))
     Variable *T = NULL;
     if (Index) {
       // The shuffle only needs to occur if the element to be extracted
       // is not at the lowest index.
       Constant *Mask = Ctx->getConstantInt(IceType_i8, Index);
       T = makeReg(Ty);
       _pshufd(T, ALIGN_HACK(SourceVectOperand), Mask);
     } else {
       T = legalizeToVar(SourceVectOperand);
     }
 
     if (InVectorElementTy == IceType_i32) {
       _movd(ExtractedElement, T);
     } else { // Ty == Icetype_f32
       // TODO(wala): _movss is only used here because _mov does not
       // allow a vector source and a scalar destination.  _mov should be
       // able to be used here.
       // _movss is a binary instruction, so the FakeDef is needed to
       // keep the live range analysis consistent.
       Context.insert(InstFakeDef::create(Func, ExtractedElement));
       _movss(ExtractedElement, T);
     }
 #undef ALIGN_HACK
-  } else if (Ty == IceType_v8i16 || Ty == IceType_v8i1) {
-    Constant *Mask = Ctx->getConstantInt(IceType_i8, Index);
-    _pextrw(ExtractedElement, legalizeToVar(SourceVectOperand), Mask);
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and do the extraction in memory.
-    // TODO(wala): SSE4.1 has pextrb.
     //
     // TODO(wala): use legalize(SourceVectOperand, Legal_Mem) when
     // support for legalizing to mem is implemented.
     Variable *Slot = Func->makeVariable(Ty, Context.getNode());
     Slot->setWeight(RegWeight::Zero);
     _movp(Slot, legalizeToVar(SourceVectOperand));
 
     // Compute the location of the element in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     OperandX8632Mem *Loc =
@@ skipping 325 matching lines @@
     // Expand the element to the appropriate size for it to be inserted
     // in the vector.
     Variable *Expanded =
         Func->makeVariable(InVectorElementTy, Context.getNode());
     InstCast *Cast =
         InstCast::create(Func, InstCast::Zext, Expanded, ElementToInsert);
     lowerCast(Cast);
     ElementToInsert = Expanded;
   }
 
-  if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
-    // Lower insertelement with 32-bit wide elements using shufps or
-    // movss.
-    // TODO(wala): SSE4.1 has pinsrd and insertps.
+  if (Ty == IceType_v8i16 || Ty == IceType_v8i1 || InstructionSet >= SSE4_1) {
+    // Use insertps, pinsrb, pinsrw, or pinsrd.
+    Operand *Element = legalize(ElementToInsert, Legal_Mem | Legal_Reg);
+    Variable *T = makeReg(Ty);
+    _movp(T, SourceVectOperand);
+    if (Ty == IceType_v4f32)
+      _insertps(T, Element, Ctx->getConstantInt(IceType_i8, Index << 4));
+    else
+      _pinsr(T, Element, Ctx->getConstantInt(IceType_i8, Index));
+    _movp(Inst->getDest(), T);
+  } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
+    // Use shufps or movss.
     Variable *Element = NULL;
     if (InVectorElementTy == IceType_f32) {
       // Element will be in an XMM register since it is floating point.
       Element = legalizeToVar(ElementToInsert);
     } else {
       // Copy an integer to an XMM register.
       Operand *T = legalize(ElementToInsert, Legal_Reg | Legal_Mem);
       Element = makeReg(Ty);
       _movd(Element, T);
     }
@@ skipping 44 matching lines @@
       _shufps(Element, SourceVectOperand, Mask2Constant);
       _movp(Inst->getDest(), Element);
     } else {
       Variable *T = makeReg(Ty);
       _movp(T, SourceVectOperand);
       _shufps(Element, T, Mask1Constant);
       _shufps(T, Element, Mask2Constant);
       _movp(Inst->getDest(), T);
     }
 #undef ALIGN_HACK
-  } else if (Ty == IceType_v8i16 || Ty == IceType_v8i1) {
-    Operand *Element = legalize(ElementToInsert, Legal_Mem | Legal_Reg);
-    Variable *T = makeReg(Ty);
-    _movp(T, SourceVectOperand);
-    _pinsrw(T, Element, Ctx->getConstantInt(IceType_i8, Index));
-    _movp(Inst->getDest(), T);
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and perform the insertion in
     // memory.
-    // TODO(wala): SSE4.1 has pinsrb.
     //
     // TODO(wala): use legalize(SourceVectOperand, Legal_Mem) when
     // support for legalizing to mem is implemented.
     Variable *Slot = Func->makeVariable(Ty, Context.getNode());
     Slot->setWeight(RegWeight::Zero);
     _movp(Slot, legalizeToVar(SourceVectOperand));
 
     // Compute the location of the position to insert in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     OperandX8632Mem *Loc =
@@ skipping 913 matching lines @@
   Context.insert(InstFakeUse::create(Func, esp));
 }
 
 void TargetX8632::lowerSelect(const InstSelect *Inst) {
   Variable *Dest = Inst->getDest();
   Operand *SrcT = Inst->getTrueOperand();
   Operand *SrcF = Inst->getFalseOperand();
   Operand *Condition = Inst->getCondition();
 
   if (isVectorType(Dest->getType())) {
-    // a=d?b:c ==> d=sext(d); a=(b&d)|(c&~d)
-    // TODO(wala): SSE4.1 has blendvps and pblendvb.  SSE4.1 also has
-    // blendps and pblendw for constant condition operands.
     Type SrcTy = SrcT->getType();
     Variable *T = makeReg(SrcTy);
+    // ALIGNHACK: Until stack alignment support is implemented, vector
+    // instructions need to have vector operands in registers.  Once
+    // there is support for stack alignment, LEGAL_HACK can be removed.
+#define LEGAL_HACK(Vect) legalizeToVar((Vect))
+    if (InstructionSet >= SSE4_1) {
+      // TODO(wala): If the condition operand is a constant, use blendps
+      // or pblendw.
+      //
+      // Use blendvps or pblendvb to implement select.
+      if (SrcTy == IceType_v4i1 || SrcTy == IceType_v4i32 ||
+          SrcTy == IceType_v4f32) {
+        Variable *xmm0 = makeReg(IceType_v4i32, Reg_xmm0);
+        _movp(xmm0, Condition);
+        _psll(xmm0, Ctx->getConstantInt(IceType_i8, 31));
+        _movp(T, SrcF);
+        _blendvps(T, LEGAL_HACK(SrcT), xmm0);
+        _movp(Dest, T);
+      } else {
+        assert(typeNumElements(SrcTy) == 8 || typeNumElements(SrcTy) == 16);
+        Type SignExtTy = Condition->getType() == IceType_v8i1 ? IceType_v8i16
+            : IceType_v16i8;
+        Variable *xmm0 = makeReg(SignExtTy, Reg_xmm0);
+        lowerCast(InstCast::create(Func, InstCast::Sext, xmm0, Condition));
+        _movp(T, SrcF);
+        _pblendvb(T, LEGAL_HACK(SrcT), xmm0);
+        _movp(Dest, T);
+      }
+      return;
+    }
+    // Lower select without SSE4.1:
+    // a=d?b:c ==>
+    //   if elementtype(d) != i1:
+    //      d=sext(d);
+    //   a=(b&d)|(c&~d);
     Variable *T2 = makeReg(SrcTy);
     // Sign extend the condition operand if applicable.
     if (SrcTy == IceType_v4f32) {
       // The sext operation takes only integer arguments.
       Variable *T3 = Func->makeVariable(IceType_v4i32, Context.getNode());
       lowerCast(InstCast::create(Func, InstCast::Sext, T3, Condition));
       _movp(T, T3);
     } else if (typeElementType(SrcTy) != IceType_i1) {
       lowerCast(InstCast::create(Func, InstCast::Sext, T, Condition));
     } else {
       _movp(T, Condition);
     }
-    // ALIGNHACK: Until stack alignment support is implemented, the
-    // bitwise vector instructions need to have both operands in
-    // registers.  Once there is support for stack alignment, LEGAL_HACK
-    // can be removed.
-#define LEGAL_HACK(Vect) legalizeToVar((Vect))
     _movp(T2, T);
     _pand(T, LEGAL_HACK(SrcT));
     _pandn(T2, LEGAL_HACK(SrcF));
     _por(T, T2);
     _movp(Dest, T);
 #undef LEGAL_HACK
 
     return;
   }
 
@@ skipping 504 matching lines @@
     for (SizeT i = 0; i < Size; ++i) {
       Str << "\t.byte\t" << (((unsigned)Data[i]) & 0xff) << "\n";
     }
     Str << "\t.size\t" << MangledName << ", " << Size << "\n";
   }
   Str << "\t" << (IsInternal ? ".local" : ".global") << "\t" << MangledName
       << "\n";
 }
 
 } // end of namespace Ice