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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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450 // but it may be bound only once. | 450 // but it may be bound only once. |
451 void bind(Label* L); // Binds an unbound label L to current code position. | 451 void bind(Label* L); // Binds an unbound label L to current code position. |
452 // Determines if Label is bound and near enough so that branch instruction | 452 // Determines if Label is bound and near enough so that branch instruction |
453 // can be used to reach it, instead of jump instruction. | 453 // can be used to reach it, instead of jump instruction. |
454 bool is_near(Label* L); | 454 bool is_near(Label* L); |
455 | 455 |
456 // Returns the branch offset to the given label from the current code | 456 // Returns the branch offset to the given label from the current code |
457 // position. Links the label to the current position if it is still unbound. | 457 // position. Links the label to the current position if it is still unbound. |
458 // Manages the jump elimination optimization if the second parameter is true. | 458 // Manages the jump elimination optimization if the second parameter is true. |
459 int32_t branch_offset(Label* L, bool jump_elimination_allowed); | 459 int32_t branch_offset(Label* L, bool jump_elimination_allowed); |
| 460 int32_t branch_offset_compact(Label* L, bool jump_elimination_allowed); |
| 461 int32_t branch_offset21(Label* L, bool jump_elimination_allowed); |
| 462 int32_t branch_offset21_compact(Label* L, bool jump_elimination_allowed); |
460 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) { | 463 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) { |
461 int32_t o = branch_offset(L, jump_elimination_allowed); | 464 int32_t o = branch_offset(L, jump_elimination_allowed); |
462 ASSERT((o & 3) == 0); // Assert the offset is aligned. | 465 ASSERT((o & 3) == 0); // Assert the offset is aligned. |
463 return o >> 2; | 466 return o >> 2; |
464 } | 467 } |
| 468 int32_t shifted_branch_offset_compact(Label* L, |
| 469 bool jump_elimination_allowed) { |
| 470 int32_t o = branch_offset_compact(L, jump_elimination_allowed); |
| 471 ASSERT((o & 3) == 0); // Assert the offset is aligned. |
| 472 return o >> 2; |
| 473 } |
465 uint64_t jump_address(Label* L); | 474 uint64_t jump_address(Label* L); |
466 | 475 |
467 // Puts a labels target address at the given position. | 476 // Puts a labels target address at the given position. |
468 // The high 8 bits are set to zero. | 477 // The high 8 bits are set to zero. |
469 void label_at_put(Label* L, int at_offset); | 478 void label_at_put(Label* L, int at_offset); |
470 | 479 |
471 // Read/Modify the code target address in the branch/call instruction at pc. | 480 // Read/Modify the code target address in the branch/call instruction at pc. |
472 static Address target_address_at(Address pc); | 481 static Address target_address_at(Address pc); |
473 static void set_target_address_at(Address pc, | 482 static void set_target_address_at(Address pc, |
474 Address target, | 483 Address target, |
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610 void b(int16_t offset); | 619 void b(int16_t offset); |
611 void b(Label* L) { b(branch_offset(L, false)>>2); } | 620 void b(Label* L) { b(branch_offset(L, false)>>2); } |
612 void bal(int16_t offset); | 621 void bal(int16_t offset); |
613 void bal(Label* L) { bal(branch_offset(L, false)>>2); } | 622 void bal(Label* L) { bal(branch_offset(L, false)>>2); } |
614 | 623 |
615 void beq(Register rs, Register rt, int16_t offset); | 624 void beq(Register rs, Register rt, int16_t offset); |
616 void beq(Register rs, Register rt, Label* L) { | 625 void beq(Register rs, Register rt, Label* L) { |
617 beq(rs, rt, branch_offset(L, false) >> 2); | 626 beq(rs, rt, branch_offset(L, false) >> 2); |
618 } | 627 } |
619 void bgez(Register rs, int16_t offset); | 628 void bgez(Register rs, int16_t offset); |
| 629 void bgezc(Register rt, int16_t offset); |
| 630 void bgezc(Register rt, Label* L) { |
| 631 bgezc(rt, branch_offset_compact(L, false)>>2); |
| 632 } |
| 633 void bgeuc(Register rs, Register rt, int16_t offset); |
| 634 void bgeuc(Register rs, Register rt, Label* L) { |
| 635 bgeuc(rs, rt, branch_offset_compact(L, false)>>2); |
| 636 } |
| 637 void bgec(Register rs, Register rt, int16_t offset); |
| 638 void bgec(Register rs, Register rt, Label* L) { |
| 639 bgec(rs, rt, branch_offset_compact(L, false)>>2); |
| 640 } |
620 void bgezal(Register rs, int16_t offset); | 641 void bgezal(Register rs, int16_t offset); |
| 642 void bgezalc(Register rt, int16_t offset); |
| 643 void bgezalc(Register rt, Label* L) { |
| 644 bgezalc(rt, branch_offset_compact(L, false)>>2); |
| 645 } |
| 646 void bgezall(Register rs, int16_t offset); |
| 647 void bgezall(Register rs, Label* L) { |
| 648 bgezall(rs, branch_offset(L, false)>>2); |
| 649 } |
621 void bgtz(Register rs, int16_t offset); | 650 void bgtz(Register rs, int16_t offset); |
| 651 void bgtzc(Register rt, int16_t offset); |
| 652 void bgtzc(Register rt, Label* L) { |
| 653 bgtzc(rt, branch_offset_compact(L, false)>>2); |
| 654 } |
622 void blez(Register rs, int16_t offset); | 655 void blez(Register rs, int16_t offset); |
| 656 void blezc(Register rt, int16_t offset); |
| 657 void blezc(Register rt, Label* L) { |
| 658 blezc(rt, branch_offset_compact(L, false)>>2); |
| 659 } |
623 void bltz(Register rs, int16_t offset); | 660 void bltz(Register rs, int16_t offset); |
| 661 void bltzc(Register rt, int16_t offset); |
| 662 void bltzc(Register rt, Label* L) { |
| 663 bltzc(rt, branch_offset_compact(L, false)>>2); |
| 664 } |
| 665 void bltuc(Register rs, Register rt, int16_t offset); |
| 666 void bltuc(Register rs, Register rt, Label* L) { |
| 667 bltuc(rs, rt, branch_offset_compact(L, false)>>2); |
| 668 } |
| 669 void bltc(Register rs, Register rt, int16_t offset); |
| 670 void bltc(Register rs, Register rt, Label* L) { |
| 671 bltc(rs, rt, branch_offset_compact(L, false)>>2); |
| 672 } |
| 673 |
624 void bltzal(Register rs, int16_t offset); | 674 void bltzal(Register rs, int16_t offset); |
| 675 void blezalc(Register rt, int16_t offset); |
| 676 void blezalc(Register rt, Label* L) { |
| 677 blezalc(rt, branch_offset_compact(L, false)>>2); |
| 678 } |
| 679 void bltzalc(Register rt, int16_t offset); |
| 680 void bltzalc(Register rt, Label* L) { |
| 681 bltzalc(rt, branch_offset_compact(L, false)>>2); |
| 682 } |
| 683 void bgtzalc(Register rt, int16_t offset); |
| 684 void bgtzalc(Register rt, Label* L) { |
| 685 bgtzalc(rt, branch_offset_compact(L, false)>>2); |
| 686 } |
| 687 void beqzalc(Register rt, int16_t offset); |
| 688 void beqzalc(Register rt, Label* L) { |
| 689 beqzalc(rt, branch_offset_compact(L, false)>>2); |
| 690 } |
| 691 void beqc(Register rs, Register rt, int16_t offset); |
| 692 void beqc(Register rs, Register rt, Label* L) { |
| 693 beqc(rs, rt, branch_offset_compact(L, false)>>2); |
| 694 } |
| 695 void beqzc(Register rs, int32_t offset); |
| 696 void beqzc(Register rs, Label* L) { |
| 697 beqzc(rs, branch_offset21_compact(L, false)>>2); |
| 698 } |
| 699 void bnezalc(Register rt, int16_t offset); |
| 700 void bnezalc(Register rt, Label* L) { |
| 701 bnezalc(rt, branch_offset_compact(L, false)>>2); |
| 702 } |
| 703 void bnec(Register rs, Register rt, int16_t offset); |
| 704 void bnec(Register rs, Register rt, Label* L) { |
| 705 bnec(rs, rt, branch_offset_compact(L, false)>>2); |
| 706 } |
| 707 void bnezc(Register rt, int32_t offset); |
| 708 void bnezc(Register rt, Label* L) { |
| 709 bnezc(rt, branch_offset21_compact(L, false)>>2); |
| 710 } |
625 void bne(Register rs, Register rt, int16_t offset); | 711 void bne(Register rs, Register rt, int16_t offset); |
626 void bne(Register rs, Register rt, Label* L) { | 712 void bne(Register rs, Register rt, Label* L) { |
627 bne(rs, rt, branch_offset(L, false)>>2); | 713 bne(rs, rt, branch_offset(L, false)>>2); |
628 } | 714 } |
| 715 void bovc(Register rs, Register rt, int16_t offset); |
| 716 void bovc(Register rs, Register rt, Label* L) { |
| 717 bovc(rs, rt, branch_offset_compact(L, false)>>2); |
| 718 } |
| 719 void bnvc(Register rs, Register rt, int16_t offset); |
| 720 void bnvc(Register rs, Register rt, Label* L) { |
| 721 bnvc(rs, rt, branch_offset_compact(L, false)>>2); |
| 722 } |
629 | 723 |
630 // Never use the int16_t b(l)cond version with a branch offset | 724 // Never use the int16_t b(l)cond version with a branch offset |
631 // instead of using the Label* version. | 725 // instead of using the Label* version. |
632 | 726 |
633 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits. | 727 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits. |
634 void j(int64_t target); | 728 void j(int64_t target); |
635 void jal(int64_t target); | 729 void jal(int64_t target); |
636 void jalr(Register rs, Register rd = ra); | 730 void jalr(Register rs, Register rd = ra); |
637 void jr(Register target); | 731 void jr(Register target); |
638 void j_or_jr(int64_t target, Register rs); | 732 void j_or_jr(int64_t target, Register rs); |
639 void jal_or_jalr(int64_t target, Register rs); | 733 void jal_or_jalr(int64_t target, Register rs); |
640 | 734 |
641 | 735 |
642 // -------Data-processing-instructions--------- | 736 // -------Data-processing-instructions--------- |
643 | 737 |
644 // Arithmetic. | 738 // Arithmetic. |
645 void addu(Register rd, Register rs, Register rt); | 739 void addu(Register rd, Register rs, Register rt); |
646 void subu(Register rd, Register rs, Register rt); | 740 void subu(Register rd, Register rs, Register rt); |
| 741 |
| 742 void div(Register rs, Register rt); |
| 743 void divu(Register rs, Register rt); |
| 744 void ddiv(Register rs, Register rt); |
| 745 void ddivu(Register rs, Register rt); |
| 746 void div(Register rd, Register rs, Register rt); |
| 747 void divu(Register rd, Register rs, Register rt); |
| 748 void ddiv(Register rd, Register rs, Register rt); |
| 749 void ddivu(Register rd, Register rs, Register rt); |
| 750 void mod(Register rd, Register rs, Register rt); |
| 751 void modu(Register rd, Register rs, Register rt); |
| 752 void dmod(Register rd, Register rs, Register rt); |
| 753 void dmodu(Register rd, Register rs, Register rt); |
| 754 |
| 755 void mul(Register rd, Register rs, Register rt); |
| 756 void muh(Register rd, Register rs, Register rt); |
| 757 void mulu(Register rd, Register rs, Register rt); |
| 758 void muhu(Register rd, Register rs, Register rt); |
647 void mult(Register rs, Register rt); | 759 void mult(Register rs, Register rt); |
648 void multu(Register rs, Register rt); | 760 void multu(Register rs, Register rt); |
649 void div(Register rs, Register rt); | 761 void dmul(Register rd, Register rs, Register rt); |
650 void divu(Register rs, Register rt); | 762 void dmuh(Register rd, Register rs, Register rt); |
651 void mul(Register rd, Register rs, Register rt); | 763 void dmulu(Register rd, Register rs, Register rt); |
| 764 void dmuhu(Register rd, Register rs, Register rt); |
652 void daddu(Register rd, Register rs, Register rt); | 765 void daddu(Register rd, Register rs, Register rt); |
653 void dsubu(Register rd, Register rs, Register rt); | 766 void dsubu(Register rd, Register rs, Register rt); |
654 void dmult(Register rs, Register rt); | 767 void dmult(Register rs, Register rt); |
655 void dmultu(Register rs, Register rt); | 768 void dmultu(Register rs, Register rt); |
656 void ddiv(Register rs, Register rt); | |
657 void ddivu(Register rs, Register rt); | |
658 | 769 |
659 void addiu(Register rd, Register rs, int32_t j); | 770 void addiu(Register rd, Register rs, int32_t j); |
660 void daddiu(Register rd, Register rs, int32_t j); | 771 void daddiu(Register rd, Register rs, int32_t j); |
661 | 772 |
662 // Logical. | 773 // Logical. |
663 void and_(Register rd, Register rs, Register rt); | 774 void and_(Register rd, Register rs, Register rt); |
664 void or_(Register rd, Register rs, Register rt); | 775 void or_(Register rd, Register rs, Register rt); |
665 void xor_(Register rd, Register rs, Register rt); | 776 void xor_(Register rd, Register rs, Register rt); |
666 void nor(Register rd, Register rs, Register rt); | 777 void nor(Register rd, Register rs, Register rt); |
667 | 778 |
668 void andi(Register rd, Register rs, int32_t j); | 779 void andi(Register rd, Register rs, int32_t j); |
669 void ori(Register rd, Register rs, int32_t j); | 780 void ori(Register rd, Register rs, int32_t j); |
670 void xori(Register rd, Register rs, int32_t j); | 781 void xori(Register rd, Register rs, int32_t j); |
671 void lui(Register rd, int32_t j); | 782 void lui(Register rd, int32_t j); |
| 783 void aui(Register rs, Register rt, int32_t j); |
| 784 void daui(Register rs, Register rt, int32_t j); |
| 785 void dahi(Register rs, int32_t j); |
| 786 void dati(Register rs, int32_t j); |
672 | 787 |
673 // Shifts. | 788 // Shifts. |
674 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop | 789 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop |
675 // and may cause problems in normal code. coming_from_nop makes sure this | 790 // and may cause problems in normal code. coming_from_nop makes sure this |
676 // doesn't happen. | 791 // doesn't happen. |
677 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); | 792 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); |
678 void sllv(Register rd, Register rt, Register rs); | 793 void sllv(Register rd, Register rt, Register rs); |
679 void srl(Register rd, Register rt, uint16_t sa); | 794 void srl(Register rd, Register rt, uint16_t sa); |
680 void srlv(Register rd, Register rt, Register rs); | 795 void srlv(Register rd, Register rt, Register rs); |
681 void sra(Register rt, Register rd, uint16_t sa); | 796 void sra(Register rt, Register rd, uint16_t sa); |
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744 void sltu(Register rd, Register rs, Register rt); | 859 void sltu(Register rd, Register rs, Register rt); |
745 void slti(Register rd, Register rs, int32_t j); | 860 void slti(Register rd, Register rs, int32_t j); |
746 void sltiu(Register rd, Register rs, int32_t j); | 861 void sltiu(Register rd, Register rs, int32_t j); |
747 | 862 |
748 // Conditional move. | 863 // Conditional move. |
749 void movz(Register rd, Register rs, Register rt); | 864 void movz(Register rd, Register rs, Register rt); |
750 void movn(Register rd, Register rs, Register rt); | 865 void movn(Register rd, Register rs, Register rt); |
751 void movt(Register rd, Register rs, uint16_t cc = 0); | 866 void movt(Register rd, Register rs, uint16_t cc = 0); |
752 void movf(Register rd, Register rs, uint16_t cc = 0); | 867 void movf(Register rd, Register rs, uint16_t cc = 0); |
753 | 868 |
| 869 void sel(SecondaryField fmt, FPURegister fd, FPURegister ft, |
| 870 FPURegister fs, uint8_t sel); |
| 871 void seleqz(Register rs, Register rt, Register rd); |
| 872 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister ft, |
| 873 FPURegister fs); |
| 874 void selnez(Register rs, Register rt, Register rd); |
| 875 void selnez(SecondaryField fmt, FPURegister fd, FPURegister ft, |
| 876 FPURegister fs); |
| 877 |
754 // Bit twiddling. | 878 // Bit twiddling. |
755 void clz(Register rd, Register rs); | 879 void clz(Register rd, Register rs); |
756 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); | 880 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); |
757 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); | 881 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); |
758 | 882 |
759 // --------Coprocessor-instructions---------------- | 883 // --------Coprocessor-instructions---------------- |
760 | 884 |
761 // Load, store, and move. | 885 // Load, store, and move. |
762 void lwc1(FPURegister fd, const MemOperand& src); | 886 void lwc1(FPURegister fd, const MemOperand& src); |
763 void ldc1(FPURegister fd, const MemOperand& src); | 887 void ldc1(FPURegister fd, const MemOperand& src); |
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803 void cvt_l_d(FPURegister fd, FPURegister fs); | 927 void cvt_l_d(FPURegister fd, FPURegister fs); |
804 void trunc_l_s(FPURegister fd, FPURegister fs); | 928 void trunc_l_s(FPURegister fd, FPURegister fs); |
805 void trunc_l_d(FPURegister fd, FPURegister fs); | 929 void trunc_l_d(FPURegister fd, FPURegister fs); |
806 void round_l_s(FPURegister fd, FPURegister fs); | 930 void round_l_s(FPURegister fd, FPURegister fs); |
807 void round_l_d(FPURegister fd, FPURegister fs); | 931 void round_l_d(FPURegister fd, FPURegister fs); |
808 void floor_l_s(FPURegister fd, FPURegister fs); | 932 void floor_l_s(FPURegister fd, FPURegister fs); |
809 void floor_l_d(FPURegister fd, FPURegister fs); | 933 void floor_l_d(FPURegister fd, FPURegister fs); |
810 void ceil_l_s(FPURegister fd, FPURegister fs); | 934 void ceil_l_s(FPURegister fd, FPURegister fs); |
811 void ceil_l_d(FPURegister fd, FPURegister fs); | 935 void ceil_l_d(FPURegister fd, FPURegister fs); |
812 | 936 |
| 937 void min(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs); |
| 938 void mina(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs); |
| 939 void max(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs); |
| 940 void maxa(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs); |
| 941 |
813 void cvt_s_w(FPURegister fd, FPURegister fs); | 942 void cvt_s_w(FPURegister fd, FPURegister fs); |
814 void cvt_s_l(FPURegister fd, FPURegister fs); | 943 void cvt_s_l(FPURegister fd, FPURegister fs); |
815 void cvt_s_d(FPURegister fd, FPURegister fs); | 944 void cvt_s_d(FPURegister fd, FPURegister fs); |
816 | 945 |
817 void cvt_d_w(FPURegister fd, FPURegister fs); | 946 void cvt_d_w(FPURegister fd, FPURegister fs); |
818 void cvt_d_l(FPURegister fd, FPURegister fs); | 947 void cvt_d_l(FPURegister fd, FPURegister fs); |
819 void cvt_d_s(FPURegister fd, FPURegister fs); | 948 void cvt_d_s(FPURegister fd, FPURegister fs); |
820 | 949 |
821 // Conditions and branches. | 950 // Conditions and branches for MIPSr6. |
| 951 void cmp(FPUCondition cond, SecondaryField fmt, |
| 952 FPURegister fd, FPURegister ft, FPURegister fs); |
| 953 |
| 954 void bc1eqz(int16_t offset, FPURegister ft); |
| 955 void bc1eqz(Label* L, FPURegister ft) { |
| 956 bc1eqz(branch_offset(L, false)>>2, ft); |
| 957 } |
| 958 void bc1nez(int16_t offset, FPURegister ft); |
| 959 void bc1nez(Label* L, FPURegister ft) { |
| 960 bc1nez(branch_offset(L, false)>>2, ft); |
| 961 } |
| 962 |
| 963 // Conditions and branches for non MIPSr6. |
822 void c(FPUCondition cond, SecondaryField fmt, | 964 void c(FPUCondition cond, SecondaryField fmt, |
823 FPURegister ft, FPURegister fs, uint16_t cc = 0); | 965 FPURegister ft, FPURegister fs, uint16_t cc = 0); |
824 | 966 |
825 void bc1f(int16_t offset, uint16_t cc = 0); | 967 void bc1f(int16_t offset, uint16_t cc = 0); |
826 void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); } | 968 void bc1f(Label* L, uint16_t cc = 0) { |
| 969 bc1f(branch_offset(L, false)>>2, cc); |
| 970 } |
827 void bc1t(int16_t offset, uint16_t cc = 0); | 971 void bc1t(int16_t offset, uint16_t cc = 0); |
828 void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); } | 972 void bc1t(Label* L, uint16_t cc = 0) { |
| 973 bc1t(branch_offset(L, false)>>2, cc); |
| 974 } |
829 void fcmp(FPURegister src1, const double src2, FPUCondition cond); | 975 void fcmp(FPURegister src1, const double src2, FPUCondition cond); |
830 | 976 |
831 // Check the code size generated from label to here. | 977 // Check the code size generated from label to here. |
832 int SizeOfCodeGeneratedSince(Label* label) { | 978 int SizeOfCodeGeneratedSince(Label* label) { |
833 return pc_offset() - label->pos(); | 979 return pc_offset() - label->pos(); |
834 } | 980 } |
835 | 981 |
836 // Check the number of instructions generated from label to here. | 982 // Check the number of instructions generated from label to here. |
837 int InstructionsGeneratedSince(Label* label) { | 983 int InstructionsGeneratedSince(Label* label) { |
838 return SizeOfCodeGeneratedSince(label) / kInstrSize; | 984 return SizeOfCodeGeneratedSince(label) / kInstrSize; |
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1258 class EnsureSpace BASE_EMBEDDED { | 1404 class EnsureSpace BASE_EMBEDDED { |
1259 public: | 1405 public: |
1260 explicit EnsureSpace(Assembler* assembler) { | 1406 explicit EnsureSpace(Assembler* assembler) { |
1261 assembler->CheckBuffer(); | 1407 assembler->CheckBuffer(); |
1262 } | 1408 } |
1263 }; | 1409 }; |
1264 | 1410 |
1265 } } // namespace v8::internal | 1411 } } // namespace v8::internal |
1266 | 1412 |
1267 #endif // V8_ARM_ASSEMBLER_MIPS_H_ | 1413 #endif // V8_ARM_ASSEMBLER_MIPS_H_ |
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